JBL Ms-A5001 Rev0 Car Amplifier SM
JBL Ms-A5001 Rev0 Car Amplifier SM
JBL Ms-A5001 Rev0 Car Amplifier SM
1 CHANNEL
Digital Signal Processing Amplifier
SERVICE MANUAL
- CONTENTS -
SPECIFICATIONS ………………………………………..1
PACKAGING…………..……………………………..…....2
CONTROL/INSTALLATION DRAWINGS………………3
CONTROL/INSTALLATION INSTRUCTIONS………....4
NOTE ON SETTINGS AND TESTING…..………………5
CONNECTIONS …..………………………………………6
DISPLAY………………………..………………………….9
EXPLODED VIEW/PARTS LIST…….….….……..……10
AMPLIFIER BLOCK DIAGRAMS………………….……11
P.C.B. DRAWINGS….………………………...…….……13
ELECTRICAL PARTS LIST ..……….….…….…….……23
IC/TRANSISTOR PINOUTS..…………………….….…..28
SCHEMATICS……………..………….…….………..…...72
MS-A5001 Specifications
JBL continually strives to update and improve existing products, as well as create new ones. The specifications and details in
this and related JBL publications are therefore subject to change without notice.
1
MS-A5001
NO PART NUMBER DESCRIPTION QTY
3 8 GIFT LABEL 1
9 5 6 .1 8 .TIN Y1R5001 CARTON LABEL 1
10 CE LABEL 1
11 272-3 8 .1 1 2 .TINY2 SETUP C
CDD 1
14 12 visit www.jbl.com MANUAL
OWNER'S MANUAL 1
13 PLASTIC BAG 2
14 6 5 .1 .2 R 5 2 0 2.5mm ALLEN WRENCH 1
15
15 6 5 .1 .0 4 2 0 4.0 mm ALLEN WRENCH 1
16 2 6 .1 2 1 .1 1 2 1 0 1 RCA R
toCbare
A (BLACK) TACK
wire Adapters 4
6 17 56.15.MSA50010 LABEL 1
16 13
17
4
IC: 6132C-MSA5001AS
This device complies with part 15 of the
FCC Rules. Operation is subject to the
following two conditions:
(1) This device may not cause harmful
interference, and
(2) this device must accept any interference
received, including interference that may
cause undesired operation.
Harman consumer,Inc
Made in China
MADE IN CHINA
TINY
2010.06.24 MP-10D5-0076
8
5
9
2
MS-A5001
3 4 2 1
Lo Hi Hi2 Level
Input
Input 1 1 1
Input Output
3
2
2 2
Inpu 1
t
2 Lo
Hi
Hi2
Inpu Le
t
1
Outp
ut
2
40 A
2X40A
40 A
8 9 10 11
1 x 80A
- +
10 11
3
MS-A5001
1 4 9
5
10
2
6
11
7
3
4
MS-A5001
http://www.jbl.com/EN-
US/Support/Pages/ProductSelector.aspx
5
MS-A5001
1 x 80A
- +
Input 1
2 Lo
Hi
Hi2
Input Le
1
Outpu
t
2
Inpu 1
t
2
6
MS-A5001
1,2
24dB Hz Hz 24dB
1,2
1,2
24dB Hz Hz 24dB
1,2
7
MS-A5001
24dB Hz Hz 24dB
24dB Hz Hz 24dB
8
MS-A5001
1 2 3 4 5 6 7 8
1
1,2 6dB 6dB
12dB 12dB
24dB kHz kHz 24dB
1,2
!
11 10 9
1 5 9
2 6 7 10
!
1 6dB
1,2 12dB
kHz 24dB
3 4 8 11
6dB
12dB
24dB kHz
9
MS-A5001
10
MS-A5001
11
MS-A5001
DC 12V
Flexible
REM_IN_ACT
PWREN
VCC
VEE
VBIAS
VCAR
HEVN
GND
GND
Main Amp
Tramsmit
WBC
3V
Power Regulator Receive
(TDA3681) u-Control
PWREN
Auto OCP, OTP
Sense
VCC
VEE
Head Unit
VBIAS
VDIF,+8P5VA, 5V-ON 3P3V-ON 5V-ON
Lo -8P5VA
12
MS-A5001
13
MS-A5001
14
MS-A5001
15
MS-A5001
16
MS-A5001
17
MS-A5001
18
MS-A5001
19
MS-A5001
20
MS-A5001
21
MS-A5001
22
MS-A5001
MS-A5001 Electrical Parts List
PREAMP/INPUT PCB
Semiconductors
Resistors
23
MS-A5001
Part Number Description Qty Reference Designator or Application
PREAMP/INPUT PCB
Capacitors
24
MS-A5001
Part Number Description Qty Reference Designator or Application
PREAMP/INPUT PCB
Miscellaneous
POWER PCB
Semiconductors
Resistors
25
MS-A5001
Part Number Description Qty Reference Designator or Application
POWER PCB
Capacitors
Miscellaneous
DISPLAY PCB
Semiconductors
Resistors
26
MS-A5001
Part Number Description Qty Reference Designator or Application
DISPLAY PCB
Capacitors
CAP050104-0603 SMD Capacitor CAP, SM 104PF 50V 10% 0603 2 C502 C503
CAP050104-0805 SMD Capacitor SMD"0805" 50V 10% 104P 2 C1,3
CAP0310102-10 SMD EL Capacitor ELECTROLYTIC"MVG/SC" 20%, 10Φ1000uF/10V 1 C6
CAP0325220-4 SMD EL Capacitor ELECTROLYTIC"CHIP""SC/MV"5PHI22uF/25V 1 C2
Miscellaneous
MECHANICAL/MISCELLANEOUS
27
MS-A5001
Philips Semiconductors Product specification
ORDERING INFORMATION
TYPE PACKAGE
NUMBER NAME DESCRIPTION VERSION
TDA3681J DBS17P plastic DIL-bent-SIL power package; 17 leads (lead length 7.7 mm) SOT243-3
TDA3681JR DBS17P plastic DIL-bent-SIL (special bent) power package; 17 leads SOT475-1
(lead length 12 mm)
TDA3681TH HSOP20 plastic, heatsink small outline package; 20 leads; low stand-off height SOT418-2
28
MS-A5001
Philips Semiconductors Product specification
8 TEMPERATURE
ENSW & LOAD DUMP
PROTECTION
(14 V/
BACKUP SWITCH 13 100 mA)
BU
BACKUP CONTROL
(5 V/
12 300 mA)
REGULATOR 2 REG2
20
VP2
(3.3 V/
1 1 A)
REGULATOR 4 REG4
&
6
EN4
11
HEATTAB (5 V/
n.c. 15 19 1400 mA)
REGULATOR 3 REG3
18 &
n.c.
TDA3681TH
(8.5 V/
17 600 mA)
REGULATOR 1 REG1
&
7
EN1/3
9
HOLD
+
OR
&
4
RES
5
CRES
2 3
IGNIN IGNITION BUFFER IGNOUT
10
MGU353
GND
29
MS-A5001
Philips Semiconductors Product specification
Note
1. The pin is used for final test purposes. In the
application it should be connected directly to ground.
30
MS-A5001
MC9S08GT16A/GT8A Features
8-Bit HCS08 Central Processor Unit (CPU) • Software selectable pullups on ports when used as
input
• 40-MHz HCS08 CPU • Internal pullup on RESET and IRQ pin to reduce
• HC08 instruction set with added BGND instruction customer system cost
• Support for up to 32 interrupt/reset sources • Up to 38 general-purpose input/output (I/O) pins,
plus one output-only pin, depending on package
Memory Options selection
• FLASH read/program/erase down to 1.8 V Development Support
• Up to 16K FLASH; up to 2K RAM
• Background debugging system
Power-Saving Modes • Breakpoint capability to allow single breakpoint
setting during in-circuit debugging (plus two more
• Three very low power stop modes breakpoints in on-chip debug module)
• Reduced power wait mode • On-chip, in-circuit emulation (ICE) debug module
• Very low power real time interrupt for use in run, with real-time bus capture. On-chip ICE debug
wait, and stop module containing two comparators and nine trigger
modes. Eight deep FIFO for storing change-of-flow
Clock Source Options
addresses and event-only data.
• Clock sources to internal hardware frequency • Single-wire background debug interface
locked-loop (FLL): internal, external, crystal, or
Package Options
resonator
• Internal clock with ±0.2% trimming resolution and • 48-pin QFN
±0.5% deviation across voltage or across • 44-pin QFP
temperature
• 42-pin PSDIP
System Protection • 32-pin QFN
Peripherals
Input/Output
31
MS-A5001
Device Overview
VREFH
VREFL
VSSAD
VDDAD
4
8 PTA7/KBIP7–
PORT A
HCS08 CORE 8-BIT KEYBOARD PTA4/KBIP4 NOTE 6
INTERRUPT (KBI) 4
BKGD PTA3/KBIP3–
PTA0/KBIP0
CPU BDC
4
PTB7/ADP7–
PORT B
10-BIT 8 PTB4/ADP4
ANALOG-TO-DIGITAL 4
HCS08 SYSTEM CONTROL CONVERTER (ATD) PTB3/ADP3–
RESET PTB0/ADP0
NOTE 4 RESETS AND INTERRUPTS
MODES OF OPERATION PTC7
POWER MANAGEMENT PTC6
PTC5
PTC4
PORT C
SCL NOTE 5
RTI COP PTC3/SCL
INTER-IC (IIC) SDA
PTC2/SDA
IRQ IRQ LVD
RXD2
NOTES 2, 3 SERIAL COMMUNICATIONS PTC1/RxD2
TXD2 PTC0/TxD2
INTERFACE (SCI2)
PORT D
CH0
PTD2/TPM1CH2
3-CHANNEL TIMER/PWM CH1 PTD1/TPM1CH1
(TPM1) CH2 PTD0/TPM1CLK/TPM1CH0
USER RAM
(GT16A = 2048 BYTES)
(GT8A = 1024 BYTES) SPSCK PTE5/SPSCK
MOSI
SERIAL PERIPHERAL PTE4/MOSI
MISO PTE3/MISO
INTERFACE (SPI)
PORT E
SS PTE2/SS
ON-CHIP ICE
DEBUG
RXD1
MODULE (DBG) SERIAL COMMUNICATIONS PTE1/RxD1
TXD1 PTE0/TxD1
INTERFACE (SCI1)
INTERNAL CLOCK
GENERATOR (ICG)
PTG3
EXTAL
PORT G
PTG2/EXTAL
XTAL PTG1/XTAL
LOW-POWER OSCILLATOR
BKGD PTG0/BKGD/MS
VDD
VOLTAGE
VSS
REGULATOR = Pins not available in 44-, 42-, or 32-pin packages
VSS = Pins not available in 42- or 32-pin packages
= Pins not available in 32-pin packages
NOTES:
1. Port pins are software configurable with pullup device if input port.
2. Pin contains pullup/pulldown device if IRQ enabled (IRQPE = 1).
3. IRQ does not have a clamp diode to VDD. IRQ should not be driven above VDD.
4. Pin contains integrated pullup device.
5. High current drive
6. Pins PTA[7:4] contain both pullup and pulldown devices. Pulldown available when KBI enabled (KBIPn = 1).
32
MS-A5001
Device Overview
Module Version
ICGOUT BUSCLK
÷2
ICGLCLK*
33
MS-A5001
Chapter 2
Pins and Connections
2.1 Introduction
This section describes signals that connect to package pins. It includes a pinout diagram, a table of signal
properties, and detailed discussion of signals.
PTG0/BKGD/MS
PTG2/EXTAL
PTA5/KBIP5
PTA4/KBIP4
PTA2/KBIP2
PTA7/KBIP7
PTA6/KBIP6
PTA3/KBIP3
PTG1/XTAL
VDDAD
VSSAD
43
42
41
40
44
39
38
37
36
35
34
RESET 1 33 PTA1/KBIP1
PTC0/TxD2 2 32 PTA0/KBIP0
PTC1/RxD2 3 31 VREFL
PTC2/SDA 4 30 VREFH
PTC3/SCL 5 29 PTB7/ADP7
PTC4 6 28 PTB6/ADP6
PTC5 7 27 PTB5/ADP5
PTC6 8 26 PTB4/ADP4
PTE0/TxD1 9 25 PTB3/ADP3
PTE1/RxD1 10 24 PTB2/ADP2
IRQ 11 23 PTB1/ADP1
22
13
14
15
16
17
18
19
20
21
12
PTE2/SS
PTE3/MISO
PTE5/SPSCK
VSS
VDD
PTD0/TPM1CLK/TPM1CH0
PTD1/TPM1CH1
PTD3/TPM2CLK/TPM2CH0
PTD4/TPM2CH1
PTB0/ADP0
PTE4/MOSI
34
MS-A5001
Figure 2-5 shows pin connections that are common to almost all MC9S08GT16A application systems. A
more detailed discussion of system connections follows.
VREFH PTA0/KBIP0
VDDAD MC9S08GT16A PTA1/KBIP1
CBYAD
PTA2/KBIP2
0.1 µF
PTA3/KBIP3
VSSAD PORT
SYSTEM VDD A PTA4/KBIP4
VREFL
POWER PTA5/KBIP5
VDD
+ PTA6/KBIP6
3V CBLK + CBY
10 µF 0.1 µF PTA7/KBIP7
VSS
NOTE4 PTB0/ADP0
VSS
PTB1/ADP1
BACKGROUND HEADER
PTB2/ADP2
BKGD/MS PORT PTB3/ADP3
VDD
B PTB4/ADP4
VDD PTB5/ADP5
I/O AND
PTB6/ADP6
4.7 kΩ–10 kΩ PERIPHERAL
PTB7/ADP7
RESET INTERFACE TO
0.1 µF NOTE 3 PTC0/TxD2
PTC1/RxD2 APPLICATION
OPTIONAL
MANUAL VDD PTC2/SDA
SYSTEM
RESET PORT PTC3/SCL
4.7 kΩ–10 kΩ C PTC4
ASYNCHRONOUS
INTERRUPT PTC5
IRQ
INPUT 0.1 µF NOTE 3 PTC6
PTC7
PTD0/TPM1CLK/TPM1CH0
PTG0/BKDG/MS
PTD1/TPM1CH1
PTG1/XTAL PORT PORT PTD2/TPM1CH2
PTG2/EXTAL G D
PTD3/TPM2CLK/TPM2CH0
PTG3
PTD4/TPM2CH1
NOTE 1 RF
RS XTAL PTE0/TxD1
PTE1/RxD1
C1 X1 C2 PTE2/SS
PORT
E PTE3/MISO
EXTAL
PTE4/MOSI
PTE5/SPSCK
NOTES:
1. Not required if using the internal oscillator option.
2. The 48-pin QFN has 2 VSS pins (VSS1 and VSS2), both of which must be connected to GND.
3. RC filters on RESET and IRQ are recommended for EMC-sensitive applications and systems.
35
MS-A5001
TPS77001, TPS77012, TPS77015, TPS77018, TPS77025
TPS77027, TPS77028, TPS77030, TPS77033, TPS77050
ULTRA LOW-POWER 50-mA LOW-DROPOUT LINEAR REGULATORS
SLVS210C – JUNE 1999 – REVISED SEPTEMBER 1999
description
The TPS770xx family of low-dropout (LDO) voltage regulators offers the benefits of low dropout voltage, ultra
low-power operation, and miniaturized packaging. These regulators feature low dropout voltages and ultra low
quiescent current compared to conventional LDO regulators. Offered in a 5-terminal small outline
integrated-circuit SOT-23 package, the TPS770xx series devices are ideal for micropower operations and
where board space is at a premium.
A combination of new circuit design and process innovation has enabled the usual PNP pass transistor to be
replaced by a PMOS pass element. Because the PMOS pass element behaves as a low-value resistor, the
dropout voltage is very low — typically 35 mV at 50 mA of load current (TPS77050) — and is directly proportional
to the load current. Since the PMOS pass element is a voltage-driven device, the quiescent current is ultra low
(28 µA maximum) and is stable over the entire range of output load current (0 mA to 50 mA).
Intended for use in portable systems such as
laptops and cellular phones, the ultra low-dropout TPS77033
voltage feature and ultra low-power operation GROUND CURRENT
result in a significant increase in system battery vs
operating life. FREE-AIR TEMPERATURE
The TPS770xx also features a logic-enabled 22
sleep mode to shut down the regulator, reducing VI = 4.3 V
quiescent current to 1 µA typical at TJ = 25°C. The 21 CO = 4.7 µF
TPS770xx is offered in 1.2-V, 1.5-V, 1.8-V, 2.5-V,
2.7-V, 2.8-V, 3.0-V, 3.3-V, and 5-V fixed-voltage 20
Ground Current – µ A
IO = 50 mA IO = 0 mA
18
17
16
15
–60 –40 –20 0 20 40 60 80 100 120 140
TA – Free-Air Temperature – °C
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright 1999, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
36
MS-A5001
6276
Data Sheet
26185.201
16-BIT SERIAL-INPUT, CONSTANT-
CURRENT LATCHED LED DRIVER
A6276ELW
The A6276EA and A6276ELW are specifically designed for LED-
display applications. Each BiCMOS device includes a 16-bit CMOS
GROUND 1 VDD 24
LOGIC shift register, accompanying data latches, and 16 npn constant-current
SUPPLY
SERIAL IO
sink drivers. Except for package style and allowable package power
2 23 REXT
DATA IN REGULATOR
dissipation, the two devices are identical.
SERIAL
CLOCK 3 CK 22 DATA OUT
LATCH 4 L OE 21 OUTPUT The CMOS shift register and latches allow direct interfacing with
ENABLE ENABLE
REGISTER
microprocessor-based systems. With a 5 V logic supply, typical serial
OUT 0 5 LATCHES 20 OUT 15
data-input rates are up to 20 MHz. The LED drive current is deter-
OUT 1 6 19 OUT 14
mined by the user’s selection of a single resistor. A CMOS serial data
OUT 2 7 18 OUT 13 output permits cascade connections in applications requiring additional
OUT 3 8 17 OUT 12
drive lines. For inter-digit blanking, all output drivers can be disabled
with an ENABLE input high. Similar 8-bit devices are available as the
OUT 4 9 16 OUT 11
A6275EA and A6275ELW.
OUT 5 10 15 OUT 10
OUT 6 11 14 OUT 9 Two package styles are provided for through-hole DIP (suffix A) or
surface-mount SOIC (suffix LW). Under normal applications, a copper
OUT 7 12 13 OUT 8
lead frame and low logic-power dissipation allow the dual in-line
Dwg. PP-029-11 package to sink maximum rated current through all outputs continu-
Note that the A6276EA (DIP) and the A6276ELW ously over the operating temperature range (90 mA, 0.75 V drop,
(SOIC) are electrically identical and share a
common terminal number assignment. +85°C). Both devices are also available for operation over the standard
ABSOLUTE MAXIMUM RATINGS temperature range of -20°C to +85°C. To order, change the suffix
letter ‘E’ to ‘S’.
Supply Voltage, VDD ...................... 7.0 V
Output Voltage Range,
FEATURES
VO ............................ -0.5 V to +17 V
Output Current, IO ........................ 90 mA
Ground Current, IGND ............... 1475 mA ■ To 90 mA Constant-Current Outputs
Input Voltage Range, ■ Under-Voltage Lockout
VI .................... -0.4 V to VDD + 0.4 V
■ Low-Power CMOS Logic and Latches
Package Power Dissipation,
PD ..................................... See Graph ■ High Data Input Rate
Operating Temperature Range, ■ Functional Replacement for TB62706BN/BF
TA ............................. -40°C to +85°C
Storage Temperature Range,
TS ........................... -55°C to +150°C
Caution: These CMOS devices have input
static protection (Class 2) but are still suscep-
tible to damage if exposed to extremely high
static electrical charges. Always order by complete part number, e.g., A6276EA .
37
MS-A5001
6276
16-BIT SERIAL-INPUT,
CONSTANT-CURRENT
LATCHED LED DRIVER
2.5
ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS
1.5
1.0
0.5
0
25 50 75 100 125 150
AMBIENT TEMPERATURE IN °C
Dwg. GP-022-3
VDD
LOGIC
UVLO
CLOCK SUPPLY
SERIAL SERIAL
SERIAL-PARALLEL SHIFT REGISTER
DATA IN DATA OUT
LATCH
LATCHES
ENABLE
OUTPUT ENABLE
GROUND (ACTIVE LOW)
MOS
BIPOLAR
IO R
EXT
REGULATOR
38
MS-A5001
6276
16-BIT SERIAL-INPUT,
CONSTANT-CURRENT
LATCHED LED DRIVER
VDD VDD
IN IN
Dwg. EP-010-7
Dwg. EP-010-6
VDD VDD
IN OUT
Dwg. EP-063-1
Dwg. EP-010-5
TRUTH TABLE
Serial Shift Register Contents Serial Latch Latch Contents Output Output Contents
Data Clock Data Enable Enable
Input Input I1 I2 I3 ... IN-1 IN Output Input I1 I2 I3 ... IN-1 IN Input I1 I2 I3 ... IN-1 IN
X X X ... X X H H H H ... H H
L = Low Logic (Voltage) Level H = High Logic (Voltage) Level X = Irrelevant P = Present State R = Previous State
3
39
MS-A5001
MIC2981/2982 Micrel, Inc.
MIC2981/2982
High-Voltage High-Current Source Driver Array
General Features
The MIC2981/82 is an 8-channel, high-voltage, high-current • Output voltage to 50V
source driver array ideal for switching high-power loads from • Output current to 500mA
logic-level TTL, CMOS, or PMOS control signals. • Transient-protected outputs
These drivers can manage multiple loads of up to 50V and • Integral clamp diodes
500mA, limited only by package power dissipation. • TTL, CMOS, or PMOS compatible inputs
Micrel’s MIC2981/82 features inputs compatible with 5V TTL Applications
and 5V to 15V CMOS or PMOS logic outputs. Micrel’s • Relay and solenoid switching
dual-marked device replaces either UDN2981 or UDN2982 • Stepping motor
devices. • LED and incandescent displays
The MIC2981/82 is available in the 18-pin plastic DIP and
18-lead wide SOP package. Both devices operate in the
industrial temperature range.
Ordering Information
Part Number
Reference Manufacturing* PbFree Temperature Range Package
MIC2981BN** MIC2981/82BN MIC2981/82YN –40ºC to +85ºC 18-pin DIP
MIC2982BN** MIC2981/82BN MIC2981/82YN –40ºC to +85ºC 18-pin DIP
MIC2981BWM** MIC2981/82BWM MIC2981/82YWM –40ºC to +85ºC 18-pin wide SOP
MIC2982BWM** MIC2981/82BWM MIC2981/82YWM –40ºC to +85ºC 18-pin wide SOP
* Order entry P/N.
**Orders for MIC2981BN or MIC2982BN will be filled with dual-marked MIC2981/82BN.
**Orders for MIC2981YN or MIC2982YN will be filled with dual-marked MIC2981/82YN.
**Orders for MIC2981BWM or MIC2982BWM will be filled with dual-marked MIC2981/82BWM.
**Orders for MIC2981YWM or MIC2982YWM will be filled with dual-marked MIC2981/82YWM.
Functional Diagrams
IN1 OUT1
VS
IN2 OUT2
20k
IN3 OUT3
1.8k
IN4–IN7 4 OUT4–OUT7 IN
800
GND
VS GND
MIC2981 Typical MIC2891/2982 Source Driver
MIC2982
40
MS-A5001
Pin Configuration
IN1 1 18 OUT1
IN2 2 17 OUT2
IN3 3 16 OUT3
IN4 4 15 OUT4
IN5 5 14 OUT5
IN6 6 13 OUT6
IN7 7 12 OUT7
IN8 8 11 OUT8
VS 9 10 GND
Pin Description
Pin No. Pin No. Pin Name Pin Function
1–8 IN1–IN8 Input 1 through Input 8: Base drive to driver input transistor.
9 VS Supply Input
10 GND Ground
11–18 OUT8–OUT1 Output 8 through Output 1: Emitter of Darlington driver output.
41
MS-A5001
TYPICAL
SYMBOL PARAMETER CONDITIONS UNIT
HC HCT
tPHL/ tPLH propagation delay CL = 15 pF; VCC = 5 V
An to Yn 14 18 ns
E3 to Yn 16 20 ns
En to Yn 17 21 ns
CI input capacitance 3.5 3.5 pF
CPD power dissipation capacitance per package notes 1 and 2 72 76 pF
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
∑ (CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC − 1.5 V
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
42
MS-A5001
PIN DESCRIPTION
(a)
(b)
43
MS-A5001
FUNCTION TABLE
INPUTS OUTPUTS
E1 E2 E3 A0 A1 A2 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
H X X X X X L L L L L L L L
X H X X X X L L L L L L L L
X X L X X X L L L L L L L L
L L H L L L H L L L L L L L
L L H H L L L H L L L L L L
L L H L H L L L H L L L L L
L L H H H L L L L H L L L L
L L H L L H L L L L H L L L
L L H H L H L L L L L H L L
L L H L H H L L L L L L H L
L L H H H H L L L L L L L H
Note
1. H = HIGH voltage level
L = LOW voltage level
X = don’t care
44
MS-A5001
PACKAGES
TYPE NUMBER TEMPERATURE
PINS PACKAGE MATERIAL CODE MARKING
RANGE
74AHC1G04GW 5 SC-88A plastic SOT353 AC
−40 to +85 °C
74AHCT1G04GW 5 SC-88A plastic SOT353 CC
45
MS-A5001
Philips Semiconductors Product specification
handbook, halfpage
n.c. 1 5 VCC
handbook, halfpage
inA 2 2 inA outY 4
04
GND 3 4 outY
MNA108
MNA107
handbook, halfpage 1
2 4 handbook, halfpage
inA outY
MNA110
MNA109
46
MS-A5001
STA309A
Features
! 8 channels of 24-bit DDX® TQFP64
! >100 dB SNR and dynamic range
! Selectable 32 kHz - 192 kHz input sample rates ! Advanced PopFree operation
! 6 channels of DSD/SACD input ! Advanced AM interference frequency
! Digital gain/attenuation +58 dB to -100 dB in switching and noise suppression modes
0.5 dB steps ! I2S output channel mapping function
! Soft volume update ! Independent channel volume and DSP bypass
! Individual channel and master gain/attenuation ! Channel mapping of any input to any
plus channel trim (-10 dB to +10 dB) processing/DDX® channel
! Up to 10 independent 32-bit user ! DC blocking selectable high-pass filter
programmable biquads (EQ) per channel
! Selectable per-channel DDX® damped ternary
! Bass/treble tone control or binary PWM output
! Pre and post EQ full 8-channel input mix on all ! Max power correction for lower full-power THD
8 channels
! Variable per channel DDX® output delay control
! Dual independent limiters/compressors
! 192 kHz internal processing sample rate, 24-bit
! Dynamic range compression or anti-clipping to 36-bit precision
modes
! AutoModes: Description
– 5-band graphic EQ
– 32 preset EQ curves (rock, jazz, pop, etc.) The STA309A is a single chip solution for digital
– Automatic volume controlled loudness audio processing and control in multi-channel
applications. It provides output capabilities for
– 5.1 to 2-channel downmix
DDX® (direct digital amplification). In conjunction
– Simultaneous 5.1- and 2-channel downmix with a DDX® power device, it provides high-
outputs quality, high-efficiency, all digital amplification.
– 3 preset volume curves The device is extremely versatile, allowing for
– 2 preset anti-clipping modes input of most digital formats including 6.1/7.1-
– Preset movie nighttime listening mode channel and 192 kHz, 24-bit DVD-audio,
– Preset TV channel/commercial AGC mode DSD/SACD. In 5.1 application the additional 2
channels can be used for audio line-out or
– 5.1, 2.1 bass management configurations
headphone drive. In speaker mode, with 8
– AM frequency automatic output PWM channel outputs in parallel, the STA309A can
frequency shifting deliver more than 1 W.
– 8 preset crossover filters
! Individual channel and master soft/hard mute Table 1. Device summary
! Automatic zero-detect and invalid input mute Order code Package
! Automatic invalid input detect mute STA309A TQFP64
47
MS-A5001
STA309A Block diagram
1 Block diagram
OUT1A/B
LRCKI
BICKI I2C OUT2A/B
SERIAL OVERSAMPLING OUT3A/B
SDI12 DATA OUT4A/B
SDI34 DDX
IN SYSTEM OUT5A/B
SDI56 CONTROL
OUT6A/B
SDI78
OUT7A/B
OUT8A/B
VARIABLE TREBLE, VOLUME
CHANNEL
OVER- BASS, EQ LIMITING
MAPPING LRCKO
SAMPLING (BIQUADS)
BICKO
SERIAL
SDO12
SYSTEM TIMING DATA
OUT SDO34
PLLB PLL VARIABLE
POWER SDO56
DOWN DOWN-
SAMPLING SDO78
Interp_Rate
8 Inputs
From I2S 1x,2x,4x Mapping/ Biquads Volume 2x
Mix #2
Interp DSDE Mix #1 B/T Limiter Interp
DDX
Distortion Output
Compensation NS C_Con PWM
From To
Mix#1 Mix#2
Engine Engine
High-Pass Biquad Biquad Biquad Biquad Biquad Biquad Biquad
Or PreScale Bass Treble
Filter #2 #3 #4 #5 #6 #7 #8
Previous
Channel
Biquad#10
Output
(CxBLP)
Hard Set Hard Set User Programmable
Hard Set to User Progammable Hard Set Coeffecients when AutoMode EQ
Coeffecients when Coeffecients when Biquads #9 and #10
-18dB when Biquad #1 when (AMEQ)
AutoMode DeEmphasis When Tone Bypassed
AutoMode EQ High-Pass Bypassed
Bass Management Enabled (CxTCB)
(AMEQ) (HPB)
Crossover (DEMP)
(AMBMXE)
9/67
48
MS-A5001
Pin connections STA309A
2 Pin connections
OUT1_A
OUT1_B
SDO_78
SDO_56
SDO_34
SDO_12
LRCKO
BICKO
PWDN
EAPD
GND
GND
VDD
VDD
NC
NC
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
MVO 1 48 OUT2_A
GND 2 47 OUT2_B
VDD 3 46 NC
GND 4 45 GND
NC 5 44 VDD
SDI_78 6 43 OUT3_A
SDI_56 7 42 OUT3_B
SDI_34 8 41 OUT4_A
SDI_12 9 40 OUT4_B
LRCKI 10 39 OUT5_A
BICKI 11 38 OUT5_B
VDD 12 37 NC
GND 13 36 GND
NC 14 35 VDD
RESET 15 34 OUT6_A
PLLB 16 33 OUT6_B
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
NC
GNDA
VDDA
CKOUT
NC
GND
VDD
OUT8_B
OUT8_A
OUT7_B
OUT7_A
SA
SDA
SCL
XTI
FILTER_PLL
STA308APINCON
10/67
49
MS-A5001
11/67
50
MS-A5001
Pin connections STA309A
12/67
51
MS-A5001
Block Diagrams
BA CC0WFP/ BA DD0WHFP/ BA CC0WT(V5)/ BA DD0WT
GND
Fin
(TO252-5 HRP5)
Vcc FIN
TOP VIEW
1 2 3 4 5
Fin GND GND
2 Only for TO252-5 and HRP5
*2
CTL Vcc N.C. OUT N.C. 1 TO252-5 is N.C.,and TO220FP-5,-5(V5),and HRP5 are GND
(TO252-5)
GND 1 2 3 45 1 2 3 45
(TO220FP-5,-5(V5),HRP5)
TO220FP-5 TO220FP-5 V5
Fig.25
OVP TSD OCP
R1
1 2 3
1 TO252-3 is N.C.,and TO-220FP-3,is GND
2 Only for TO252-3 and HRP5
1 2 3
TO252-3 TO220FP-3
1 2 3
Vcc N.C. OUT
(TO252-3)
GND
(TO220FP-3)
Fig.26
Vcc
Vcc Vcc
39k 2k
10k CTL
25k
OUT
CTL OUT
25k
31k R2
R2
R1 R1
Fig.27 Fig.28
52
MS-A5001
PRODUCT SPECIFICATION
Q5)6LQJOH&KLS*+]5DGLR7UDQVFHLYHU
• True single chip GFSK transceiver in a small • Wireless mouse, keyboard, joystick
24-pin package (QFN24 5x5mm) • Keyless entry
• Data rate 0 to1Mbps • Wireless data communication
• Only 2 external components • Alarm and security systems
• Multi channel operation • Home automation
• 125 channels • Home automation
• Channel switching time <200µs. • Surveillance
• Support frequency hopping • Automotive
• Data slicer / clock recovery of data • Telemetry
• Address and CRC computation • Intelligent sports equipment
• DuoCeiver™ for simultaneous dual receiver • Industrial sensors
topology • Toys
• ShockBurst™ mode for ultra-low power
operation and relaxed MCU performance
• Power supply range: 1.9 to 3.6 V
• Low supply current (TX), typical 10.5mA peak
@ -5dBm output power
• Low supply current (RX), typical 18mA peak in
receive mode
• 100% RF tested
• No need for external SAW filter
• World wide use
*(1(5$/'(6&5,37,21
nRF2401 is a single-chip radio transceiver for the world wide 2.4 - 2.5 GHz ISM
band. The transceiver consists of a fully integrated frequency synthesizer, a power
amplifier, a crystal oscillator and a modulator. Output power and frequency channels
are easily programmable by use of the 3-wire serial interface. Current consumption is
very low, only 10.5mA at an output power of -5dBm and 18mA in receive mode.
Built-in Power Down modes makes power saving easily realizable.
48,&.5()(5(1&('$7$
3DUDPHWHU 9DOXH 8QLW
Minimum supply voltage 1.9 V
Maximum output power 0 dBm
Maximum data rate 1000 kbps
Supply current in transmit @ -5dBm output power 10.5 mA
Supply current in receive mode 18 mA
Temperature range -40 to +85 °C
Sensitivity -90 dBm
Supply current in Power Down mode 1 µΑ
53
MS-A5001
PRODUCT SPECIFICATION
Q5)6LQJOH&KLS*+]5DGLR7UDQVFHLYHU
%/2&.',$*5$0
VDD=3V
VDD=3V
VSS=0V
VSS=3V
VSS=0V
VSS=0V
VSS=0V
DVDD
XC1
PWR_UP
DuoCeiverTM
VSS=0V XC2
ShockBurstTM
VSS_PA=0V
DEMOD
IF BPF
VDD_PS=1.8V
CE LNA
Clock
Recovery,
DR2
DataSlicer
Data DOUT2 ADDR
Channel 2 Decode
CLK2
CRC Frequency
Code/Decode Synthesiser
DR1 FIFO
In/Out
Data DATA
Channel 1 ANT1
CLK1
GFSK
PA 400Ω
3-wire Filter
ANT2
interface
CS IREF
22kΩ
54
MS-A5001
PRODUCT SPECIFICATION
Q5)6LQJOH&KLS*+]5DGLR7UDQVFHLYHU
3,1)81&7,216
3,1$66,*10(17
24 23 22 21 20 19
CE 1 18 VSS
Q5)
DR2 2 17 VDD
QFN24 5x5
CLK2 3 16 VSS_PA
DOUT2 4 15 ANT2
CS 5 14 ANT1
DR1 6 13 VDD_PA
7 8 9 10 11 12
CLK1 DATA DVDD VSS XC2 XC1
Figure 2. nRF2401 pin assignment (top view) for a QFN24 5x5 package.
55
MS-A5001
ASAHI KASEI [AK5384]
AK5384
107dB 24-Bit 96kHz 4-Channel ADC
GENERAL DESCRIPTION
The AK5384 is a 4-channel A/D Converter with wide sampling rate of 8kHz ∼ 96kHz and is suitable for
Multi-channel audio system. The AK5384 achieves high accuracy and low cost by using Enhanced dual
bit ∆Σ techniques. The AK5384 supports master mode and TDM format. Therefore, the AK5384 is
suitable for multi-channel audio system.
FEATURES
ο 4-Channel ∆Σ ADC
ο Differential Inputs
ο Digital HPF for DC-Offset Cancel
ο S/(N+D): 100dB@5V for 48kHz
ο DR: 107dB@5V for 48kHz
ο S/N: 107dB@5V for 48kHz
ο Sampling Rate Ranging from 8kHz to 96kHz
ο Master Clock:
256fs/384fs/512fs/768fs (∼ 48kHz)
256fs/384fs (∼ 96kHz)
ο TTL Digital Input Level
ο Output format: 24bit MSB justified, I2S or TDM
ο Cascade TDM Interface
ο Master & Slave Mode
ο Overflow Flag
ο Power Supply: 4.75 to 5.25V
ο Power Supply for output buffer: 3.0 to 5.25V
ο Ta = −40 ∼ 85°C
ο 28pin VSOP
AVDD AVSS DVDD DVSS TVDD
MS0225-E-00 2003/05
-1-
56
MS-A5001
ASAHI KASEI [AK5384]
ν Ordering Guide
ν Pin Layout
LIN2+ 1 28 LIN1+
LIN2- 2 27 LIN1-
RIN2+ 3 26 RIN1+
RIN2- 4 25 RIN1-
TEST 5 24 M/S
VCOM 6 23 CKS
AVSS 7 Top View 22 PDN
AVDD 8 21 DVSS
DIF 9 20 DVDD
TDM1 10 19 TVDD
TDM0 11 18 SDTO1
TDMIN 12 17 SDTO2
MCLK 13 16 BICK
OVF 14 15 LRCK
MS0225-E-00 2003/05
-2-
57
MS-A5001
ASAHI KASEI [AK5384]
PIN/FUNCTION
MS0225-E-00 2003/05
-3-
58
MS-A5001
ASAHI KASEI [AK4382A]
AK4382A
112dB 192kHz 24-Bit 2ch ∆Σ DAC
GENERAL DESCRIPTION
The AK4382A offers the perfect mix for cost and performance based audio systems. Using AKM's multi
bit architecture for its modulator the AK4382A delivers a wide dynamic range while preserving linearity
for improved THD+N performance. The AK4382A has full differential SCF outputs, removing the need
for AC coupling capacitors and increasing performance for systems with excessive clock jitter. The 24 Bit
word length and 192kHz sampling rate make this part ideal for a wide range of applications including
DVD-Audio. The AK4382A is offered in a space saving 16pin TSSOP package.
FEATURES
ο Sampling Rate Ranging from 8kHz to 192kHz
ο 128 times Oversampling (Normal Speed Mode)
ο 64 times Oversampling (Double Speed Mode)
ο 32 times Oversampling (Quad Speed Mode)
ο 24-Bit 8 times FIR Digital Filter
ο On chip SCF
ο Digital de-emphasis for 32k, 44.1k and 48kHz sampling
ο Soft mute
ο Digital Attenuator (256 steps)
ο I/F format: 24-Bit MSB justified, 24/20/16-Bit LSB justified or I2S
ο Master clock: 256fs, 384fs, 512fs or 768fs (Normal Speed Mode)
128fs, 192fs, 256fs or 384fs (Double Speed Mode)
128fs, 192fs (Quad Speed Mode)
ο THD+N: -94dB
ο Dynamic Range: 112dB
ο High Tolerance to Clock Jitter
ο Power supply: 4.75 to 5.25V
ο Very Small Package: 16pin TSSOP (6.4mm x 5.0mm)
MCLK
VDD
Clock VSS
CSN De-emphasis
µP Control Divider
CCLK Interface DZFL
CDTI
DZFR
8X ∆Σ AOUTL+
LRCK Audio Interpolator Modulator SCF
AOUTL-
BICK
Data
Interface
SDTI 8X ∆Σ AOUTR+
Interpolator Modulator SCF
AOUTR-
PDN
MS0071-E-01 2002/2
-1-
59
MS-A5001
ASAHI KASEI [AK4382A]
ν Ordering Guide
ν Pin Layout
MCLK 1 16 DZFL
BICK 2 15 DZFR
SDTI 3 14 VDD
CSN 6 11 AOUTL-
CCLK 7 10 AOUTR+
CDTI 8 9 AOUTR-
PIN/FUNCTION
MS0071-E-01 2002/2
-2-
60
MS-A5001
March 5, 2009
Datasheet No – PD97381
IRS20957S
Protected Digital Audio Driver
Note: Please refer to Lead Assignments for correct pin configuration. This diagram shows
electrical connections only.
61
MS-A5001
IRS20957S
UV
HIGH
Q
SIDE
INPUT CS
LOGIC HO
IN
15.3V
10.2V
HV
LEVEL VS
SHIFT HV HV
FLOATING HIGH SIDE
LEVEL LEVEL
VSS SHIFT SHIFT
5V REG VCC
UV
CHARGE/ DETECT
DISCHARGE
CSD
DEAD-TIME
LO
20.4V
SD DT
HV
LEVEL
COM
SHIFT
PROTECTION
CONTROL HV
LEVEL LOW SIDE CS OCSET
SHIFT
DT
62
MS-A5001
IRS20957S
VB
ESD
Diode
15 V HO
Clamp
ESD
Diode
VS
200 V V CC
VCC
ESD
Diode
20 V
Clamp LO
ESD
Diode
COM
63
MS-A5001
IRS20957S
Lead Definitions
Lead Assignments
VDD 1 16 CSH
CSD 2 15 VB
3 14 HO
IRS20957
IN
VSS 4 13 VS
NC 5 12 NC
VREF 6 11 VCC
OCSET 7 10 LO
DT 8 9 COM
64
MS-A5001
June 2009
FDV301N
Digital FET , N-Channel
General Description Features
This N-Channel logic level enhancement mode field effect 25 V, 0.22 A continuous, 0.5 A Peak.
transistor is produced using Fairchild's proprietary, high cell RDS(ON) = 5 Ω @ VGS= 2.7 V
density, DMOS technology. This very high density process is RDS(ON) = 4 Ω @ VGS= 4.5 V.
especially tailored to minimize on-state resistance. This
device has been designed especially for low voltage Very low level gate drive requirements allowing direct
applications as a replacement for digital transistors. Since operation in 3V circuits. VGS(th) < 1.06V.
bias resistors are not required, this one N-channel FET can
Gate-Source Zener for ESD ruggedness.
replace several different digital transistors, with different bias
>6kV Human Body Model
resistor values.
Replace multiple NPN digital transistors with one DMOS
FET.
Mark:301
OUT
IN G S
G S GND
65
MS-A5001
TL494
PULSE-WIDTH-MODULATION CONTROL CIRCUITS
www.ti.com SLVS074E – JANUARY 1983 – REVISED FEBRUARY 2005
DESCRIPTION
The TL494 incorporates all the functions required in the construction of a pulse-width-modulation (PWM) control
circuit on a single chip. Designed primarily for power-supply control, this device offers the flexibility to tailor the
power-supply control circuitry to a specific application.
The TL494 contains two error amplifiers, an on-chip adjustable oscillator, a dead-time control (DTC) comparator,
a pulse-steering control flip-flop, a 5-V, 5%-precision regulator, and output-control circuits.
The error amplifiers exhibit a common-mode voltage range from –0.3 V to VCC – 2 V. The dead-time control
comparator has a fixed offset that provides approximately 5% dead time. The on-chip oscillator can be bypassed
by terminating RT to the reference output and providing a sawtooth input to CT, or it can drive the common
circuits in synchronous multiple-rail power supplies.
The uncommitted output transistors provide either common-emitter or emitter-follower output capability. The
TL494 provides for push-pull or single-ended output operation, which can be selected through the output-control
function. The architecture of this device prohibits the possibility of either output being pulsed twice during
push-pull operation.
The TL494C is characterized for operation from 0°C to 70°C. The TL494I is characterized for operation from
–40°C to 85°C.
AVAILABLE OPTIONS
PACKAGED DEVICES (1)
TA SHRINK SMALL THIN SHRINK
SMALL OUTLINE PLASTIC DIP SMALL OUTLINE
OUTLINE SMALL OUTLINE
(D) (N) (NS)
(DB) (PW)
0°C to 70°C TL494CD TL494CN TL494CNS TL494CDB TL494CPW
–40°C to 85°C TL494ID TL494IN — — —
(1) The D, DB, NS, and PW packages are available taped and reeled. Add the suffix R to device type (e.g., TL494CDR).
66
MS-A5001
TL494
PULSE-WIDTH-MODULATION CONTROL CIRCUITS www.ti.com
SLVS074E – JANUARY 1983 – REVISED FEBRUARY 2005
FUNCTION TABLE
INPUT TO
OUTPUT FUNCTION
OUTPUT CTRL
VI = GND Single-ended or parallel output
VI = Vref Normal push-pull operation
≈ 0.7 V Q2 11
PWM
Error Amplifier 1 C2
Comparator
1 10
1IN+ + E2
2 Pulse-Steering
1IN− −
Flip-Flop
Error Amplifier 2 12
16 VCC
2IN+ +
2IN− 15 − Reference 14
REF
Regulator
7
GND
3 0.7 mA
FEEDBACK
67
MS-A5001
MS-SERIES
MC9S08QG8
MC9S08GT16A
nRF2401+
68
MS-A5001
IRS20957
ADTL082 TPS78833
FEP16DTD
IRF3205
TDA3681TH
69
MS-A5001
MIC2982
BA50DD0WHFP LM2931
70
MS-A5001
71
MS-A5001
72
MS-A5001
73
MS-A5001
74
MS-A5001
75
MS-A5001
76
MS-A5001
77
MS-A5001
78
MS-A5001
79
MS-A5001
80
MS-A5001
81
MS-A5001
82
MS-A5001
83
MS-A5001_Power supply_Rev.C_Mar.29.sch-1 - Fri May 13 10:14:05 2011
MS-A5001
84