GOVERNMENTPOLYTECHNICCOLLEGE

MATTANNUR-670702

(Department of Technical Education,

Kerala)

SEMINAR REPOPORT ON

RESISTIVE RAM
SUBMITTED BY

DHEERAJ SATHEESH
REG NO : 2201041485

DEPARTMENT OF ELECTRONICS ENGINEERING 2024-25

GOVERNMENTPOLYTECHNICCOLLEGE MATTANNUR-670702

(Department of Technical Education, Kerala)

 CERTIFICATE
Certified that seminar work entitled “ RESISTIVE RAM ”is a bonafide work
carried out by “DHEERAJ SATHEESH ” in partial fulfilment for the award of Diploma
in Electronics Engineering from Government Polytechnic College Mattannur
during the academic year 2024-2025.
Seminar Head of
Coordinator Section
External
Internal Examiner Examiner
ACKNOWLEDGMENT

I would like to take this opportunity to extend my sincere thanks to people who helped me to
make this seminar possible. This seminar will be incomplete without mentioning all the people
who helped me to make it real.
Firstly, I would like to thank GOD, almighty, our supreme guide, for bestowing his
blessings upon me in my entire endeavor.
I would like to express my deepest gratitude Mrs. SHAMILA K (Principal GPTC,
Mattannur), Mr. GEORGEKUTTY P P (Head of Department of Electronics Engineering.), for the
help rendered by him to prepare and present this Seminar in proper way. Moreover I am very
much indebted to Mr. SREEJITH A (Lecturer, Electronics Engineering, seminar coordinator), for
their advice.
I am also indebted to all my friends and classmates who have given valuable suggestion
and encouragement.

DHEERAJ SATHEESH
 DECLARATION

I hereby declare that the report of the RESISTIVE RAM work entitled which is being
submitted to the Govt. Polytechnic College Mattannur, in partial fulfillment of the
requirement for the award of Diploma in ELECTRONICS ENGINEERING is a confide report of the
work carried out by me. The material in this report has not been submitted to any institute
for the award of any degree.

Place: DHEERAJ SATHEESH

Mattannur Date:
Contents
1
Introduction.............................................................................................................................1
1.1 Historical Background .............................................................1 1.2 Current Memory
Technology.................................................................................................................2 1.2.1 Volatile
Memory.......................................................................................................................2 1.2.2 Non-
Volatile Memory ...............................................................................................................2 1.3
Benefits and Types of RRAM .........................................................................................2 1.3.1
Neuromorphic
Computing .........................................................................................................2 1.3.2
Hyper-Dimensional Computing
..................................................................................................3 1.3.3 Classification
............................................................................................................................3 2 Theory
........................................................................................... .
.4
2.1 The RRAM Cell ..................................................................................................4 2.1.1
Switching Mechanism and Operation Modes ............................................................................4 2.2
The Crossbar
Array................................................................................................................................6 3
Method...........................................................................................................................................
.8
3.1 Experimental Part
.................................................................................................................................8 3.1.1
Experimental Setup and Data Acquisition .................................................................................8 3.1.2
Data Handling ........................................................................................................................10 3.2
Simulation Part ........................................................................................... 11 3.2.1 Passive Array
........................................................................................................................... 11 3.2.2 1T1R Array
..............................................................................................................................13 3.2.3 Small Signal
Modelling of NW 1T1R cell ...................................................................................14 3.2.4
Capacitances ..........................................................................................................................15 3.2.5
Integration of 1T1R Cell to the Array Model ............................................................................16
3.2.6 Array Performance and Figures of Merit
..........................................................................16 4 Results ....................................17
4.1 Experimental Part .......................................................................................................17
4.2
Simulations.........................................................................................................................................2
0 5
Discussion.................................................................................................................................
.25
5.1 Experimental Part
...............................................................................................................................25 5.2
 Abstract
As modern electronics have started to reach its physical scaling limits, novel architectures and
physics is needed
to meet future demands. Oxide-based Resistive Random Access Memory (RRAM) is a new emerging
technology that uses filament formation and rupture in thin oxides to generate resistive switching.
Structure of RRAM devices often use transistors as selector devices. In this work a one-transistor-
oneRRAM (1T1R) device is characterised using pulsed measurements. The endurance of the device is
extracted as well as the switching probability. Moreover, the data acquired from the device is used to
simulate 1T1R nano-wire (NW) arrays by integrating a cell level small signalmodel with an array-level
model. Analytical expressions are used to calculate parasitic capacitances. Worst-case cell analyses of
the access voltage and read margin are performed for different pulse widths, resistivities and
technology nodes. The average switching probabilities for a given array size are also calculated using
experimental data. It turns out that the examined device showed excellent endurance, exceeding 2
million cycles. Moreover, it also showed excellent switching characteristics and resistance window.
Simulations showed that high probability of switching could be achieved even for array sizes > 1000
bits. These results show that it is possible to integrate > Mbit sub-arrays with low-voltage 10 ns pulses,
providing a foundation for larger Gbit memory sizes, which are comparable with current DRAM and
NAND technology.
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CHAPTER 1
1 Introduction
this can be attributed to the successful scaling and integration of silicon (Si)
complementary metal oxide semiconductor (CMOS) transistors, which has constituted a
major part of the past 50 years of semiconductor research.
Today, on the other hand, the future of memory technology suffers from two main
bottlenecks. One has to do with the scale of nanoscale devices. The size of transistor
technology is approaching its physical limits. This means that the small size of a transistor
leads to leakage currents or a decrease in performance from parasitic elements. The
parasitic elements become significant for devices and interconnects in close proximity
[1]. Another main obstacle concerns the von Neumann architecture of conventional
computers. The data processing of the central processing unit and the random access
memory unit are separated, giving an Throughout history, humanity has used external
resources to record information in order to pass on knowledge. The external bearers of
information have evolved, ranging from sequences of stone formations to ink on paper
or magnetic tapes. While the technology responsible for the bearing of information has
changed, the mechanism responsible for the retention of information is often referred
to as memory. Modern memory technology has evolved both in terms of speed and size.
The invention of digital memory has led to smaller andintfearsprteertivteecihnoln ogies,
such as tapes, hard disk drives and the more recent solid state flash memory. As memory
technology has improved, so has also the computing capability of computers. One major
reason for
1. Historical Background
In his famous paper from 1971, Leon Chua laid down the theory for a fourth fundamental
circuit element with the possible property of carrying memory. He held the resistor,
capacitor and inductor as the other three fundamental circuit elements. In his text, Chua
argued that the properties of these elements are governed by differential equations
between four main quantities: voltage v, current i, charge q and flux linkage φ. Since
there are four quantities linking three components, Chua postulated that, by symmetry,
a fourth fundamental component could exist. The differential equations that link these
components are listed in table 1.
Table 1: The four fundamental circuit devices are related by differential equations
between voltage v, current i, magnetic flux linkage φ and charge q.

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Property R =
(unit) dvdi
itance C =
(farad) dqdv
Resistor Device
Capacitor Capac

Inductor Inductance (henry)

= dφ di
Memristor Memristance (ohm)
= dφdq
Among these relationships, the resistor, capacitor and inductor were well known. Only
the last element, the memristor, was at the time Chua’s paper was written not
discovered. He also showed that solving the above equation for voltage as a function of
time gave the relationship v(t) = M (q(t))i(t), (1)
which showed that the memristor has a charge-dependent resistance [4]. It presented a
possibility for a circuit component whose resistance is dependent on the history of past
voltages and currents.
While the theoretical and practical implication of Chua’s paper has been up for
considerable debate, his idea sparked an interest in the discovery of devices whose
resistance depends on past voltages. The research into memristors has led to a variety
of possible candidates. These include (among others) ferro- electric memories, phase
change memories and resistive memories [1]. While there is much to be said of each
technology, it is outside the scope of this work, and the rest of the text will therefore be
concerned with resistive memory technology.
2. Current Memory Technology
Modern digital memory technology is diverse and the physical mechanisms depend on
the application. Information is measured in bits and one bit of information has a binary
value of a 0 or a 1. For a memory cell to store information it thus needs to be able to
switch between two well defined states, as well as being read without disrupting its
value. What determines how fast and how efficiently a memory cell can be switched or
read depends on the cell size, materials as well as its complexity.
1. Volatile Memory
Digital memory technology can be classified into volatile and non-volatile memory (VM
and NVM re- spectively). Volatile memory needs constant power consumption to retain
its data. The two dominant VM technologies that dominate the market today is
considered to be dynamic and static random ac- cess memory (DRAM and SRAM,
respectively). These have different cell architectures, strengths and weaknesses. SRAM

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technology is a fast memory technology used often as temporary storage for central
processing units (CPUs). The memory cell is in its most generic form consisted of six
transistors, forming two inverters, which makes the SRAM cell capable of writing and
retaining the data without refreshment, although at the cost of a large feature size due
to the number of components needed. A DRAM cell, on the other hand, is built up of one
transistor and one capacitor. Its small feature size makes DRAM capable of storing large
amounts of data at high speed. The major drawback of this technology is its high power
consumption. Due to current leakage the charge of the capacitor needs to be refreshed
regularly to retain its memory [5].
2. Non-Volatile Memory
Non-volatile memory, as opposed to volatile memory, is characterised by its ability to
retain data even without power consumption. Modern USB memories and solid state
drives (SSD) are composed of flash memory cells, which include technology based on the
NAND or NOR logic gate architectures. A flash memory cell is consisted of a single
floating-gate MOSFET, which makes it possible to significantly reduce its size. It has a very
fast read speed, though it suffers from a much lower write speed. Furthermore, its
endurance (number of read/write cycles before failure) is much lower than for static and
dynamic RAM, which hinders it from applications where many read and write operations
are needed [5].
3. Benefits and Types of RRAM
The current digital memory landscape thus brings fast volatile memory on one hand, and
energy-efficient / small non-volatile memory on the other hand. Though all of these
technologies have excellent performance in terms of random access and reliability, they
suffer from high power consumption and low write speed. To tackle these problems new
architectures, engineering and physics are needed.
Resistive random access memory holds promise for tackling all of these drawbacks. Its
simple structure makes it both fast and highly scalable, while also operating at high
speed and low power. Moreover RRAM is non-volatile as well. While the details of the
mechanism and architectures of RRAM will be laid out below, there are additional
computational advances that can be realised and improved by RRAM.
1. Neuromorphic Computing
Neuromorphic computing (NC) draws inspiration from the brain and aims to resolve the
von-Neumann limitations of sequential computing. The von-Neumann architecture is
assembled to produce computa- tions in series. The reason
for this is because of the separation of the processing unit and the memory.
Neuromorphic computing architecture, on the other hand, compute in-memory,
meaning that signals travel to different nodes, as opposed to sequential inputs and
outputs. This distributed way of signal processing makes it possible for NC to solve
problems much faster than conventional computers. In particular, problems related to
artificial neural networks, which also have nodal signal pathways, will become faster.

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There are neuromorphic architectures today based on current transistor technology. As

such, power consumption is still a problem even though the problem-solving capacity is
improved [6].
2. Hyper-Dimensional Computing
Hyper-dimensional computing is a newer development of brain-inspired computing. The
central objective is to build a computational model that incorporates the size and error
immunity of the brain. Data is represented as random vectors with a very high
dimensionality ( 10000 bits). Any new random vector will, on average, differ in 50 % of
the bits. As a result, data with high uncertainty (10-20 % error rate) can still be classified.
This, in turn, means that HD computing is capable of one-shot learning, meaning it can
classify data with few examples, as opposed to neural networks that require huge
amounts of data. RRAM based hyper-dimensional computing on 3D arrays have been
demonstrated, capable of recognising 21 languages with 90 % and 98 % accuracy [7, 8].
3. Classification
RRAM can be classified into two types with respect to material selection. Anion-based
RRAM is the type that is used in this thesis, where oxygen ion migration and
redoxreaction is the main mechanism to form conductive filaments of oxygen vacancies.
This type of RRAM has been extensively researched [1, 3, 9] and is also in most cases
classified as bipolar due to the fact that a reverse voltage is needed to rupture the
conductive filament.
Cation-based (CB) RRAM, on theother hand, is dominated by electro-chemical reactions
and diffu- sion of Ag or Cu to form a conductive bridge. This type of RRAM is normally
operated with voltage pulses of the same polarity, where the main mechanism for the
rupture the conductive filament is Joule heating [10].
Anion and cation based RRAM have shown strengths and weaknesses of different kinds.
Anion type RRAM are the most researched and have exhibited the best performance with
regards to endurance and compatibility with industry CMOS technology as a high-k
technology node. On the other hand, one main obstacle is the need for a forming
operation (explained in section 2.1.1). This lies in contrast to CBRAM which does not need
a forming operation. CBRAM also has a high resistance window between its two states,
making it a viable option for multi-bit storage cells [10]. Therein lies a challenge as well,
as the diffusion of Ag and Cu atoms in CBRAM makes the conductive bridge hard to
control consistently. This in turn is often considered as a main contributor to the low
endurance of CBRAM [1].
There is much more to be said of both these categories of RRAM and while this
classification holds in general, there are cases where it is problematic. There are indeed
cases where oxide-based RRAM has displayed Joule heating filament rupture [11].
Furthermore, ITO based RRAM has shown conductive bridge formation due to indium
diffusion [12]. Even so, this categorisation of RRAM is still used and provides a general
landscape of the technology.

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CHAPTER 2
2 Theory
The theory of RRAM technology is still ongoing, and much is yet to be discovered. In
particular, the details regarding the switching mechanics of RRAM remain to be unfolded.
The following section thus aims to provide the frameworks of the general consensus
regarding anion-type oxide RRAM, which is the technology of interest in this work and
has been extensively researched in Lund University. In particular the specific mechanisms
at play for ITO-HfO2-TiN RRAM will be considered. A large part of this work also
investigates the system-level behaviour of RRAM. For this case the terms ”RRAM device”
and ”RRAM cell” will at times be used interchangeably, as opposed to ”RRAM array”,
which will denote the system composed of RRAM cells. The author apologises for any
unintentional ambiguities that may arise due to this terminology.

Figure 1: Schematic of a MIM RRAM cell. The dielectric HfO is sandwiched between the
top electrode ITO and bottom 2 electrode TiN.
1. The RRAM Cell
The structure of an oxide-based cell is, at its core, identical to a capacitor. For an
oxidebased RRAM a thin insulating high-k dielectric (in this work: hafnium dioxide, or
HfO2) is sandwiched between two metal electrodes (a metal-oxide-metal (MIM)
structure) which is illustrated in figure 1. The top electrode (TE) signifies the input, while
the output is represented by the bottom electrode (BE), which may be composed of

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different metals or alloys. In this work the TE is made of indium-tin-oxide (ITO) and the
bottom electrode of titanium nitride (TiN).
1. Switching Mechanism and Operation Modes
The main mechanism for switching of oxide based RRAM is the formation and rupture of
a conductive filament. These are formed by applying a soft breakdown voltage over the
device. Initially the RRAM is at a high resistance state (HRS). To get a working RRAM cell,
a filament is constructed by a forming voltage. The electric field displaces oxygen ions,
which reside in the dielectric, towards the oxygen rich ITO, leaving a conductive oxygen
vacancy filament. In this mode the RRAM is said to be in a low resistance state (LRS). To
reset the RRAM into a HRS a reverse bias is applied which lets the oxygen in the ITO
remigrate into the filament, resulting in a rupture. A set operation can be programmed
by again applying a positive voltage. This process is illustrated in figure 2a- d.

Figure 2: Schematic of the different operations ofan RRAM cell. a) The RRAM is in its
initial high resistance state. b) A soft breakdown forming voltage is applied which results
in a conductive filament of oxygen vacancies (dashedlines). The RRAM is now in a low
resistance state. c) A reverse voltage pulse ruptures the filament by ion-vacancy
recombination which rests the cell into a high resistance state. d) the RRAM is now
functioning and can be set to a low resistance state.
These modes can be observed by measuring the direct current (DC) versus voltage curve
of the RRAM, which is illustrated in figure 3. A positive voltage is applied and the RRAM
behaves as a resistor, until a critical voltage is achieved (the SET voltage Vset). The
filament is formed and the lowered resistance allows for a greater current flow. The
resetting is achieved by a negative bias where, just as for the SET operation, a critical
voltage Vreset ruptures the filament and resets the cell into HRS. Although the curve might

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look different depending on the structure and material of the RRAM, this generic curve
illustrates a generic RRAM switching behaviour.

Figure 3: Generic IV characteristics of a RRAM cell. The operations involve the set which
sets the RRAM from a high resistances stateto a low resistance state.The reset operation
resets the device. The path of the voltage sweep is given by the arrows. RW denotes the
resistance window. The figure is reprinted with permission from [13]
There are a number of different quantities and properties of the RRAM that determine
the SET and RESET voltage. The materials of all three components; TE, BE and dielectric,
significantly alter the behaviour of the
RRAM. The oxide thickness is also an important parameter that determines how the
filament is formed. The RRAM material stack chosen for this work is described in section
3.1.1.
2.2 The Crossbar Array
As mentioned above, RRAM stands as a promising candidate for novel computing
architectures. In order to use RRAM in applications, arrays of devices will be used. Below
follows the background regarding one of the most investigated structures for the
realisation of new computation architectures, the crossbar array (CBA)[14, 7, 8, 15, 16].
The CBA is a square array with the rows and columns separated by RRAM cells, situated
on each node. This structure is attractive because of its simplicity and similarity with
current DRAM arrays [8, 5]. The architecture allows for random access of each device,
meaning the time it takes to write and read information from each node is in the same
time scale. Furthermore, the cells may be composed of various memory technology as
well as compositions of devices, which are used to build artificial neurons [6]. Thus, an
investigation of the CBA is not only important for oxide based RRAM, but for all resistive
non-volatile memory technology. Nonetheless, this work will focus on CBA performance
in relation to RRAM.
The CBA has different appearances and architectures. The cells may be made of a single
RRAM cell as depicted in figure 1. This will be referred to as a passive CBA and is, in terms
of engineering, an uncomplicated structure. A passive crossbar array is illustrated in
figure 4. Ideally, passive CBAs would stand as an excellent structure, though the
operations that are used to write and read memory bring difficulties related to leakage
currents.

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Active CBAs have been shown to suppress leakage currents by introducing selector
devices in the cell. The selectors are coupled in series with the RRAM. Different selectors
have been investigated both experimentally and by simulation, ranging from diodes to
transistors [17, 18, 19, 20]. For this work, the simulation will incorporate nanowire
transistors as the selector device. In particular the one-transistor- one-RRAM (1T1R)
structure will be investigated. A generic array structure for a 1T1R NWRRAM array can
be seen in figure 5. The circuit representations for both 1T1R and one-RRAM (1R) cells
can be viewed in figure 6.

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Figure 4: An illustration of a array. The NWs are attached to

passive cross- bar array. At each the substrate.
intersection a RRAM cell is The word-line is
situated. By applying a potential connected to
difference between the bottom the transistor
level (word line) and the top level gate (lower
(bit line) the RRAM can be level) and the
switched on Figure 5: An bit-line to the
illustration of an active 1T1R NW RRAM device
(top level).

and off.
Figure 6: Circuit representation of a 1T1R and 1R cell structure. (a) A 1T1R structure.
The WL isconnected to the gate of the MOSFET and the BL to the source. The RRAM
is connected in series with the drain of the transistor with the BE grounded.
(b) A single passive 1R cell. The WL is connected to the TE and the BL to the BE A
cell is programmed by applying voltages to the word-line (WL) and bit-line (BL) of
the CBA. The WL connects to a row of cells. The operation is trivial for passive CBAs
but for 1T1R CBAs the WL accesses the transistor and allows for a current to flow
between the source and the drain. The specific way the WL and BL are biased
depends on the type of CBA, and will be explained in detail below.

CHAPTER 3

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3 Method
As mentioned above, this work consists of both an experimental and a simulations
part. A one-transistor- oneRRAM (1T1R) structure was examined and the data was
used to investigate the RRAM’s perfor- mance in a simulated array environment.
The methods for both parts are explained below. It should be noted that several
RRAM devices and structures were investigated, with different equipment, before
it was decided on which experiment to include in the work. This work accounts for
one of these ex- periments, where pulsed voltages were applied on a 1T1R
structure, which gave presentable and clear results, as well as good statistical
performance. Lastly, the RRAM device in the experimental part and the simulated

NW RRAM devices have different structures. Ideally the measured device should
have close resemblance to the simulated one, but at the current time no such
devices had been successfully processed.
1. Experimental Part
1. Experimental Setup and Data Acquisition
Several different RRAM stacks had been previously fabricated at Lund NanoLab. The
RRAM device that is presented in this work was grown in a via opening on a Silicon
on oxide-substrate with a 200 nm oxide layer. It has a TiN top electrode deposited
by 200 ◦C atomic layer deposition (ALD), a 3 nm thick HfO2 film also deposited by
200 ◦C ALD. The 20 nm thick ITO bottom electrode was deposited with sputtering
with Au cover. Further details concerning the fabrication of the stack can be found
in [21].
The RRAM device is connected to a FET with a coaxial wire. The FET used for this
work had been previously fabricated for low-power RF-applications and consisted
of a single NW [22]. For this experiment it acted as a selector, with the role of
reducing current overshoot and forces the current to compliance. The circuit
representation of this setup is given in figure 6a above.
The devices were situated on a probe station. The RRAM BE and the gate of the
transistor were connected by probes to a B1500A Device Parameter Analyser by
Keysight Technologies, which was used to apply signals and measure the current.
Before probing the device, the probes were assured to be working by measuring
signals to the gold cover of the RRAM sample. Care was taken to not break the
probes.
Following this, a functional FET was chosen. The transfer and output characteristics
of the FET can be viewed in figures 7 and 8 respectively. From figure 7 one can see
the drain current as dependent on gate voltage for VSD
= 0.5 V (lower line) and 1 V (upper line). This shows a well functioning gate
modulation of the current. Figure 8 shows the drain current as dependent on the
source/drain voltage, with the gate voltage swept between -0.8 V to 0.8 V in steps
of 0.4 V.

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Figure 7: The transfer characteristics of a FET device used in the experiment for VSD
= 0.5 V (lower line) and 1 V (upper line)

Figure 8: The output characteristics of a FET device used in the experiment. The
output was measured by sweeping the gate voltage from -0.8 V (lowest line) to 0.8
V (upmost line) in steps of 0.4 V
Well defined biasing schemes are needed to operate the 1T1R device. The three
different modes of operation for the setup are the set, reset and read operations.
Motivated by the FET figures 7 and 8, the set operation was defined at zero gate
bias to counteract current overshoot. For the read operation the gate bias was set
to 0.4 V. This level of gate bias gave a larger source/drain current. For the reset
operation a large gate bias was applied so as to allow for a high compliance current.
For each gate pulse, the structure was biased from RRAM to the drain of the FET
with different amplitudes. The set operation had positive voltages, while the reset
had negative. The experiment was implemented for amplitudes 1.5 V and 1 V. The
reading voltage was set to 50 mV. A summary of the bias scheme can be viewed in
table 2.
Table 2: The bias scheme for the 1T1R experimental setup
Gate Source Operation
Voltage -
Drain

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Voltages

0.0 V 1.5/1 V Set

0.4 V 50 mV Read
0.8 V -1.5/-1 V Reset

One sequence of measurements corresponded to the operations read-set-

readreset-read. The pulses on the gate were square, while the pulses between the
source and drain were triangular. The wire connecting the RRAM to the FET was
long enough to give rise to capacitive currents for small pulses. To alleviate this,
long pulses of 3 ms pulse width were applied. Figure 9 shows the current and gate
voltage of one measuring sequence with voltage amplitude being 1.5 V. The first
current spike shows a successful set event, with a sudden vertical elevation at
around 7 ms. The same is true for the reset operation at 17 ms, where the first
negative current spike marks the reset event.

Figure 9: One cycle of measurements shows the source/drain current (left axis) and
gate voltage (right axis) and their time evolution. The sequence of operations are
read-set-read-reset-read. The stop voltage for this measurement was 1.5 V
3.1.2 Data Handling
The pulsing sequence described above was implemented for the setup up to two
million times. Because of the high number of pulses, there was no way to measure
every cycle. Because of this checkpoints were placed in logarithmic intervals to
measure the status of the device. The data acquired was handled using the Python
programming language. Before analysis, background noise was subtracted from the
current. In order to extract the statistics of Vset and Vreset, the switching event had
to be clearly defined. The definition of the set voltage was done by looking at the
derivative of the current. The reason behind this being that the steepest change
should mark the middle of the switching event. While it proved successful most of
the times, it marked a number of false switching events. It was found that the

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current had neighbouring points that were noisy enough to give off spikes of false
switching events. In order to mitigate this, the data was first filtered through a
Gaussian filter to smooth out the curve. Figure 10 shows the process of extracting
one set event.

Figure 10: A set event marked by the gradient. The data is filtered and the middle

of the set event was found by the derivative and second derivative of the curve.

Figure 11: A reset event marked by the gradient. Two reset events are seen, yet
only one is successfully marked
The reset voltage statistics were extracted differently. This was mainly because of
the fact that one sweep sometimes included two reset events. One such sweep can
be seen in figure 11, where two points are marked. The leftmost (red) marks a false
event and the rightmost (green) marks a true second reset event. The actual reset
voltage was then defined as the average of the two. Because of the wide switching
window of the device, a false reset voltage was not seen as problematic, since it is
in general unclear how to define a switching voltage for a double reset event. For
the purpose of calculating the LRS and HRS resistances of the RRAM, the reading
current for each cycle was extracted. The structure was operated at Vr = 20 mV for
a reading operation. From figure 8 one can see that the onset of the curve gives the
on resistance of the device, Ron. Since the measured current applies to the whole
structure which is connected in series, we get the total resistance Rtot = RRRAM + Ron
= Vr/Ir, where Ir is the reading current through the structure. A simple
rearrangement gives an estimation of the resistance of the RRAM:
Vr
RRRAM = − R on . (2)
Ir
Once the relevant quantities had been clearly defined and extracted, the statistics
were calculated. The quantities that were calculated were the mean and standard
deviation of the set/reset voltage and the switching probability. The switching
probability was extracted by calculating the cumulative probability distribution of
the switching voltages.

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2. Simulation Part
The simulation of the CBA can be divided into two parts. One part deals with an
array without selectors. The model was incorporated from [15] with the reason of
visualising the DC access voltage without selectors. The second model is a
smallsignal model on cell level, and is based on the framework that was in
development in the Nano-electronics group in Lund University.
1. Passive Array
For the purpose of developing a simulation platform for a passive crossbar array,
the approach given in [15] was incorporated, which allows for versatile biasing
schemes. As such, details concerning derivation and mathematical rigour of the
resulting formulas are omitted in this work and the interested reader can be
referred to [15].
The CBA is represented by a matrix, which can be viewed in figure 12. The matrix is
rectangular with m rows
(word lines) and n columns (bit-lines), whereby the intersections containing RRAM
cells are represented as
matrix elements {i m, j n}. The array is operated at a supply voltage Vapp which
can be applied to the left and right of the WL plane (Vapp,W L1 and Vapp,W L2
respectively) or to the top and bottom of the BL plane (Vapp,BL1
and Vapp,BL2 respectively). The applied voltage has an access resistance, which in the
model is represented by the vectors RS,W L1, RS,W L2, RS,BL1 and RS,BL2. The nodes are
connected by wires with a specific line resistance Rl. Each node contains an RRAM
with a specific resistance. The RRAM resistance can be represented by a resistance
matrix with dimensions m × n.

Figure 12: A schematic of a 4x4 passive CBA with corresponding parameters. The
array can be biased on the
WL plane (Vapp,WL1 and Vapp,WL2) and the BL plane(Vapp,BL1 and Vapp,BL2). Ateach
intersection resides an RRAM cell with resistance Rij. The model also includes line
resistance Rl and access resistances Rs.
This model effectively represents a 4 port network, whereby the cells can be
classified into four groups. Selected devices are accessed by a selected WL and BL.
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The unselected devices have a common unselected WL and BL bias. Half selected
devices have either common WL or BL bias with the selected devices. At each node
Kirchhoff’s continuity equation is assumed to hold. For an array of size m × n this
means that there will be 2mn equations (one set for the WL plane and one set for
the BL plane). The current at site (i, j) is IW L(i, j) = I(i, j) + IW L(i, j + 1) (3) IBL(i, j) = I(i, j)
+ IBL(i − 1, j),
where I(i, j) is the current through the cell, IW L(i, j) the current in the WL plane going
into node (i, j) from (i, j − 1) and IBL(i, j) the current in the BL plane going out of the
node (i, j). The equations may also be written in voltage form. The resulting
unknown voltage delivered on the WL and BL planes can be obtained by solving the
2mn equations [15]. How this is done is given by the Python code in the appendix.
Figure 13 shows one simulation run for a 32x32 bit array, with a high line resistance,
for the purpose of illustration. The voltage loss is clearly demonstrated, with the
best cell residing in the top left corner, and the worst cell at the lower right corner.
Biasing schemes are integral to passive array operation to not switch unselected
devices. For this run the selected WL was biased at Vapp = 1 V while the unselected
WL and the BL were biased at Vapp/2. The WL was biased from the left and BL from
the top. The access voltage given in the figure is defined as the voltage difference
between the BL and WL planes.

Figure 13: Bit map of a 32x32 bit passive array. Each square pixel correponds to a
RRAM cell. The left y axis shows the insertion point of the BL voltage and the top x
axis the insertion point of the WL voltage. The applied voltage in this run was 1 V.
The map illustrates the behaviour of a passive array with effects of line resistance
and sneak path currents. For this simulation run the line resistance was raised
significantly for visualisation purposes.
The figure shows that the worst case bit (at the bottom rightmost corner) suffers
the worst access voltage, while the top leftmost corner yields the best access
voltage, as would be expected. With this model at hand, the 1T1R cells could be
incorporated.
3.2.2 1T1R Array

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For the purpose of investigating nanowire 1T1R arrays, an active 1T1R cell model
was constructed. The model takes into account the dimensions of the NW and
RRAM. The schematic of a cell and its corresponding dimensions can be viewed in
figures 14 and 15.
Figure 14 shows a top-down view of the 1T1R cell. The NW is situated in the middle
with a diameter dnw. The total NW diameter includes several development films
which are formed during the fabrication process. The interconnects have a width W
and are in this work half the size of the node U .

Figure 14: A top-down schematic of the NW cell, with its corresponding dimensions.
U signifies the unit length of the square cell, W the width of the interconnect and
dnw the diameter of the nanowire. The figure is illustrative and the relative
dimensions differ in the simulations.
Figure 15 shows a side-view of one NW 1T1R cell. The distances between
interconnects are marked as well as a circuit schematic.

Figure 15: A sideways schematic of the NW RRAM cell. The distances between the
WL, BL and source/sub- strate are SBL−WL,
SBL−S and SWL−S . The interconnects have thickness T
3.2.3 Small Signal Modelling of NW 1T1R cell
The 1T1R cell was modelled to incorporate signal loss, which arises due to parasitic
capacitances of the cell. These losses might not be apparent for small arrays, but
may give rise to large losses for larger arrays. Thus the
RRAM device can be viewed as being constituted by a resistor, RRRAM , and a
capacitor, CRRAM , connected in parallel. The resulting circuit representation can be
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viewed in figure 16. The parameters that were used in the simulations are shown in
table 3. While the NW material is generic in this work, some material parameters
were chosen in particular. The interconnects are made of copper, because of its
extensive use in the industry. For the same reason the interconnects and NW are
spaced by silicon dioxide.

Figure 16: Circuit representation of a 1T1R NW cell without fringe and neighbouring
capacitances. The RRAM is modelled as a resistor coupled in parallel with a
capacitor.
Table 3: Parameters for a 1T1R cell for different node sizes

3.2.4
Capacit The different geometries
included in a cell give rise to varying types of capacitances.
Firstly the
parasitic
capacitances of the NWFET were modelled as coaxial capacitances:
2πϵ0ϵox
t , (4)
C= ·

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dnw Nanowire 8/12/18 nm
coax ln ((rnw + diameter
tox)/rnw) l where W Interconnect 17.5/25/50 nm
ϵ0 is the electric width
permitivity of T Interconnect 35/50/100 nm
vacuum, ϵox the thickness
relative ρC Interconnect 5.8 ×10−8Ω m
permitivity of Resistivity
tox−RRAM 2.8 nm
the oxide, rnw RRAM oxide
Lnw 320/480/720
the radius of the thickness
SWL−S Lg nm
NW, tox the NW Length
ances 80/120/160 nm
oxide thickness WL- 30/40/50 nm
and tl the Substrate
thickness of the Distance FET
WL. The Gate
capacitance Length
between the
interconnects have a parallel component. For that the formula for parallel plate
capacitance was used:
ϵ0ϵoxA
Cpar = , (5)
d
where A is the area of the parallel plate and d the distance between the
corresponding parallel plates.
Besides these two types of capacitances, the close proximity of cells and
interconnects give rise to additional parasitic elements, which occur between
fringes of interconnects and neighbouring cells. While it is possible to compute the
fringe capacitances numerically using a wide array of software, some of them can
be extracted analytically and used without any significant computational cost. The
conceptual framework of how these are inferred can be found in [23]. In this work
the resulting analytical expressions are incorporated as they were presented in the
article.
In figure 17 the two fringe capacitances used in this work are demonstrated
between interconnects. The WL and BL have capacitive couplings with both the
substrate and each other. The capacitive coupling from the BL to the substrate goes
from the side of the BL electrode to the top of the substrate. The same type of
coupling is modelled between the side of the BL electrode and the top of the WL.
The electrodes also couple to adjacent electrodes in the same level, where the
coupling that is mainly between the top of each interconnect. The formulas for the
two fringe capacitances Cs−t and Ct−t are given in equations (10) and (11) in
appendix A.1. For each cell Ct−t was calculated between all interconnects in a
proximity of 2 microns. Cs−t was calculated both between interconnects and
interconnect to substrate.

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Figure 17: The fringe capacitances between interconnects. a shows the coupling
between the side of an interconnect to the top of another. b shows the fringe
capacitance between the top of two interconnects. In this work the couplings are
also modelled between interconnects and the substrate.
The cell also has capacitive couplings to neighbouring cells. These included
interconnect to interconnect couplings as well as nanowire-to-nanowire
capacitance. All these capacitances were calculated using equation (5). The total
capacitance from neighbouring and fringe couplings for the BL can then be
expressed as:

Σ
Cf,n = {2µm} Ct−t
(6) +Cbss− t + Cbw s−t +2CBL−BL + 4CNW−NW , where the sum is within a
neighbourhood of 2 µm, Cbs the fringe capacitance between the BL and the
s−t substrate, Cwb − t the fringe capacitance between BL and WL, C − the
capcitance between two BL interconnects
s BL BL and CNW −NW the capacitance between the neighbouring nanowires. With all
the capacitances defined, the impedance for each cell could be calculated as
follows:
1
ZC = , (7)
i2πf C
where f is the frequency of the voltage pulse, C the capacitance responsible for the
impedance and i the imaginary unit. The impedance from the WL and the BL are
different. The capacitances included in the calculation of the impedance for the BL
are (cf the circuit in figure 16): CBL−S, CBL−W L, CRRAM , Cgd och Cgs. The BL also has a
resistive part RRRAM . The total impedance experienced by a pulse sent to the BL is
(”//” denotes parallel coupling):
ZBL = ZCBL−S //ZCBL−W L //ZCf,n
(8) //((ZCRRAM //ZRRRAM ) + ZCgd + ZCgs ).
5. Integration of 1T1R Cell to the Array Model
The 1T1R cell has slightly different connections than the passive arrays. The cell is a
three-terminal device, while the passive array cell is a two-terminal device (cf.
figure
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6). In order to incorporate a three-terminal device into

a two-terminal structure, the WL and BL needed to be modified. Since the biasing
of the WL for the 1T1R model modulates the FET, its function is different than in
the passive array model. This meant that the programming of the 1T1R array would
have to be amended. To solve this discrepancy, each node resistance Rij was set to
Zmod,i,
where i denotes the BL row number of the array. The WL of the array then
effectively acts as the substrate level.
One last obstacle was the computational cost of large arrays. One run for 32x32
array took about one second, but for intermediate arrays (64x64) one simulation
ran for minutes, and for even larger arrays it would take hours and days. To be able
to simulate larger arrays, the resistances Rij and line resistances were first calculated
for smaller sub-arrays, and later inserted for a simulation of a 32x32 array as
effective resistances. This reduced
the run-time scale to seconds. The code is provided in the appendix.
6. Array Performance and Figures of Merit
The performance of the array can be characterised by a number of key figures of
merit.Because of the high number of cells included in an array, analysis of the worst
case cell is a natural way to go. The worst case cell suffers from the worst signal
losses (in this work the cell in the lower right corner). For both write and read
operations the voltage of the array needs to access all the cells. This will be referred
to as the access voltage.
Furthermore, the resistance of a cell needs to be observed reliably in a read
operation. The read margin is calculated by
RM = VLRS − VHRS, (9)
i.e. the measured voltage difference between the cell in low resistance state and
high resistance state.
Another interesting part is to relate the observed data in relation to array
simulations. In particular the probability of switching a cell is of interest for
application purposes, specifically in HD computing where stochastic distributions of
resistances is a sought after property of the array [8]. To this end, the access voltage
of the array can be mapped to the switching probability. In particular, the average
switching probability over a given array size was calculated.

CHAPTER 4
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4 Results
1. Experimental Part
The pulses used on the 1T1R device were long enough to be considered as DC
sweeps. For each set and reset pulse, the DC characteristics were extracted. The
device was first pulsed up to one million times with a pulse amplitude of 1.5 V, and
after that an additional million times with 1 V pulse amplitude. A total of 60 set and
reset measurements were extracted for 1 million cycles. Figures 18 and 19 show
the resulted IV plot for the device with a stop voltage of 1.5 V and 1 V respectively.
The thickness of the lines are growing along with successive sweeps. The forming is
not included in the figures, since the device was pulsed several times until a
functioning switching was achieved. The RRAM device showed clear switching
characteristics, although with a distinct spread to the switching voltages. There is
more information that can be gathered from these plots.
For both runs at a region at around -0.45 V a sudden downward spike of current can
be seen, which can be explained as a capacitive current due to the long wires used
in the experiment. A comparison of the IV curves reveals some differences and
similarities. One difference between the runs that is the apparent spread and
stability of the current. For 1.5 V stopping voltage, the switching voltages have a
larger spread than for 1 V stop voltage. For a measure of this difference, figures 20
and 21 provide the histogram of both runs. The mean (notated as µ) and standard
deviation (σ) were calculated and are also included in the plot.
This difference can be attributed to two main reasons, both of which include the
filament. One explanation has to do with the order of the measurements. As
mentioned in the theory section, the filament of an ITObased RRAM is consisted of
oxygen vacancies, that are assumed to migrate due to an electric field. Because of
this, the filament formation might need many pulses before a stable switching
behaviour is achieved. Another possible explanation has to do with the stopping
voltage. The smaller stopping voltage gives a lower interaction with the filament.
This means that the rupture and resetting of the filament could be under less stress,
and thus giving less spread and lower switching voltages.
Another feature that sticks out for this particular RRAM is the occurrence of two
set/reset events. This quality is most visible in figure 19 but can also be noticed in
figure 18. Figure 21 also strengthens this bu having a bi- modal distribution for the
set voltage. While the mechanism regarding the formation and evolution of the
filament lies outside the scope of this work, it can be mentioned that for this device
may consist of two filaments or a filament with two main paths.
The switching probability of both runs can be viewed in figures 22 and 23, for 1.5 V
and 1 V respectively. Both reset and set voltages are positive for easier comparison.
For both set and reset probabilities the highest measured switching voltage is
marked with vertical dashed lines. The top set voltage for 1.5 V lies at around 0.95
V, while the top reset voltage lies at around 0.87 V. For the 1 V run the top set

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voltage lies at 0.87 V while the top reset voltage is at 0.54 V. For both runs one
observation that stands out is the clear asymmetry between the set and reset
voltages. This asymmetry is larger for 1 V stop voltage than for 1.5 V. Furthermore,
the cumulative probability for 1 V has a steeper form. indicating a more defined
switching voltage with less spread, which is corroborated by the histograms and the
IV curves.
The endurance of this setup is seen in figures 24 and 25 for stop voltages 1.5 V
and 1 V respectively. From this data the mean high resistance and low resistance
states was calculated and presented in table 4.
Table 4: Table showing the mean and standard deviation of both low and high
resistance modes of for both 1.5 V and 1 V stop voltages
Voltag Stat Mea Std
e e n
1.5 LRS 58 kΩ 32 kΩ

1.5 HRS 46 43
MΩ M
Ω
1 LRS 89 kΩ 16 kΩ

1 HRS 107 16
MΩ 4
M
Ω
First and foremost the device showed remarkably good endurance, with the total
number of pulses exceeding 2 million cycles. Both figures and table 4 show that the
resistance window is large enough to
distinguish the states of the device, with a resistance ratio of RHRS/RLRS 103. The
spread of the device is significantly large, with standard deviations reaching the
same order of magnitude as the mean. For both runs the spread is smaller for the
LRS than for the HRS, while for 1 V stop voltage the LRS spread is smaller along with
a larger HRS spread.

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Figure 18: DC sweeps of the initial one mil- lion Figure 19: DC sweeps with stop
voltage 1 V. The cycles with stop voltage 1.5 V. The num- ber of number of cycles
between the sweeps range
cycles between the sweeps range from 100 to from 100 to 100 000. Thicker
lines in- dicate a
100 later stage in the cycling process.
000. Thicker lines indicate a later stage in the cycling process.

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Figure 20: Histogram of
the extracted set and
reset voltages of the Figure 21:
initial one million cycles Histogram of
for stop voltage 1.5 V. the extracted
The mean set voltage set and reset
was found to be µ = voltages for
0.568 V with standard stop voltage 1
deviation σ = 0.23 V. The V. The mean
mean reset voltage was set voltage was
found to be -0.403 V ± found to be µ =
0.191 V RESISTIVE RAM 0.579 V with

standard
deviation σ=
0.152 V. The
mean reset
voltage was
found to be
0.351 ± 0.097
V.

cycles with stop voltage

Figure 22: Cumulative 1.5 V.
switching probabil- ity of
the initial one million
Figure 24: Endurance measurements for the
initial one measurement with million cycles
with stop voltage 1.5 Figure 23:
Cumulative switching probabil- ity with stop
voltage 1 V.

Figure 25: Endurance stop voltage 1 V.

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V.
4.2 Simulations
All the parameters for the simulations are listed in table 3, unless indicated otherwise.
Worst case cell analyses for the access voltage and read margin can be seen in figures 26
- 31, with varying parameters. Figure 26 shows the access voltage versus array size for
technology node 35 nm. For high-speed applica- tions, the frequencies will reside in the
GHz regime, thus the pulse width is varied from 10 ns to 150 ns. The plot shows a distinct
decline in performance with a lower pulse width. This is expected, as a fast switching give
rise to higher losses due to parasitic elements. For larger array sizes (> 10000 bits) the
differences between the runs becomes smaller. Figure 27 shows the same type of analysis
with varying resistivity of the interconnects and with the pulse width fixed at 10 ns. The
resistivity is varied from the bulk resistivity of copper (16.8 Ω nm) to ten times the bulk
resistivity. The plot shows a large decline in performance with higher resistivity. The
difference between runs is not uniform, with the improvement being smaller for high
resistivities. For array sizes >
1000 bits the access voltage decreases exponentially. A similar analysis for the read
margin can be seen in figures 28 and 29 for 35 nm technology node. In order to choose a
reasonable reading voltage so as to not switch a cell unintentionally, figure 23 was
considered. From this the reading voltage was chosen to be around 150 mV with positive
polarization. The RM was calculated using equation (9). In figure 28 the sense resistance
is varied from 100 Ω to 100 kΩ. This shows the sense resistance dependence of the read
margin, and provides a sanity-check that the model works as expected. For 100 kΩ the
sense resistance is in the same order of magnitude as the LRS of the RRAM, and was thus
accepted as a reasonable value for the remaining simulations. Figure 28 shows the RM
with varying pulse widths. For small arrays (< 1000 bits) the RM declines slowly,
transitioning into an exponential decrease with array size. The RM is significantly
improved for larger pulse widths.
Figures 30 and 31 show access voltage and read margin analysis, respectively, for
different technology nodes. For these runs all the parameters are fixed as indicated in
table 3. The 100 nm technology node shows the best performance, while the 35
technology node shows the worst. This result is expected, as arrays with tighter devices
give rise to both higher resistivity of interconnects and larger parasitic elements. To get a
figure of how the signal losses are distributed between the different parasitic elements
the conductance
(inverse of resistance) was calculated for one cell. The results are presented in table
5 for each technology node. The parasitic elements that are included are BL-to-BL, BL-
toWL, BL-to- Substrate capacitances. Most of the leakage is due to BL-BL capacitances.
This leakage goes down if technology node is compared with 100 nm node. The next
largest contributors of losses are the parasitic elements of the NW. These losses increase
with technology node. This result is expected, as the BL-to-BL portion of the losses
decrease with node size. The BL-tosubstrate capacitances make up a small portion of the
total losses. The losses due between BL and WL take similarly only make up a marginal
portion of the total losses. This result shows that there are no significant losses due to
WL

parasitic elements, although it goes up for one order of magnitude from 35 nm to 100 nm
technology node. This increase is not something that has been looked into at this time. A
possible cause might be the relative sizes of the different parameters in use, which are
slightly different for the three node sizes investigated.
The veracity of the model could be further investigated by looking at how the leakage
distribution behaves with pulse width. Since the small signal model simulates signal
losses, the losses due to parasitic elements should become less significant as the pulse
width is increased. Figures 32 and 33 show the same parasitic elements with increasing
pulse width for technology node 35 nm. The simulations show that the BL-to-BL and NW
stand for the majority of the current leakage. For larger pulses the BL-to-BL parasitic
capacitances become less significant, while the NW leakage become more significant,
approaching 100 % for pulses > 1µs. Since the NW portion of the small signal model
includes less capacitive elements and more resistive elements, this behaviour is expected.
Moreover, the BL-WL and BL-S parasitic elements play a less important role even for 10
ns pulses, and decline rapidly with pulse width.
Figure 26: Write Access
voltage over the worst case cell vs

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 array size for different pulse
widths. The resistivity is fixed at
5.8×10−8 Ω m and the
technology node is 35 nm.

Figure 28: Read Margin analysis for the worst case cell, vs array size and for
different sense re- sistances. The pulse width is fixed at 10 ns and resistivity
5.8×10−8 Ω m. Technology node is 35 nm.

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Figure 27: Access Voltage over

the worst case cell vs array size
for different resistivities of the
interconnects. The pulse
width is fixed at 10 ns and the
technology node is 35 nm.
 Figure 30: Access voltage for the pulse widths. The resistivity is
worst case cell, vs array size and fixed at 5.8×10−8 Ω m.
fordifferent technology nodes. The Technology node is 35 nm.
pulse width is fixed at 10 ns and Figure 31: Read margin
resistivity 5.8×10−8 Ω m Figure 29: analysis for the worst case
Read Margin analysis for the worst cell, vs array size and for
case cell, vs array size and for different technology nodes.
different RESISTIVE RAM The pulse width is fixed at
10 ns and resis- tivity 5.8×10−8
Ω m
Table 5: Table showing the leakage percentage for each parasitic element of 1T1R cell. The pulse
width is set at 10 ns.
Parasitic 35 nm 50 nm 100 nm
Element Node Node Node
(%) (%) (%)

BL to 91.33 90.76 85.80

BL
NW 8.47 9.06 13.47
BL to 0.12 0.18 0.38
Substrate
BL to 0.08 0.01 0.35
WL

Figure 32: Leakage portion of the parasitic ele- ments Figure 33: Leakage portion of the
parasitic ele- ments due to BL-BLcouplings (top level) and NW leakage, as a due to BL-WL
and BL-Source couplings, as a function of function of pulse width for technology node 35 nm
pulse width for technology node 35 nm
The distribution of access voltage for array size 2048 bits is given in figure 34. For this size
the voltage loss was large enough to be visualised. The cells furthest to the right have the
largest loss of voltage, while the ones on the left have the highest. There are no significant
losses that arise due to the vertical position of a cell. The access voltage was mapped to
switching probabilities from the experimental part, and can be seen in figures 35-36 for array
size 2048 bits. The uneven distribution between set and reset operations from experiments
is, naturally, reflected in the probability maps. Reset operations can be seen as having a
distinctly better performance than set operations, with a uniform probability = 1 over the
whole array. To get a figure of this performance, the average switching probability, with
Seminar report 2024

standard deviation, for a given array size was calculated, which can be seen in figures 37 and
38 for array sizes 1024 and 2048 bits respectively. The plots are reminiscent of figure 23,
which is expected. In particular the asymmetry between set and reset operations is clear.
The probability of switching decreases with array size, while the spread increases with array
size. The spread of the probabilities is low for large and small voltage amplitudes, while
increasing for intermediate amplitudes. This is due to the fact that a larger array has a larger
distribution of access voltage, and as such the probability of switching a random cell has a
wider range.
Figure 34: Access voltage bitmap for a 2048 bit Figure 35: Set probability map for a
2048 bit array and voltage amplitude 1 V. The pulse width array. The pulse width is
fixed at
10 ns and is fixed at 10 ns and resistivity 5.8×10−8 Ω m resistivity
5.8×10−8 Ω m

Figure 36: Reset probability map for a 2048 bit array

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Figure 37: Average switching probability and standard deviation for array size = 1024 bit
Figure 38: Average switching probability and standard deviation for array size = 2048 bit

CHAPTER 5

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5 Discussion
The work presented in this thesis can be separated into two distinct sections, where in the
first part characterisation of RRAM devices was conducted, and in the second part, modelling
and simulations were performed using realistic values and data taken from the measured
RRAM devices in the first part.
1. Experimental Part
For the experimental part the goal was to set up a 1T1R structure that was functional enough
to show switching behaviours that are distinct to RRAM, as well as good endurance. The
RRAM material stack that was used had been previously developed in LNL with HfO 2 as oxide
layer, TiN TE and ITO BE. The FET was also developed previously and consisted of arrays if
NW FET’s. Several devices were examined, but the device presented in this work yielded the
best results. Both the FET, RRAM and integration of both devices showed clear
characteristics, yielding a wide resistance widow and strong endurance. The device was
measured for 1.5 V stop voltage and 1 V stop voltage. The RRAM had a mean LRS of 58-89
kΩ and a HRS of 46-107 MΩ, showing an excellent resistance window. The spread of
resistances is lower for LRS, which is due to the compliance set by the transistor. For the HRS
the spread of the resistances are within a good margin to allow for single-bit storage.
Endurance measurements were made on the structure, which exceeded 2 million switching
cycles, which is a result that is impressive in itself, though it should be mentioned that several
other devices of the same RRAM die showed poor endurance. While this is mainly a question
of the yield of the specific RRAM stack, it is hard to generalise this result. Even so, an
excellent endurance using a NW transistor and a thin high-k dielectric film is generally a hard
task to achieve. Compared to DRAM and SRAM, where > 1015 endurance has been achieved,
RRAM lags behind [24]. What is important, though, is that RRAM is non-volatile. Compared
to contemporary non-volatile flash memory, which has up to 1012 endurance [24]. Although
this figure is higher, RRAM is still in its infancy and holds great promise with future
improvements. Furthermore, RRAM performance does not degrade with scaling, due to the
small size of the filament, while flash memory is reliant on floating gates, whose
performance does degrade with scaling.
There are a few other things that have been revealed in the endurance data. If we turn to
figure 24, both the HRS and LRS of the cell increase close to one million cycles. The increase
of LRS in particular might indicate that the device approaches switching failure. This is in
comparison to figure 25 which does not show this trend. This shows that a too high switching
voltage might induce switching failure. This result is in agreement with [25], where it is
showed that stopping voltage is the primary reason for switching failure, as opposed to pulse

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widths. This failure of switching with higher stop voltages can be explained by looking to the
workings of the ITO-HfO2 -TiN composition. As the oxygenvacancy filament is formed, oxygen
ions migrate towards the oxygen rich ITO top electrode. The ITO is eventually depleted of
oxygen-vacancies and reaches a saturated self- compliance of the current [26]. The larger
the stop voltage becomes, the further in the oxygen ions migrate in the ITO and, as a result,
they become more dispersed. In order to reverse this dispersion a larger backward bias is
needed to rupture the filament. Since the same magnitude of the voltage was used in our
experiment, the LRS becomes higher, which might lead to failure.
The cumulative switching probability for both set and reset operations were extracted. For
this device the striking difference between set and reset operations was the asymmetry. This
shows the effect of stopping voltage has on the stability of the filament. A too large stop
voltage might give off unintentional switching, as figure 22 shows switching voltages as low
as a few mV’s. For application purposes this would be a significant parameter to consider,
since it has a direct effect on the biasing.
2. Simulations
The structure and goals of the simulation part of the work was evolving during the project,
but the initial plan for the simulations was to set up a working framework to simulate the
performance of RRAM crossbar arrays using experimental data. The investigation started
from simulation in ADS (no presentable models were made). While ADS was successful to
investigate compact RRAM models ([27]), it was eventually decided that for the purpose of
signal loss for large arrays it would be more fruitful to use Python as the framework, since
the workings of filament- and conduction-mechanics were seen as irrelevant for large scale
simulations.
A model for passive arrays from [15] was used specifically as a starting point, where Kirchoff’s
continuity equations were used to calculate the voltage propagation. The model had no
selector device, and simulated the
sneak-path currents that occur. This model was included in the work as a motivation for why
to include selectors in the first place. The cells were modelled by developing an integrated
NWRRAM small-signal model, which included both parasitic and non-parasitic capacitances.
Moreover, analytical expressions for fringe capacitances were incorporated in the model.
The system level passive array model and cell-level small-signal model were joined to form
a 1T1R array that was used to simulate signal losses. Within this framework a worst-case
scenario analysis was done for access voltage and read margin while varying pulse width,
resistivity and node size. The results show that for array sizes above 1000 bits there is a
significant loss for high speed or high density arrays. This result shows that the array size is
high and stands to compete with current technology array sizes [5], and shows that 1T1RNW
arrays show great potential even if capacitances disturb the signal for larger arrays. On the
other hand, it is worth noting that RRAM arrays for incomputing structures, which require
high speed signalling, might meet new difficulties for higher density architectures, like 3D

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stacked arrays. On the other hand, for purposes which do not require ultra fast operations,
like pure memory applications, denser and larger arrays would be less hindered by NW
technology.
The access voltage was mapped to a probability map, using the measured switching
probabilities. To get a quantitative figure of this distribution, the average switching
probability of a given array size was calculated and it was showed that the probability
decreased with array size, while the spread of switching increased with array size. This type
of analysis could prove useful for application purposes that include stochastic switching of
cells, which is a property that is considered important for hyper-dimensional computing
applications [7, 8].
The models used in the simulations are subject to some sources of error. Most notably, the
ca- pacitances used in a run are entirely analytical and might be over-estimated. Numerical
simulations concerning capacitances would give a more detailed picture, and could be used
to compare the analytical results of this work for small arrays. Another uncertainty concerns
the combination of the three-port 1T1R cell model and the two-port array model. The
pathway of the true signal propagation is more complex than modelled in the array. Still, this
shows no significant losses in the WL arises in these structures.
The project could be improved in a number of ways, which were considered but not
implemented due to lack of time. One thing would be to compare the results with dedicated
circuit-design simulation frameworks, like ADS. This comparison would elucidate some
possible errors that the analytical expres- sions might give rise to. Another thing that could
be improved is the RRAM device that were chosen in the experiment. To get a sounder
correspondence between experiment and simulation, an actual in- tegrated NWRRAM 1T1R
cell should be measured. At the time of writing this thesis, such structures are in
development at Lund NanoLab.
5.3 Summary and Outlook
This project set out to examine the workings of RRAM arrays using experimental data. The
general theory of filament formation and switching mechanism for oxide-based RRAMs was
given. Furthermore, the technology of crossbararrays and their importance for applications
such as neuromorphic circuits and hyper-dimensional computing was discussed. A 1T1R
device was characterised by applying voltage pulses. The devices showed excellent
endurance performance, exceeding 2 million cycles. Moreover, it had a wide resistance
window.
The second part of this work used the measured data to show how this type of device would
behave in a nanowire array environment. The simulations showed that even for small
technology nodes large arrays (> 1000 bits per row) could reliably be constructed, with good
access voltages and switching probabilities.
Specifically, the results show that it is possible to integrate > Mbit sub-arrays with low-
voltage 10 ns pulses, providing a solid foundation for larger Gbit memory sizes, which are

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comparable with current DRAM and NAND technology. The advantage of RRAM will be, for
one, its excellent scalability .
Secondly, the non-volatility and low-voltage operation will make RRAM an ultra-low-power
choice for random access applications. This stands in contrast to the constant power supply
needed to refresh DRAM memory cells. As such, the outlook for the future of RRAM
technology is promising.

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CHAPTER 6

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