Lab 3

ECE 2060 (9148)

Dominic Doan, Logan Costa, Guanran Hao

Following the ECE 2060 Lab 3 presentation, we tested the two circuits that we created in
ModelSim via both a schematic and by code. We first constructed a 2 to 4 Decoder as a scematic
and as code before testing it in ModelSim. Then, we constructed a 4 to 2 Encoder as a schematic
and as code before testing it in ModelSim. Each circuit functioned as expected in accordance
with the truth tables given in the Lab 3 presentation.

Introduction:

The function of Encoders and Decoders can vary with by application, but their general
function is to convert information from one length of bit to another. In the Lab performed this
day, we constructed a 2 to 4 Decoder and 4 to 2 Encoder according to truth tables given in the
ECE 2060 Labs 3 presentation. The Encoders and Decoders were constructed as both a
schematic and code to be them tested in ModelSim for their inputs and outputs to match those of
the truth tables.

Experimental Methodology:

We followed the Lab 3 guide found in the ECE 2060 Labs website to determine the K-
Maps, schematics, and VHDL code of the 2 to 4 Decoder and 4 to 2 Encoder.

Firstly, we were given a table of two inputs and four outputs for the 2 to 4 Decoder,
found in ECE 2060 Labs. From the table, we made a K-Map for the four outputs as shown
below. From each output, we determined the inputs needed to produce a high output. With the
expressions, we constructed a schematic in a .bdf file to produce the outputs with the inputs we
determined. After schematic construction, we imported the file into ModelSim to test the inputs
and outputs, matching the table given through the presentation.
 Figure 1: K-Maps and Expressions of 2 to 4 Decoder

After simulating the schematic, we opened a new .vhd file to construct a coded version of
the 2 to 4 Decoder, guided by Figure 2 in ECE 2060 Lab 3. After successfully constructing the
code, we imported the code into ModelSim to test the inputs and outputs, matching the graph
from the schematic and table from the presentation.

We then were given another table of four inputs and two outputs for the 4 to 2 Encoder,
found from the ECE 2060 Labs 3 presentation. We constructed K-Maps for the two outputs as
shown below. From each output, we devised an expression that resulted in a high output while
using the fewest amount of gates as possible by blocking off eight minterms at a time. With the
expressions, we constructed a schematic in a new .bdf file. After construction, we imported the
schematic into ModelSim to test the inputs and outputs, matching the table given in the
presentation.
 Figure 2: K-Maps and Expressions of 4 to 2 Encoder

After simulating the schematic, we opened a new .vhd file to create a coded version of
the 4 to 2 Encoder using the expressions we found from K-Mapping the table. The form looked
similar to the 2 to 4 Decoder. After constructing the Encoder, we imported the file into
ModelSim to test the inputs and outputs, matching the graph from the schematic and table from
the presentation.

Results:

The following figures are screenshots of the schematics, codes, and simulations of the 2
to 4 Decoder and 4 to 2 Encoder, all in accordance with the Encoder and Decoder truth tables
given in the ECE 2060 Lab 6 presentation.

The schematic pictured below shows the 2 to 4 Decoder in the form of a schematic using
two inputs and four outputs just as the truth table shows.
 Figure 3: Schematic of 2 to 4 Decoder

The simulation below shows how the inputs and outputs of the previous schematic was
tested. Every combination of inputs was simulated to test for appropriate outputs.

Figure 4: Simulation of Schematic of 2 to 4 Decoder

The code pictured below shows the 2 to 4 Decoder in the form of code, calling in two
inputs and four outputs and their behavior as the truth table shows.
 Figure 5: Code of 2 to 4 Decoder

The simulation below shows how the inputs and outputs of the previous code was tested.
Every combination of inputs was simulated to test for appropriate outputs.

Figure 6: Simulation of Code of 2 to 4 Decoder

The schematic pictured below shows the 4 to 2 Encoder in the form of a schematic using
four inputs and two outputs just as the truth table shows.
 Figure 7: Schematic of 4 to 2 Encoder

The simulation below shows how the inputs and outputs of the previous schematic was
tested. Every combination of inputs was simulated to test for appropriate outputs.

Figure 8: Simulation of 4 to 2 Encoder

The code pictured below shows the 4 to 2 Encoder in the form of code, calling in four
inputs and two outputs and their behavior as the truth table shows.
 Figure 9: Code of 4 to 2 Encoder

The simulation below shows how the inputs and outputs of the previous code was tested.
Every combination of inputs was simulated to test for appropriate outputs.

Figure 10: Simulation of code of 4 to 2 Encoder

Discussion:
1. You would design a 16-4 multiplexer since 2^4 = 16 and you have 16 inputs.
2. You would design a demultiplexer circuit. It would require 4 bits from the output port, since there
are 14 outputs. But because you only need 14 of the 16 outputs, you would have 2 unused
combinations.
3. D(0) = A(1) + A(3) + A(5) + A(7)
D(1) = A(2) + A(3) + A(6) + A(7)
D(2) = A(4) + A(5) + A(6) + A(7)

Conclusion:

In this lab, we gained more experience with gate-level design, VHDL, and ModelSim. We
created a 2 to 4 Decoder and a 4 to 2 Encoder with both gates and VHDL, and then simulated
them in ModelSim to gain more understanding of how to use all of them.
Acknowledgements:

Thank you to the laboratory teaching assistants and staff for their excellent guidance and
assistance. Thanks to the lab for providing equipment and resources.

References:

ECE 2060 Labs, “Lab 3 – Encoders and Decoders,” OSU Department of Electrical & computer
Engineering, https://u.osu.edu/ece2060labs/labs/lab-03/.