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DRV8848
SLLSEL7A – OCTOBER 2014 – REVISED NOVEMBER 2015

DRV8848 Dual H-Bridge Motor Driver

1 Features 3 Description
1• Dual H-Bridge Motor Driver The DRV8848 provides a dual H-bridge motor driver
for home appliances and other mechatronic
– Single/Dual Brushed DC applications. The device can be used to drive one or
– Stepper two DC motors, a bipolar stepper motor, or other
• PWM Control Interface loads. A simple PWM interface allows easy
interfacing to controller circuits.
• Optional Current Regulation With 20-μs Fixed Off-
Time The output block of each H-bridge driver consists of
• High Output Current per H-Bridge N-channel and P-channel power MOSFETs
configured as full H-bridges to drive the motor
– 2-A Maximum Driver Current at 12 V and windings. Each H-bridge includes circuitry to regulate
TA = 25°C the winding current using a fixed off-time chopping
– Parallel Mode Available Capable of 4-A scheme. The DRV8848 is capable of driving up to 2
Maximum Driver Current at 12 V and A of current from each output or 4 A of current in
TA = 25°C parallel mode (with proper heat sinking, at 12 V and
TA = 25°C).
• 4- to 18-V Operating Supply Voltage Range
• Low-Current 3-µA Sleep Mode A low-power sleep mode is provided, which shuts
down internal circuitry to achieve very-low quiescent
• Thermally-Enhanced Surface Mount Package current draw. This sleep mode can be set using a
• Protection Features dedicated nSLEEP pin.
– VM Undervoltage Lockout (UVLO) Internal protection functions are provided for UVLO,
– Overcurrent Protection (OCP) OCP, short-circuit protection, and overtemperature.
– Thermal Shutdown (TSD) Fault conditions are indicated by a nFAULT pin.
– Fault Condition Indication Pin (nFAULT) Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
2 Applications
DRV8848 HTSSOP (16) 5.00 mm × 6.40 mm
• Appliances
(1) For all available packages, see the orderable addendum at
• General Brushed and Stepper Motors the end of the data sheet.
• Printers
Simplified Schematic
4 to 18 V

PWM DRV8848
DC
1A
Controller

PWM M
Dual
H-Bridge
VREF
Motor
nFAULT Driver DC
1A M

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features .................................................................. 1 7.3 Feature Description................................................... 9
2 Applications ........................................................... 1 7.4 Device Functional Modes........................................ 14
3 Description ............................................................. 1 8 Application and Implementation ........................ 15
4 Revision History..................................................... 2 8.1 Application Information............................................ 15
8.2 Typical Application ................................................. 15
5 Pin Configuration and Functions ......................... 3
6 Specifications......................................................... 4 9 Power Supply Recommendations...................... 17
9.1 Bulk Capacitance Sizing ......................................... 17
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4 10 Layout................................................................... 18
6.3 Recommended Operating Conditions....................... 4 10.1 Layout Guidelines ................................................. 18
6.4 Thermal Information .................................................. 4 10.2 Layout Example .................................................... 18
6.5 Electrical Characteristics........................................... 5 11 Device and Documentation Support ................. 19
6.6 Timing Requirements ................................................ 6 11.1 Community Resources.......................................... 19
6.7 Typical Characteristics .............................................. 7 11.2 Trademarks ........................................................... 19
7 Detailed Description .............................................. 8 11.3 Electrostatic Discharge Caution ............................ 19
7.1 Overview ................................................................... 8 11.4 Glossary ................................................................ 19
7.2 Functional Block Diagram ......................................... 9 12 Mechanical, Packaging, and Orderable
Information ........................................................... 19

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Original (October 2014) to Revision A Page

• Updated unit for RDS(ON) .......................................................................................................................................................... 5

• Corrected lines for Figure 6 ................................................................................................................................................. 10
• Added Community Resources ............................................................................................................................................. 19

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5 Pin Configuration and Functions

PWP Package
16-Pin HTSSOP
Top View

nSLEEP 1 16 AIN1
AOUT1 2 15 AIN2
AISEN 3 14 VINT
AOUT2 4 GND 13 GND
BOUT2 5 (PPAD) 12 VM
BISEN 6 11 VREF
BOUT1 7 10 BIN2
nFAULT 8 9 BIN1

Pin Functions
PIN
TYPE DESCRIPTION
NAME NO.
AIN1 16 I Bridge A input 1 Controls AOUT1; tri-level input
AIN2 15 I Bridge A input 2 Controls AOUT2; tri-level input
AISEN 3 O Winding A sense Connect to current sense resistor for bridge A, or GND if current regulation is not required
AOUT1 2
O Winding A output
AOUT2 4
BIN1 9 I Bridge B input 1 Controls BOUT1; internal pulldown
BIN2 10 I Bridge B input 2 Controls BOUT2; internal pulldown
BISEN 6 O Winding B sense Connect to current sense resistor for bridge A, or GND if current regulation is not required
BOUT1 7
O Winding B output
BOUT2 5
13
GND PWR Device ground Both the GND pin and device PowerPAD must be connected to ground
PPAD
nFAULT 8 OD Fault indication pin Pulled logic low with fault condition; open-drain output requires external pullup
nSLEEP 1 I Sleep mode input Logic high to enable device; logic low to enter low-power sleep mode; internal pulldown
VINT 14 — Internal regulator Internal supply voltage; bypass to GND with 2.2-μF, 6.3-V capacitor
Connect to motor power supply; bypass to GND with a 0.1- and 10-μF (minimum) ceramic
VM 12 PWR Power supply
capacitor rated for VM
Full-scale current Voltage on this pin sets the full scale chopping current; short to VINT if not supplying an
VREF 11 I
reference input external reference voltage

External Components
COMPONENT PIN 1 PIN 2 RECOMMENDED
CVM VM GND 10-µF (minimum) ceramic capacitor rated for VM
CVM VM GND 0.1-µF ceramic capacitor rated for VM
CVINT VINT GND 6.3-V, 2.2-µF ceramic capacitor
RnFAULT VCC (1) nFAULT >1 kΩ
RAISEN AISEN GND Sense resistor, see Typical Application for sizing
RBISEN BISEN GND Sense resistor, see Typical Application for sizing

(1) VCC is not a pin on the DRV8848, but a VCC supply voltage pullup is required for open-drain output nFAULT; nFAULT may be pulled
up to VINT

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6 Specifications
6.1 Absolute Maximum Ratings
(1)
over operating free-air temperature range referenced with respect to GND (unless otherwise noted)
MIN MAX UNIT
Power supply voltage (VM) –0.3 20 V
Power supply voltage ramp rate (VM) 0 2 V/µs
Internal regulator voltage (VINT) –0.3 3.6 V
Analog input pin voltage (VREF) –0.3 3.6 V
Control pin voltage (AIN1, AIN2, BIN1, BIN2, nSLEEP, nFAULT) –0.3 7 V
Continuous phase node pin voltage (AOUT1, AOUT2, BOUT1, BOUT2) –0.3 VVM + 0.6 V
Continuous shunt amplifier input pin voltage (AISEN, BISEN) (2) –0.6 0.6 V
Peak drive current (AOUT1, AOUT2, BOUT1, BOUT2, AISEN, BISEN) Internally limited A
TJ Operating junction temperature –40 150 °C
Tstg Storage temperature –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Transients of ±1 V for less than 25 ns are acceptable.

6.2 ESD Ratings

VALUE UNIT
Electrostatic Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) ±4000
V(ESD) V
discharge Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2) ±1500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

MIN MAX UNIT
VVM Power supply voltage range (1) 4 18 V
(2)
VVREF Reference rms voltage range 1 3.3 V
ƒPWM Applied STEP signal 0 250 kHz
IVINT VINT external load current 1 mA
(3)
Irms Motor rms current per H-bridge 0 1 A
TA Operating ambient temperature –40 85 °C

(1) Note that RDS(ON) increases and maximum output current is reduced at VM supply voltages below 5 V.
(2) Operational at VREF between 0 and 1 V, but accuracy is degraded.
(3) Power dissipation and thermal limits must be observed.

6.4 Thermal Information

DRV8848
THERMAL METRIC (1) PWP (HTSSOP) UNIT
16 PINS
RθJA Junction-to-ambient thermal resistance 40.3 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 32.7 °C/W
RθJB Junction-to-board thermal resistance 28.7 °C/W
ψJT Junction-to-top characterization parameter 0.6 °C/W
ψJB Junction-to-board characterization parameter 11.4 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 4.7 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.

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6.5 Electrical Characteristics

TA = 25°C, over recommended operating conditions unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLIES (VM, VINT)
VVM VM operating voltage 4 18 V
VVM = 12 V, excluding winding current,
IVM VM operating supply current 2.5 3.8 5.5 mA
nSLEEP = 1
IVMQ VM sleep mode supply current VVM = 12 V, nSLEEP = 0 0.5 1.2 3 μA
tSLEEP Sleep time nSLEEP = 0 to sleep mode 1 ms
tWAKE Wake time nSLEEP = 1 to output transition 1 ms
tON Power-on time VVM > VUVLO rising to output transition 1 ms
VINT VINT voltage VVM > 4 V, IOUT = 0 A to 1 mA 3.13 3.3 3.47 V
LOGIC-LEVEL INPUTS (BIN1, BIN2, NSLEEP)
VIL Input logic low voltage 0 0.7 V
VIH Input logic high voltage 1.6 5.5 V
VHYS Input logic hysteresis 100 mV
IIL Input logic low current VIN = 0 V –1 1 μA
IIH Input logic high current VIN = 5 V 1 30 μA
BIN1, BIN2 200
RPD Pulldown resistance kΩ
nSLEEP 500
AIN1 or AIN2 400 ns
tDEG Input deglitch time
BIN1 or BIN2 200 ns
AIN1 or AIN2 edge to output change 800 ns
tPROP Propagation delay
BIN1 or BIN2 edge to output change 400 ns
TRI-LEVEL INPUTS (AIN1, AIN2)
VIL Tri-level input logic low voltage 0 0.7 V
VIZ Tri-level input Hi-Z voltage 1.1 V
VIH Tri-level input logic high voltage 1.6 5.5 V
VHYS Tri-level input hysteresis 100 mV
IIL Tri-level input logic low current VIN = 0 V –30 –1 μA
IIH Tri-level input logic high current VIN = 5 V 1 30 μA
RPD Tri-level pulldown resistance To GND 170 kΩ
RPU Tri-level pullup resistance To VINT 340 kΩ
CONTROL OUTPUTS (NFAULT)
VOL Output logic low voltage IO = 5 mA 0.5 V
IOH Output logic high leakage VO = 3.3 V –1 1 μA
MOTOR DRIVER OUTPUTS (AOUT1, AOUT2, BOUT1, BOUT2)
VVM = 12 V, I = 0.5 A, TJ = 25°C 550
RDS(ON) High-side FET on-resistance mΩ
VVM = 12 V, I = 0.5 A, TJ = 85°C (1) 660
VVM = 12 V, I = 0.5 A, TJ = 25°C 350
RDS(ON) Low-side FET on-resistance (1)
mΩ
VVM = 12 V, I = 0.5 A, TJ = 85°C 420
IOFF Off-state leakage current VVM = 5 V, TJ = 25°C –1 1 μA
tRISE Output rise time 60 ns
tFALL Output fall time 60 ns
tDEAD Output dead time Internal dead time 200 ns
PWM CURRENT CONTROL (VREF, AISEN, BISEN)
Externally applied VREF input
IREF VVREF = 1 to 3.3 V 1 μA
current
VTRIP xISEN trip voltage For 100% current step with VVREF = 3.3 V 500 mV

(1) Not tested in production; limits are based on characterization data

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Electrical Characteristics (continued)

TA = 25°C, over recommended operating conditions unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tBLANK Current sense blanking time 1.8 μs
AISENSE Current sense amplifier gain Reference only 6.6 V/V
tOFF Current control constant off time 20 μs
PROTECTION CIRCUITS
VVM falling; UVLO report 2.9
VUVLO VM undervoltage lockout V
VVM rising; UVLO recovery 3
IOCP Overcurrent protection trip level 2 A
tDEG Overcurrent deglitch time 2.8 μs
tOCP Overcurrent protection period 1.6 ms
(1)
TTSD Thermal shutdown temperature Die temperature TJ 150 160 180 °C
(1)
THYS Thermal shutdown hysteresis Die temperature TJ 50 °C

6.6 Timing Requirements

TA = 25°C, over recommended operating conditions unless otherwise noted
NO. MIN MAX UNIT
1 t1 Delay time, xIN1 to xOUT1 100 600 ns
2 t2 Delay time, xIN2 to xOUT1 100 600 ns
3 t3 Delay time, xIN1 to xOUT2 100 600 ns
4 t4 Delay time, xIN2 to xOUT2 100 600 ns
5 tF Output rise time 50 150 ns
6 tR Output fall time 50 150 ns

xIN1

xIN2 80% 80%

1 2 4
xOUTx
xOUT1 z z 20% 20%

5
6
xOUT2 z z
Figure 1. Timing Diagram

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6.7 Typical Characteristics

4.5 4
± ƒ& 85°C ± ƒ&
25°C 125°C 3.5 25°C
4 85°C
3 125°C
2.5
3.5
IVM (mA)

IVM (mA)
2

1.5
3
1

2.5 0.5

2 -0.5
0 5 10 15 20 0 5 10 15 20
VVM (V) D001
VVM (V) D002

Figure 2. IVM vs VVM Figure 3. IVMQ vs VVM

1.8 1.8
± ƒ& 85°C 4V
1.6 25°C 125°C 12 V
1.6 18 V
1.4
RDSON HS + LS (:)

RDSON HS + LS (:)

1.2 1.4

1
1.2
0.8

0.6 1

0.4
0.8
0.2

0 0.6
0 5 10 15 20 -50 0 50 100 150
VVM (V) D003
TA (°C) D004

Figure 4. RDSON vs VVM Figure 5. RDSON vs Temperature

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7 Detailed Description

7.1 Overview
The DRV8848 is an integrated motor driver solution for two DC motors or a bipolar stepper motor. The device
integrates two H-bridges that use NMOS low-side drivers and PMOS high-side drivers and current sense
regulation circuitry. The DRV8848 can be powered with a supply range between 4 to 18 V and is capable of
providing an output current to 1-A rms.
A simple PWM interface allows easy interfacing to the controller circuit.
The current regulation uses a fixed off-time (tOFF) PWM scheme. The current regulation trip point is controlled by
the value of the sense resistor and the voltage applied to VREF.
A low-power sleep mode is included, which allows the system to save power when not driving the motor.

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7.2 Functional Block Diagram

VM
VM

VM Internal Ref and VINT

Regs
0.1 µF 10 µF 2.2 µF

VREF
VM

VINT

AOUT1
AIN1
Gate
VINT
Drive DCM Step
and VM Motor
AIN2
OCP

AOUT2
BIN1

AISEN
ISEN
BIN2 optional
Logic VREF VM

VINT
nSLEEP
BOUT1

nFAULT Gate
Drive DCM
and VM
OCP
Over-
Temp BOUT2

BISEN
ISEN
optional
VREF

PPAD GND

7.3 Feature Description

7.3.1 PWM Motor Drivers
DRV8848 contains two identical H-bridge motor drivers with current-control PWM circuitry. Figure 6 shows a
block diagram of the circuitry.

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Feature Description (continued)

OCP VM
VM

xOUT1
xIN1
Pre- Step
xIN2 drive Motor

xOUT2
PWM

OCP

- A=6.6
xISEN

+
Optional

VREF Internal
reference

Figure 6. PWM Motor Driver Circuitry

7.3.2 Bridge Control

Table 1 shows the logic for the inputs xIN1 and xIN2.

Table 1. Bridge Control

xIN1 xIN2 xOUT1 xOUT2 Function (DC Motor)
0 0 Z Z Coast (fast decay)
0 1 L H Reverse
1 0 H L Forward
1 1 L L Brake (slow decay)

SPACE

NOTE
Pins AIN1 and AIN2 are tri-level, so when they are left Hi-Z, they are not internally pulled
to logic low. When AIN1 or AIN2 are set to Hi-Z and not in parallel mode, the output driver
maintains the previous state.

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7.3.3 Parallel Operation

The two drivers can be used in parallel to deliver twice the current to a single motor. To enter parallel mode,
AIN1 and AIN2 must be left Hi-Z during power-up or when exiting sleep mode (nSLEEP toggling from 0 to 1).
BIN1 and BIN2 are used to control the drivers. Tie AISEN and BISEN to a single sense resistor if current control
is desired. To exit parallel mode, AIN1 and AIN2 must be driven high or low and the device must be powered-up
or exit sleep mode. Figure 7 shows a block diagram of the device using parallel mode.

VM

AOUT1
AIN1

Gate
Drive
AIN2 and VM
OCP

AOUT2
BIN1

AISEN
ISEN
BIN2
Controller Logic VM

nSLEEP
BOUT1

Gate
Drive DCM
and VM
OCP

BOUT2

BISEN
ISEN
optional
VREF

Figure 7. Parallel Mode Operation

7.3.4 Current Regulation

The current through the motor windings is regulated by a fixed-off-time PWM current regulation circuit. With DC
brushed motors, current regulation can be used to limit the stall current (which is also the startup current) of the
motor.
Current regulation works as follows:
When an H-bridge is enabled, current rises through the winding at a rate dependent on the supply voltage and
inductance of the winding. If the current reaches the current chopping threshold, the bridge disables the current
for a time tOFF before starting the next PWM cycle. Note that immediately after the current is enabled, the voltage
on the xISEN pin is ignored for a period of time (tBLANK) before enabling the current sense circuitry. This blanking
time also sets the minimum on-time of the PWM cycle.

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The PWM chopping current is set by a comparator which compares the voltage across a current sense resistor,
connected to the xISEN pin, with a reference voltage. The reference voltage is derived from the voltage applied
to the VREF pin and it is VVREF / 6.6. The VREF pin can be tied, on board, to the 3.3 V – VINT pin, or it can be
externally forced to a desired VREF voltage.
The full scale chopping current in a winding is calculated as follows:
VVREF
IFS
6.6 u RISENSE
where
• IFS is the regulated current.
• VVREF is the voltage on the VREF pin.
• RISENSE is the resistance of the sense resistor. (1)
Example: If VVREF is 3.3 V and a 500-mΩ sense resistor is used, the full-scale chopping current is 3.3 V / (6.6 ×
500 mΩ) = 1 A.
Note that if the current control is not needed, the xISEN pins may be connected directly to ground. In this case,
VREF should be connected to VINT.

7.3.5 Current Recirculation and Decay Modes

During PWM current chopping, the H-bridge is enabled to drive current through the motor winding until the PWM
current chopping threshold is reached (see case 1 in Figure 8).
After the chopping current threshold is reached, the drive current is interrupted, but due to the inductive nature of
the motor, current must continue to flow for some period of time. This is called recirculation current. To handle
this recirculation current, the DRV8848 H-bridge operates in mixed decay mode.
Mixed decay is a combination of fast and slow decay modes. In fast decay mode, the opposite drivers are turned
on to allow the current to decay (see case 2 in Figure 8). If the winding current approaches zero, while in fast
decay, the bridge is disabled to prevent any reverse current flow. In slow decay mode, winding current is
recirculated by enabling both of the low-side FETs in the bridge (see case 3 in Figure 8). Mixed decay starts with
fast decay, then goes to slow decay. In DRV8848, the mixed decay ratio is 25% fast decay and 75% slow decay
(as shown in Figure 9).

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xVM

1 Drive Current
1
2 Fast decay
xOUT1 xOUT2 3 Slow decay
2

Figure 8. Decay Modes

PWM
ON PWM OFF (tOFF)

Mixed Decay
25%

Itrip 25% of tOFF

PWM CYCLE

Figure 9. Mixed Decay

7.3.6 Protection Circuits

The DRV8848 is fully protected against undervoltage, overcurrent, and overtemperature events.

7.3.6.1 OCP
An analog current limit circuit on each FET limits the current through the FET by limiting the gate drive. If this
analog current limit persists for longer than the OCP deglitch time tOCP, all FETs in the H-bridge are disabled and
the nFAULT pin is driven low. The device remains disabled until the retry time tRETRY occurs. The OCP is
independent for each H-bridge.
Overcurrent conditions are detected independently on both high-side and low-side devices; that is, a short to
ground, supply, or across the motor winding all result in an OCP event. Note that OCP does not use the current
sense circuitry used for PWM current control, so OCP functions even without presence of the xISEN resistors.
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7.3.6.2 TSD
If the die temperature exceeds safe limits TTSD, all FETs in the H-bridge are disabled and the nFAULT pin is
driven low. After the die temperature has fallen to a safe level, operation automatically resumes. The nFAULT pin
is released after operation has resumed.

7.3.6.3 UVLO
If at any time the voltage on the VM pin falls below the UVLO falling threshold voltage, VUVLO, all circuitry in the
device is disabled, and all internal logic is reset. Operation resumes when VVM rises above the UVLO rising
threshold. The nFAULT pin is driven low during an undervoltage condition and is released after operation has
resumed.

Table 2. Fault Handling

INTERNAL
FAULT ERROR REPORT H-BRIDGE RECOVERY
CIRCUITS
VM undervoltage (UVLO) nFAULT unlatched Disabled Shut down System and fault clears on recovery
System and fault clears on recovery and
Overcurrent (OCP) nFAULT unlatched Disabled Operating
motor is driven after time, tRETRY
Thermal shutdown (TSD) nFAULT unlatched Disabled Operating System and fault clears on recovery

7.4 Device Functional Modes

The DRV8848 is active unless the nSLEEP pin is brought logic low. In sleep mode, the VINT regulator is
disabled and the H-bridge FETs are disabled Hi-Z. Note that tSLEEP must elapse after a falling edge on the
nSLEEP pin before the device is in sleep mode. The DRV8848 is brought out of sleep mode automatically if
nSLEEP is brought logic high. Note that tWAKE must elapse before the output change state after wake-up.
When VVM falls below the VM UVLO threshold (VUVLO), the output driver, internal logic, and VINT regulator are
reset.

Table 3. Functional Modes

MODE CONDITION H-BRIDGE VINT
4 V < VVM < 18 V
Operating Operating Operating
nSLEEP pin = 1
4 V < VVM < 18 V
Sleep Disabled Disabled
nSLEEP pin = 0
Fault Any fault condition met Disabled Depends on fault

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8 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

8.1 Application Information

The DRV8848 is used in stepper or brushed DC motor control.

8.2 Typical Application

The user can configure the DRV8848 with the following design procedure.

1 16
nSLEEP AIN1

2 15
AOUT1 AIN2
500 PŸ 3 14
DCM AISEN VINT
2.2 µF
4 DRV8848 13
AOUT2 GND
10 µF 0.1 µF
5 12
BOUT2 VM VM
GND
500 PŸ 6 11
DCM BISEN (PPAD) VREF

7 10
BOUT1 BIN2
8 9
nFAULT BIN1

10 NŸ
VCC
logic supply

Figure 10. Typical Application Schematic

8.2.1 Design Requirements

Table 4 gives design input parameters for system design.

Table 4. Design Parameters

DESIGN PARAMETER REFERENCE EXAMPLE VALUE
Nominal supply voltage 12 V
VVM
Supply voltage range 4 to 18 V
Motor winding resistance RL 3 Ω/phase
Motor winding inductance LL 330 µH/phase
Target chopping current ICHOP 500 mA
Chopping current reference voltage VVREF 3.3 V

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8.2.2 Detailed Design Procedure

8.2.2.1 Current Regulation

The chopping current (ICHOP) is the maximum current driven through either winding. This quantity depends on the
sense resistor value (RXISEN).
VVREF
ICHOP
6.6 u R XISEN (2)
ICHOP is set by a comparator which compares the voltage across RXISEN to a reference voltage. Note that ICHOP
must follow Equation 3 to avoid saturating the motor.
VVM (V)
ICHOP (A)
RL (:) 2 u RDS(ON) (:) R XISEN (:)

where
• VVM is the motor supply voltage.
• RL is the motor winding resistance. (3)

8.2.3 Application Curves

AIN1 Fast decay

Current trip point

AIN2 Slow decay

I Motor

Figure 11. Current Regulation Figure 12. Stepper Mode Operation

16 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated

Product Folder Links: DRV8848

 DRV8848
www.ti.com SLLSEL7A – OCTOBER 2014 – REVISED NOVEMBER 2015

9 Power Supply Recommendations

The DRV8848 is designed to operate from an input voltage supply (VVM) range between 4 and 18 V. Place a 0.1-
µF ceramic capacitor rated for VM as close to the DRV8848 as possible. In addition, the user must include a bulk
capacitor of at least 10 µF on VM.

9.1 Bulk Capacitance Sizing

Bulk capacitance sizing is an important factor in motor drive system design. It depends on a variety of factors
including:
• Type of power supply
• Acceptable supply voltage ripple
• Parasitic inductance in the power supply wiring
• Type of motor (brushed DC, brushless DC, stepper)
• Motor startup current
• Motor braking method
The inductance between the power supply and motor drive system limits the rate that current can change from
the power supply. If the local bulk capacitance is too small, the system responds to excessive current demands
or dumps from the motor with a change in voltage. Size the bulk capacitance to meet acceptable voltage ripple
levels.
The data sheet provides a recommended minimum value, but system-level testing is required to determine the
appropriate-sized bulk capacitor.

Parasitic Wire
Inductance
Power Supply Motor Drive System

VM

+ + Motor
± Driver

GND

Local IC Bypass
Bulk Capacitor Capacitor

Figure 13. Setup of Motor Drive System With External Power Supply

Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback 17

Product Folder Links: DRV8848
DRV8848
SLLSEL7A – OCTOBER 2014 – REVISED NOVEMBER 2015 www.ti.com

10 Layout

10.1 Layout Guidelines

Bypass the VM terminal to GND using a low-ESR ceramic bypass capacitor with a recommended value of 10 μF
rated for VM. Place this capacitor as close to the VM pin as possible with a thick trace or ground plane
connection to the device GND pin.
Bypass VINT to ground with a ceramic capacitor rated 6.3 V. Place this bypassing capacitor as close to the pin
as possible.

10.2 Layout Example

nSLEEP AIN1
2.2 µF
AOUT1 AIN2

AISEN VINT

RAISEN AOUT2 GND

BOUT2 VM

BISEN VREF

RBISEN BOUT1 BIN2 10 µF

nFAULT BIN1

Figure 14. Layout Recommendation

18 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated

Product Folder Links: DRV8848

 DRV8848
www.ti.com SLLSEL7A – OCTOBER 2014 – REVISED NOVEMBER 2015

11 Device and Documentation Support

11.1 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.

11.2 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

11.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback 19

Product Folder Links: DRV8848
 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

DRV8848PWP ACTIVE HTSSOP PWP 16 90 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 DRV8848

DRV8848PWPR ACTIVE HTSSOP PWP 16 2000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 DRV8848

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 29-Feb-2024

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DRV8848PWPR HTSSOP PWP 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
DRV8848PWPR HTSSOP PWP 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 29-Feb-2024

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
DRV8848PWPR HTSSOP PWP 16 2000 356.0 356.0 35.0
DRV8848PWPR HTSSOP PWP 16 2000 350.0 350.0 43.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 29-Feb-2024

TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
DRV8848PWP PWP HTSSOP 16 90 530 10.2 3600 3.5

Pack Materials-Page 3
 PACKAGE OUTLINE
PWP0016C SCALE 2.500
TM
PowerPAD TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

6.6 C
TYP
A 6.2
PIN 1 INDEX 0.1 C
AREA 14X 0.65 SEATING
16 PLANE
1

2X
5.1
4.55
4.9
NOTE 3

8
9
0.30
4.5 16X
B 0.19
4.3
0.1 C A B
SEE DETAIL A

(0.15) TYP

2X 0.95 MAX
NOTE 5 4X (0.3)
8 9
2X 0.23 MAX
NOTE 5

2.31 17
0.25
1.75
GAGE PLANE 1.2 MAX

0.75 0.15
1 16 0 -8 0.50 0.05
DETAIL A
A 20

THERMAL 2.46 TYPICAL

PAD 1.75

4224559/B 01/2019
PowerPAD is a trademark of Texas Instruments.
NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
5. Features may differ or may not be present.

www.ti.com
 EXAMPLE BOARD LAYOUT
PWP0016C TM
PowerPAD TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

(3.4)
NOTE 9
(2.46)
16X (1.5)
SYMM METAL COVERED
BY SOLDER MASK
1
16X (0.45) 16 (1.2) TYP

(R0.05) TYP

SYMM 17 (2.31)
(5)
(0.6) NOTE 9
14X (0.65)

( 0.2) TYP
VIA 8 9

SOLDER MASK (1) TYP

DEFINED PAD SEE DETAILS
(5.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 10X

SOLDER MASK METAL UNDER SOLDER MASK

METAL
OPENING SOLDER MASK OPENING

EXPOSED METAL EXPOSED METAL

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
SOLDER MASK DETAILS
15.000

4224559/B 01/2019
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
10. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged
or tented.

www.ti.com
 EXAMPLE STENCIL DESIGN
PWP0016C TM
PowerPAD TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

(2.46)
BASED ON
16X (1.5) METAL COVERED
0.125 THICK
STENCIL BY SOLDER MASK
1
16X (0.45) 16

(R0.05) TYP

(2.31)
SYMM 17 BASED ON
0.125 THICK
STENCIL
14X (0.65)

8 9

SYMM SEE TABLE FOR

DIFFERENT OPENINGS
FOR OTHER STENCIL
(5.8) THICKNESSES

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE: 10X

STENCIL SOLDER STENCIL

THICKNESS OPENING
0.1 2.75 X 2.58
0.125 2.46 X 2.31 (SHOWN)
0.15 2.25 X 2.11
0.175 2.08 X 1.95

4224559/B 01/2019
NOTES: (continued)

11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.

www.ti.com
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