2X1 MUX: Its Schematic and Layout

Umeda Ranaveer
Electronics and Communication engineering, B.tech,3 rd year.
Indian Institute of Technology Roorkee
Enrollment Number: 22116097

Abstract: • Cadence Virtuoso Schematic Editor: Used

Multiplexer in digital circuit has many for creating and simulating detailed
inputs (m) with only one output and it is denoted electronic circuit designs at the transistor
by m:1 MUX where m is the number of inputs. It level.
selects only one input (one input is connected to • Cadence Virtuoso Layout Editor: Used for
the output) based on the select line. designing the physical layout of integrated
In this experiment we are going to design circuits (ICs) based on the schematic,
a 2X1 mux’s using a reference circuit, In which ensuring proper connectivity and
the output VOUT is the inverted version of the adherence to design rules.
input (VIN) when CLK = 1. When CLK = 0, the • ADE L (Analog Design Environment L) is
output is disconnected from the input, the power a tool within Cadence Virtuoso used for
supply (VDD) and ground. setting up, running, and analyzing
Implementing its schematic in Cadence Virtuoso simulations of analog and mixed-signal
Schematic Editor and its layout in layout editor circuits at the schematic level.
and verifying mux behavior. • Layout XL: is an interactive tool used for
Using its layout we verified design rule designing and editing the physical layout
check (DRC), Layout-vs-Schematic (LVS) and of circuits, offering features like automated
Parasitic extraction (PEX) and check if the layout routing, real-time design rule checking
follows these rules or not. (DRC), and integration with the schematic
Design: for accurate layout-vs-schematic (LVS)
Using SCL 180nm CMOS process Technology verification.
library in Cadence. Methodology:
PMOS Design Specifications Schematic Design in Cadence Virtuoso Schematic
• Gate width: 1.5 µm Editor
NMOS: • Initiated Cadence Virtuoso Schematic
• Gate width: 0.42 µm Editor and created a new schematic for the
• Reference circuit. 2X1 mux.
• Defined the device geometry:
o Used NMOS and PMOS provided
by tsmc18 library and other
elements like voltage and ground
from analog library.
o Defined the width of PMOS and
NMOS 1.5 um and 0.42 um
respectively.
• Designed an 2X1 mux as shown in the
below figure.

Tools:
The following Cadance Virtuoso tools
were used in this experiment:
 Results:
Symbol for MUX:

• Defined input, output and in-out pins. They

are I1, I2, CLK(or S), VDD, GND, and 2x1 mux transient analysis:
Vout.
• Specified two input signals I1 and I2 in
ADE L ,given a square wave as CLK and
used VDD=1.8v and GND as 0v.
• After specifying all inputs, we performed
transient analysis to check mux behavior.
Layout Design in Cadence Virtuoso Layout Editor.
• Open Cadence Virtuoso Layout Editor and
create a layout for the designed CMOS DRC Check:
inverter. By Using Layout XL and import
all from source to get the schematic pins
and components in layout.
• Design the layout as shown figure/ making
correct connection as schematic using
metal connections. And ensure the
connections follows technological rules
and same as schematic.
LVS Check:

• After completing layout without any errors PEX Check:

run Design Rule Check (DRC) on the
layout to make sure the layout satisfies all
the rules for successful fabrication.
• After DRC, run Layout-vs-Schematic
(LVS) to check whether all the parameters
of the layout match with that of the inverter
schematic you have designed earlier.
• After LVS for getting the values of
parasitic resistance and capacitances due to
metal routing run Parasitic extraction
(PEX).
Conclusion:
• We have verified the mux working from its
transient analysis, where we are getting I1
as output when CLK input 0 and I2 as
output when CLK input is 1.
• We have run DRC, LVS and PEX
successfully and ensured our layout
follows all the rules.

From this experiment, I have gained practical

experience in designing and simulating a CMOS
inverter using industry-standard tools like Cadence
Virtuoso, ADE L and Layout XL. I learned how to
create a schematic and layout, running simulations
to find 2X1 mux characteristics, ensure proper
layout-vs-schematic (LVS) matching, run design
rule checks (DRC) and PEX to meet fabrication
standards. Additionally, I learned how to create
Symbol for a 2x1 MUX for further usage of Mux
in complex circuits. This hands-on experience has
enhanced my understanding of digital circuit
design and verification processes.