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2 X 1 Mux

jim

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vislavathhimabindu20
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30 views3 pages

2 X 1 Mux

jim

Uploaded by

vislavathhimabindu20
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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2X1 MUX: Its Schematic and Layout

Vislavath Himabindu
Electronics and Communication engineering, B.tech,3rd year.
Indian Institute of Technology Roorkee
Enrollment Number: 22116107

Abstract:
A multiplexer (MUX) in digital circuits has
multiple inputs (m) and a single output, The following Cadance Virtuoso tools were
represented as an m:1 MUX, where m used in this experiment:
indicates the number of inputs. It selects
one input to connect to the output based on  Cadence Virtuoso Schematic Editor: Used
the select line. for creating and simulating detailed
electronic circuit designs at the transistor
In this experiment, we will design a 2:1 level.
MUX using a reference circuit. The output  Cadence Virtuoso Layout Editor: Used for
VOUT will be the inverted version of the designing the physical layout of integrated
selected input VIN when the clock signal circuits (ICs) based on the schematic,
CLK is high (1). When CLK is low (0), the ensuring proper connectivity and
output will be disconnected from the inputs, adherence to design rules.
as well as from the power supply (VDD)  ADE L (Analog Design Environment L) is
and ground. a tool within Cadence Virtuoso used for
setting up, running, and analyzing
We will implement the schematic using simulations of analog and mixed-signal
Cadence Virtuoso Schematic Editor and circuits at the schematic level.
create the layout in the layout editor. The  Layout XL: is an interactive tool used for
behavior of the MUX will be verified designing and editing the physical layout
through simulations. Additionally, we will of circuits, offering features like automated
conduct design rule checks (DRC), layout routing, real-time design rule checking
versus schematic checks (LVS), and (DRC), and integration with the schematic
parasitic extraction (PEX) to ensure that the for accurate layout-vs-schematic (LVS)
layout adheres to all necessary design rules. verification.
Design: Methodology:
Using SCL 180nm CMOS process Technology Schematic Design in Cadence Virtuoso Schematic
library in Cadence. Editor
PMOS Design Specifications  Initiated Cadence Virtuoso Schematic
 Gate width: 1.5 µm Editor and created a new schematic for the
NMOS: 2X1 mux.
 Gate width: 0.42 µm  Defined the device geometry:
 Reference circuit. o Used NMOS and PMOS provided
by tsmc18 library and other
elements like voltage and ground
from analog library.
o Defined the width of PMOS and
NMOS 1.5 um and 0.42 um
respectively.
 Designed an 2X1 mux as shown in the
below figure.

Tools:
Results:
Symbol for MUX:

 Defined input, output and in-out pins. They


are I1, I2, CLK(or S), VDD, GND, and 2x1 mux transient analysis:
Vout.
 Specified two input signals I1 and I2 in
ADE L ,given a square wave as CLK and
used VDD=1.8v and GND as 0v.
 After specifying all inputs, we performed
transient analysis to check mux behavior.
Layout Design in Cadence Virtuoso Layout Editor.
 Open Cadence Virtuoso Layout Editor and
create a layout for the designed CMOS DRC Check:
inverter. By Using Layout XL and import
all from source to get the schematic pins
and components in layout.
 Design the layout as shown figure/ making
correct connection as schematic using
metal connections. And ensure the
connections follows technological rules
and same as schematic.
LVS Check:

 After completing layout without any errors PEX Check:


run Design Rule Check (DRC) on the
layout to make sure the layout satisfies all
the rules for successful fabrication.
 After DRC, run Layout-vs-Schematic
(LVS) to check whether all the parameters
of the layout match with that of the inverter
schematic you have designed earlier.
 After LVS for getting the values of
parasitic resistance and capacitances due to
metal routing run Parasitic extraction
(PEX).
Conclusion:
We have confirmed the functionality of the MUX
through transient analysis, where the output is \( I1
\) when the CLK input is 0 and \( I2 \) when the
CLK input is 1. Additionally, we successfully
completed DRC, LVS, and PEX checks, ensuring
that our layout complies with all required rules.

Through this experiment, I gained practical


experience in designing and simulating a CMOS
inverter using industry-standard tools such as
Cadence Virtuoso, ADE L, and Layout XL. I
learned how to create both schematic and layout
designs, run simulations to analyze the
characteristics of the 2:1 MUX, and ensure proper
layout-vs-schematic (LVS) matching. I also ran
design rule checks (DRC) and performed parasitic
extraction (PEX) to meet fabrication standards.
Furthermore, I learned to create a symbol for the
2:1 MUX for future use in more complex circuits.
This hands-on experience has deepened my
understanding of digital circuit design and
verification processes.

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