Operating Systems – BCS303

MODULE 4: MEMORY MANAGEMENT, VIRTUAL

MEMORY MANAGEMENT
MEMORY MANAGEMENT
3.6 Background
Main Memory
3.6.1 Basic Hardware
3.6.2 Address Binding
3.6.3 Logical versus Physical Address Space
3.6.4 Dynamic Loading
3.6.5 Dynamic Linking and Shared Libraries
3.7 Swapping
3.8 Contiguous Memory Allocation
3.8.1 Memory Mapping & Protection
3.8.2 Memory Allocation
3.8.3 Fragmentation
3.9 Paging
3.9.1 Basic Method
3.9.2 Hardware Support for Paging
3.9.3 Protection
3.9.4 Shared Pages
3.10 Structure of the Page Table
3.10.1 Hierarchical Paging
3.10.2 Hashed Page Tables
3.10.3 Inverted Page Tables
3.11 Segmentation
3.11.1Basic Method
3.11.2Hardware Support
Virtual Memory Management
4.1 Virtual Memory(BACKGROUND)
4.2 Demand Paging
4.2.1 Basic Concepts
4.2.2 Performance
4.3 Copy-on-Write
4.4 Page Replacement
4.4.1 Need for Page Replacement
4.4.2 Basic Page Replacement
4.4.3 FIFO Page Replacement
4.4.4 Optimal Page Replacement
4.4.5 LRU Page Replacement
4.4.6 LRU-Approximation Page Replacement
4.4.6.1 Additional-Reference-Bits Algorithm
4.4.6.2 Second-Chance Algorithm
4.4.6.3 Enhanced Second-Chance Algorithm
4.4.7 Counting-Based Page Replacement
4.5 Allocation of Frames
4.5.1 Minimum Number of Frames
4.5.2 Allocation Algorithms
4.5.3 Global versus Local Allocation
4.6 Thrashing
4.6.1 Cause of Thrashing

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MODULE 3 (CONT.): MEMORY MANAGEMENT

3.6 Main Memory

Basic Hardware
• Program must be
→ brought (from disk) into memory and
→ placed within a process for it to be run.
• Main-memory and registers are only storage CPU can access directly.
• Register access in one CPU clock.
• Main-memory can take many cycles.
• Cache sits between main-memory and CPU registers.
• Protection of memory required to ensure correct operation.
• A pair of base- and limit-registers define the logical (virtual) address space (Figure 3.8 & 3.9).

Figure 3.8 A base and a limit-register define a logical-address space

Figure 3.9 Hardware address protection with base and limit-registers

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3.6.1 Address Binding

• Address binding of instructions to memory-addresses can happen at 3 different stages (Figure 3.10):
1) Compile Time
 If memory-location known a priori, absolute code can be generated.
 Must recompile code if starting location changes.
2) Load Time
 Must generate relocatable code if memory-location is not known at compile time.
3) Execution Time
 Binding delayed until run-time if the process can be moved during its execution from one
memory-segment to another.
 Need hardware support for address maps (e.g. base and limit-registers).

Figure 3.10 Multistep processing of a user-program

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3.6.2 Logical versus Physical Address Space

• Logical-address is generated by the CPU (also referred to as virtual-address).
Physical-address is the address seen by the memory-unit.
• Logical & physical-addresses are the same in compile-time & load-time address-binding methods.
Logical and physical-addresses differ in execution-time address-binding method.
• MMU (Memory-Management Unit)
 Hardware device that maps virtual-address to physical-address (Figure 3.11).
 The value in the relocation-register is added to every address generated by a user-process at
the time it is sent to memory.
 The user-program deals with logical-addresses; it never sees the real physical-addresses.

Figure 3.11 Dynamic relocation using a relocation-register

3.6.3 Dynamic Loading

• This can be used to obtain better memory-space utilization.
• A routine is not loaded until it is called.
• This works as follows:
3.6.3.1 Initially, all routines are kept on disk in a relocatable-load format.
3.6.3.2 Firstly, the main-program is loaded into memory and is executed.
3.6.3.3 When a main-program calls the routine, the main-program first checks to see
whether the routine has been loaded.
3.6.3.4 If routine has been not yet loaded, the loader is called to load desired routine into
memory.
3.6.3.5 Finally, control is passed to the newly loaded-routine.
• Advantages:
1) An unused routine is never loaded.
2) Useful when large amounts of code are needed to handle infrequently occurring cases.
3) Although the total program-size may be large, the portion that is used (and hence loaded)
may be much smaller.
4) Does not require special support from the OS.

3.6.4 Dynamic Linking and Shared Libraries

• Linking postponed until execution-time.
• This feature is usually used with system libraries, such as language subroutine libraries.
• A stub is included in the image for each library-routine reference.
• The stub is a small piece of code used to locate the appropriate memory-resident library-routine.
• When the stub is executed, it checks to see whether the needed routine is already in memory. If not,
the program loads the routine into memory.
• Stub replaces itself with the address of the routine, and executes the routine.
• Thus, the next time that particular code-segment is reached, the library-routine is executed directly,
incurring no cost for dynamic-linking.
• All processes that use a language library execute only one copy of the library code.
Shared libraries
• A library may be replaced by a new version, and all programs that reference the library will
automatically use the new one.
• Version info. is included in both program & library so that programs won't accidentally execute
incompatible versions.

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3.7 Swapping
• A process must be in memory to be executed.
• A process can be
→ swapped temporarily out-of-memory to a backing-store and
→ then brought into memory for continued execution.
• Backing-store is a fast disk which is large enough to accommodate copies of all memory-images for
all users.
• Roll out/Roll in is a swapping variant used for priority-based scheduling algorithms.
 Lower-priority process is swapped out so that higher-priority process can be loaded and
executed.
 Once the higher-priority process finishes, the lower-priority process can be swapped back in
and continued (Figure 3.12).

Figure 3.12 Swapping of two processes using a disk as a backing-store

• Swapping depends upon address-binding:

3.7.2 If binding is done at load-time, then process cannot be easily moved to a different location.
3.7.3 If binding is done at execution-time, then a process can be swapped into a different
memory- space, because the physical-addresses are computed during execution-time.
• Major part of swap-time is transfer-time; i.e. total transfer-time is directly proportional to the amount
of memory swapped.
• Disadvantages:
1) Context-switch time is fairly high.
2) If we want to swap a process, we must be sure that it is completely idle.
Two solutions:
i) Never swap a process with pending I/O.
ii) Execute I/O operations only into OS buffers.

3.8 Contiguous Memory Allocation

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• Memory is usually divided into 2 partitions:

→ One for the resident OS.
→ One for the user-processes.
• Each process is contained in a single contiguous section of memory.

3.8.1 Memory Mapping & Protection

• Memory-protection means
→ protecting OS from user-process and
→ protecting user-processes from one another.
• Memory-protection is done using
→ Relocation-register: contains the value of the smallest physical-address.
→ Limit-register: contains the range of logical-addresses.
• Each logical-address must be less than the limit-register.
• The MMU maps the logical-address dynamically by adding the value in the relocation-register. This
mapped-address is sent to memory (Figure 3.13).
• When the CPU scheduler selects a process for execution, the dispatcher loads the relocation and
limit-registers with the correct values.
• Because every address generated by the CPU is checked against these registers, we can protect the
OS from the running-process.
• The relocation-register scheme provides an effective way to allow the OS size to change dynamically.
• Transient OS code: Code that comes & goes as needed to save memory-space and overhead for
unnecessary swapping.

Figure 3.13 Hardware support for relocation and limit-registers

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3.8.2 Memory Allocation

• Two types of memory partitioning are: 1) Fixed-sized partitioning and
2) Variable-sized partitioning
3.8.2.1 Fixed-sized Partitioning
 The memory is divided into fixed-sized partitions.
 Each partition may contain exactly one process.
 The degree of multiprogramming is bound by the number of partitions.
 When a partition is free, a process is
→ selected from the input queue and
→ loaded into the free partition.
 When the process terminates, the partition becomes available for another process.
3.8.2.2 Variable-sized Partitioning
 The OS keeps a table indicating
→ which parts of memory are available and
→ which parts are occupied.
 A hole is a block of available memory.
 Normally, memory contains a set of holes of various sizes.
 Initially, all memory is
→ available for user-processes and
→ considered one large hole.
 When a process arrives, the process is allocated memory from a large hole.
 If we find the hole, we
→ allocate only as much memory as is needed and
→ keep the remaining memory available to satisfy future requests.
• Three strategies used to select a free hole from the set of available holes.
1) First Fit
 Allocate the first hole that is big enough.
 Searching can start either
→ at the beginning of the set of holes or
→ at the location where the previous first-fit search ended.
2) Best Fit
 Allocate the smallest hole that is big enough.
 We must search the entire list, unless the list is ordered by size.
 This strategy produces the smallest leftover hole.
3) Worst Fit
 Allocate the largest hole.
 Again, we must search the entire list, unless it is sorted by size.
 This strategy produces the largest leftover hole.
• First-fit and best fit are better than worst fit in terms of decreasing time and storage utilization.

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3.8.3 Fragmentation
• Two types of memory fragmentation: 1) Internal fragmentation and
2) External fragmentation
1) Internal Fragmentation
• The general approach is to
→ break the physical-memory into fixed-sized blocks and
→ allocate memory in units based on block size (Figure 3.14).
• The allocated-memory to a process may be slightly larger than the requested-memory.
• The difference between requested-memory and allocated-memory is called internal fragmentation i.e.
Unused memory that is internal to a partition.
2) External Fragmentation
• External fragmentation occurs when there is enough total memory-space to satisfy a request but the
available-spaces are not contiguous. (i.e. storage is fragmented into a large number of small holes).
• Both the first-fit and best-fit strategies for memory-allocation suffer from external fragmentation.
• Statistical analysis of first-fit reveals that
→ given N allocated blocks, another 0.5 N blocks will be lost to fragmentation.
This property is known as the 50-percent rule.
• Two solutions to external fragmentation (Figure 3.15):
1) Compaction
 The goal is to shuffle the memory-contents to place all free memory together in one large
hole.
 Compaction is possible only if relocation is
→ dynamic and
→ done at execution-time.
2) Permit the logical-address space of the processes to be non-contiguous.
 This allows a process to be allocated physical-memory wherever such memory is available.
 Two techniques achieve this solution:
1) Paging and
2) Segmentation.

Figure 3.14: Internal fragmentation Figure 3.15: External fragmentation

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3.9 Paging
• Paging is a memory-management scheme.
• This permits the physical-address space of a process to be non-contiguous.
• This also solves the considerable problem of fitting memory-chunks of varying sizes onto the
backing-store.
• Traditionally: Support for paging has been handled by hardware.
Recent designs: The hardware & OS are closely integrated.

3.9.1 Basic Method

• Physical-memory is broken into fixed-sized blocks called frames(Figure 3.16).
Logical-memory is broken into same-sized blocks called pages.
• When a process is to be executed, its pages are loaded into any available memory-frames from the
backing-store.
• The backing-store is divided into fixed-sized blocks that are of the same size as the memory-frames.

Figure 3.16 Paging hardware

• The page-table contains the base-address of each page in physical-memory.

• Address generated by CPU is divided into 2 parts (Figure 3.17):
3.9.1.1 Page-number(p) is used as an index to the page-table and
3.9.1.2 Offset(d) is combined with the base-address to define the
physical-address. This physical-address is sent to the memory-unit.

Figure 3.17 Paging model of logical and physical-memory

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• The page-size (like the frame size) is defined by the hardware (Figure 3.18).
• If the size of the logical-address space is 2 m, and a page-size is 2n addressing-units (bytes or words)
then the high-order m-n bits of a logical-address designate the page-number, and the n low-order bits
designate the page-offset.

Figure 3.18 Free frames (a) before allocation and (b) after allocation

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3.9.2 Hardware Support for Paging

• Most OS's store a page-table for each process.
• A pointer to the page-table is stored in the PCB.
Translation Lookaside Buffer
• The TLB is associative, high-speed memory.
• The TLB contains only a few of the page-table entries.
• Working:
 When a logical-address is generated by the CPU, its page-number is presented to the TLB.
 If the page-number is found (TLB hit), its frame-number is
→ immediately available and
→ used to access memory.
 If page-number is not in TLB (TLB miss), a memory-reference to page table must be made.
 The obtained frame-number can be used to access memory (Figure 3.19).
 In addition, we add the page-number and frame-number to the TLB, so that they will be found
quickly on the next reference.
• If the TLB is already full of entries, the OS must select one for replacement.
• Percentage of times that a particular page-number is found in the TLB is called hit ratio.
• Advantage: Search operation is fast.
Disadvantage: Hardware is expensive.
• Some TLBs have wired down entries that can't be removed.
• Some TLBs store ASID (address-space identifier) in each entry of the TLB that uniquely
→ identify each process and
→ provide address space protection for that process.

Figure 3.19 Paging hardware with TLB

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3.9.3 Protection
• Memory-protection is achieved by protection-bits for each frame.
• The protection-bits are kept in the page-table.
• One protection-bit can define a page to be read-write or read-only.
• Every reference to memory goes through the page-table to find the correct frame-number.
• Firstly, the physical-address is computed. At the same time, the protection-bit is checked to verify
that no writes are being made to a read-only page.
• An attempt to write to a read-only page causes a hardware-trap to the OS (or memory-protection
violation).
Valid Invalid Bit
• This bit is attached to each entry in the page-table (Figure 3.20).
3.9.3.1 Valid bit: The page is in the process’ logical-address space.
3.9.3.2 Invalid bit: The page is not in the process’ logical-address space.
• Illegal addresses are trapped by use of valid-invalid bit.
• The OS sets this bit for each page to allow or disallow access to the page.

Figure 3.20 Valid (v) or invalid (i) bit in a page-table

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3.9.4 Shared Pages

• Advantage of paging:
3.9.4.1 Possible to share common code.
• Re-entrant code is non-self-modifying code, it never changes during execution.
• Two or more processes can execute the same code at the same time.
• Each process has its own copy of registers and data-storage to hold the data for the process's
execution.
• The data for 2 different processes will be different.
• Only one copy of the editor need be kept in physical-memory (Figure 3.21).
• Each user's page-table maps onto the same physical copy of the editor,
but data pages are mapped onto different frames.
• Disadvantage:
1) Systems that use inverted page-tables have difficulty implementing shared-memory.

Figure 3.21 Sharing of code in a paging environment

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3.10 Structure of the Page Table

1) Hierarchical Paging
2) Hashed Page-tables
3) Inverted Page-tables

3.10.1Hierarchical Paging
• Problem: Most computers support a large logical-address space (2 32 to 264). In these systems, the
page-table itself becomes excessively large.
Solution: Divide the page-table into smaller pieces.
Two Level Paging Algorithm
• The page-table itself is also paged (Figure 3.22).
• This is also known as a forward-mapped page-table because address translation works from the outer
page-table inwards.
• For example (Figure 3.23):
 Consider the system with a 32-bit logical-address space and a page-size of 4 KB.
 A logical-address is divided into
→ 20-bit page-number and
→ 12-bit page-offset.
 Since the page-table is paged, the page-number is further divided into
→ 10-bit page-number and
→ 10-bit page-offset.
 Thus, a logical-address is as follows:

Figure 3.22 A two-level page-table scheme

Figure 3.23 Address translation for a two-level 32-bit paging architecture

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3.10.2Hashed Page Tables

• This approach is used for handling address spaces larger than 32 bits.
• The hash-value is the virtual page-number.
• Each entry in the hash-table contains a linked-list of elements that hash to the same location (to
handle collisions).
• Each element consists of 3 fields:
3.10.2.1 Virtual page-number
3.10.2.2 Value of the mapped page-frame and
3.10.2.3 Pointer to the next element in the linked-list.
• The algorithm works as follows (Figure 3.24):
1) The virtual page-number is hashed into the hash-table.
2) The virtual page-number is compared with the first element in the linked-list.
3) If there is a match, the corresponding page-frame (field 2) is used to form the desired
physical-address.
4) If there is no match, subsequent entries in the linked-list are searched for a matching virtual
page-number.
Clustered Page Tables
• These are similar to hashed page-tables except that each entry in the hash-table refers to several
pages rather than a single page.
• Advantages:
1) Favorable for 64-bit address spaces.
2) Useful for address spaces, where memory-references are noncontiguous and scattered
throughout the address space.

Figure 3.24 Hashed page-table

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3.10.3 Inverted Page Tables

• Has one entry for each real page of memory.
• Each entry consists of
→ virtual-address of the page stored in that real memory-location and
→ information about the process that owns the page.

Figure 3.25 Inverted page-table

• Each virtual-address consists of a triplet (Figure 3.25):

<process-id, page-number, offset>.
• Each inverted page-table entry is a pair <process-id, page-number>
• The algorithm works as follows:
3.10.3.1 When a memory-reference occurs, part of the virtual-address, consisting of
<process-id, page-number>, is presented to the memory subsystem.
3.10.3.2 The inverted page-table is then searched for a match.
3.10.3.3 If a match is found, at entry i-then the physical-address <i, offset> is generated.
3.10.3.4 If no match is found, then an illegal address access has been attempted.
• Advantage:
1) Decreases memory needed to store each page-table
• Disadvantages:
1) Increases amount of time needed to search table when a page reference occurs.
2) Difficulty implementing shared-memory.

3.11 SEGMENTATION
Basic method:
 Most users do not think memory as a linear array of bytes rather the users thinks memory as a
collection of variable sized segments which are dedicated to a particular use such as code,
data, stack, heap etc.
 A logical address is a collection of segments. Each segment has a name and length. The
address specifies both the segment name and the offset within the segments.
 The users specifies address by using two quantities: a segment name and an offset.
 For simplicity the segments are numbered and referred by a segment number. So the
logical address consists of <segment number, offset>.

Hardware support:
 We must define an implementation to map 2D user defined address in to 1D physical
address.

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 This mapping is affected by a segment table. Each entry in the segment table has a
segment base and segment limit. The segment base contains the starting physical address
where the segment resides and limit specifies the length of the segment.

 The use of segment table is shown in the above figure:

 Logical address consists of two parts: segment number‘s’ and an offset‘d’ to that
segment.
 The segment number is used as an index to segment table.
 The offset ’d’ must bi in between 0 and limit, if not an error is reported to OS.
 If legal the offset is added to the base to generate the actual physical address.
 The segment table is an array of base limit register pairs.

Protection and Sharing:

 A particular advantage of segmentation is the association of protection with the segments.
 The memory mapping hardware will check the protection bits associated with each segment
table entry to prevent illegal access to memory like attempts to write in to read-only segment.
 Another advantage of segmentation involves the sharing of code or data. Each process has a
segment table associated with it. Segments are shared when the entries in the segment tables
of two different processes points to same physical location.
 Sharing occurs at the segment table. Any information can be shared at the segment level.
 Several segments can be shared so a program consisting of several segments can be shared.
 We can also share parts of a program.

Advantages:
 Eliminates fragmentation.
 Provides virtual growth.
 Allows dynamic segment growth.
 Assist dynamic linking.
 Segmentation is visible.

Differences between segmentation and paging:-

Segmentation:
 Program is divided in to variable sized segments. x User is responsible for dividing the
program in to segments.
 Segmentation is slower than paging.
 Visible to user.
 Eliminates internal fragmentation.
 Suffers from external fragmentation.
 Process or user segment number, offset to calculate absolute address.
Paging:
 x Programs are divided in to fixed size pages.
 x Division is performed by the OS.
 x Paging is faster than segmentation. x Invisible to user. x Suffers from internal
fragmentation. x No external fragmentation. x Process or user page number, offset to
calculate absolute address.

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MODULE 4 conti…: VIRTUAL MEMORY

4.1Virtual Memory
• In many cases, the entire program is not needed.
For example:
→ Unusual error-conditions are almost never executed.
→ Arrays & lists are often allocated more memory than needed.
→ Certain options & features of a program may be used rarely.
• Benefits of executing a program that is only partially in memory.
 More programs could be run at the same time.
 Programmers could write for a large virtual-address space and need no longer use overlays.
 Less I/O would be needed to load/swap programs into memory, so each user program would
run faster.
• Virtual Memory is a technique that allows the execution of processes that are not completely in
memory (Figure 4.1).
 VM involves the separation of logical-memory as perceived by users from physical-memory.
 VM allows files and memory to be shared by several processes through page-sharing.
 Logical-address space can .‟. be much larger than physical-address space.
• Virtual-memory can be implemented by:
1) Demand paging and
2) Demand segmentation.
• The virtual (or logical) address-space of a process refers to the logical (or virtual) view of how a
process is stored in memory.
• Physical-memory may be organized in page-frames and that the physical page-frames assigned to a
process may not be contiguous.
• It is up to the MMU to map logical-pages to physical page-frames in memory.

Figure 4.1 Diagram showing virtual memory that is larger than physical-memory

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4.2 Demand Paging

• A demand-paging system is similar to a paging-system with swapping (Figure 4.2).
• Processes reside in secondary-memory (usually a disk).
• When we want to execute a process, we swap it into memory.
• Instead of swapping in a whole process, lazy swapper brings only those necessary pages into
memory.

Figure 4.2 Transfer of a paged memory to contiguous disk space

4.2.1 Basic Concepts

• Instead of swapping in a whole process, the pager brings only those necessary pages into memory.
• Advantages:
1) Avoids reading into memory-pages that will not be used,
2) Decreases the swap-time and
3) Decreases the amount of physical-memory needed.
• The valid-invalid bit scheme can be used to distinguish between
→ pages that are in memory and
→ pages that are on the disk.
1) If the bit is set to valid, the associated page is both legal and in memory.
2) If the bit is set to invalid, the page either
→ is not valid (i.e. not in the logical-address space of the process) or
→ is valid but is currently on the disk (Figure 4.3).

Figure 4.3 Page-table when some pages are not in main-memory

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• A page-fault occurs when the process tries to access a page that was not brought into memory.
• Procedure for handling the page-fault (Figure 4.4):
1) Check an internal-table to determine whether the reference was a valid or an invalid memory
access.
2) If the reference is invalid, we terminate the process.
If reference is valid, but we have not yet brought in that page, we now page it in.
3) Find a free-frame (by taking one from the free-frame list, for example).
4) Read the desired page into the newly allocated frame.
5) Modify the internal-table and the page-table to indicate that the page is now in memory.
6) Restart the instruction that was interrupted by the trap.

Figure 4.4 Steps in handling a page-fault

• Pure demand paging: Never bring pages into memory until required.
• Some programs may access several new pages of memory with each instruction, causing multiple
page-faults and poor performance.
• Programs tend to have locality of reference, so this results in reasonable performance from demand
paging.
• Hardware support:
1) Page-table
 Mark an entry invalid through a valid-invalid bit.
2) Secondary memory
 It holds pages that are not present in main-memory.
 It is usually a high-speed disk.
 It is known as the swap device (and the section of disk used for this purpose is known as
swap space).

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4.2.2 Performance
• Demand paging can significantly affect the performance of a computer-system.
• Let p be the probability of a page-fault (0≤p ≤1).
if p = 0, no page-faults.
if p = 1, every reference is a fault.
• effective access time(EAT)=[(1 - p) *memory access]+ [p *page-fault time]
• A page-fault causes the following events to occur:
1) Trap to the OS.
2) Save the user-registers and process-state.
3) Determine that the interrupt was a page-fault. '
4) Check that the page-reference was legal and determine the location of the page on the disk.
5) Issue a read from the disk to a free frame:
a. Wait in a queue for this device until the read request is serviced.
b. Wait for the device seek time.
c. Begin the transfer of the page to a free frame.
6) While waiting, allocate the CPU to some other user.
7) Receive an interrupt from the disk I/O subsystem (I/O completed).
8) Save the registers and process-state for the other user (if step 6 is executed).
9) Determine that the interrupt was from the disk.
10) Correct the page-table and other tables to show that the desired page is now in memory.
11) Wait for the CPU to be allocated to this process again.
12) Restore the user-registers, process-state, and new page-table, and then resume the
interrupted instruction.

4.3 Copy-on-Write
• This technique allows the parent and child processes initially to share the same pages.
• If either process writes to a shared-page, a copy of the shared-page is created.
• For example:
 Assume that the child process attempts to modify a page containing portions of the stack,
with the pages set to be copy-on-write.
 OS will then create a copy of this page, mapping it to the address space of the child process.
 Child process will then modify its copied page & not the page belonging to the parent process.

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4.4 Page Replacement

1) FIFO page replacement
2) Optimal page replacement
3) LRU page replacement (Least Recently Used)
4) LFU page replacement (Least Frequently Used)

4.4.1 Need for Page Replacement

• If we increase our degree of multiprogramming, we are over-allocating memory.
• While a user-process is executing, a page-fault occurs.
• The OS determines where the desired page is residing on the disk but then finds that there are no
free frames on the free-frame list (Figure 4.5).
• The OS then could:
→ Terminate the user-process (Not a good idea).
→ Swap out a process, freeing all its frames, and reducing the level of multiprogramming.
→ Perform page replacement.

Figure 4.5 Need for page replacement

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4.4.2 Basic Page Replacement

• Basic page replacement approach:
→ If no frame is free, we find one that is not currently being used and free it (Figure 4.6).
• Page replacement takes the following steps:
1) Find the location of the desired page on the disk.
2) Find a free frame:
¤ If there is a free frame, use it.
¤ If there is no free frame, use a page-replacement algorithm to select a victim-frame.
¤ Write the victim-frame to the disk; change the page and frame-tables accordingly.
3) Read the desired page into the newly freed frame; change the page and frame-tables.
4) Restart the user-process.

Figure 4.6 Page replacement

• Problem: If no frames are free, 2 page transfers (1 out & 1 in) are required. This situation
→ doubles the page-fault service-time and
→ increases the EAT accordingly.
Solution: Use a modify-bit (or dirty bit).
• Each page or frame has a modify-bit associated with the hardware.
• The modify-bit for a page is set by the hardware whenever any word is written into the page
(indicating that the page has been modified).
• Working:
1) When we select a page for replacement, we examine it‟s modify-bit.
2) If the modify-bit =1, the page has been modified. So, we must write the page to the disk.
3) If the modify-bit=0, the page has not been modified. So, we need not write the page to the
disk, it is already there.
• Advantage:
1) Can reduce the time required to service a page-fault.
• We must solve 2 major problems to implement demand paging:
1) Develop a Frame-allocation algorithm:
 If we have multiple processes in memory, we must decide how many frames to allocate to
each process.
2) Develop a Page-replacement algorithm:
 We must select the frames that are to be replaced.

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4.4.3 FIFO Page Replacement

• Each page is associated with the time when that page was brought into memory.
• When a page must be replaced, the oldest page is chosen.
• We use a FIFO queue to hold all pages in memory (Figure 4.7).
When a page must be replaced, we replace the page at the head of the queue
When a page is brought into memory, we insert it at the tail of the queue.
• Example: Consider the following references string with frames initially empty.

Figure 4.7 FIFO page-replacement algorithm

 The first three references(7, 0, 1) cause page-faults and are brought into these empty
frames.
 The next reference(2) replaces page 7, because page 7 was brought in first.
 Since 0 is the next reference and 0 is already in memory, we have no fault for this reference.
 The first reference to 3 results in replacement of page 0, since it is now first in line.
 This process continues till the end of string.
 There are fifteen faults altogether.
• Advantage:
1) Easy to understand & program.
• Disadvantages:
1) Performance is not always good (Figure 4.8).
2) A bad replacement choice increases the page-fault rate (Belady's anomaly).
• For some algorithms, the page-fault rate may increase as the number of allocated frames increases.
This is known as Belady's anomaly.
• Example: Consider the following reference string:
1, 2, 3, 4, 1, 2, 5, 1, 2, 3, 4, 5
For this example, the number of faults for four frames (ten) is greater than the number of faults
for three frames (nine)!

Figure 4.8 Page-fault curve for FIFO replacement on a reference string

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4.4.4 Optimal Page Replacement

• Working principle: Replace the page that will not be used for the longest period of time (Figure 4.9).
• This is used mainly to solve the problem of Belady‟s Anamoly.
• This has the lowest page-fault rate of all algorithms.
• Consider the following reference string:

Figure 4.9 Optimal page-replacement algorithm

 The first three references cause faults that fill the three empty frames.
 The reference to page 2 replaces page 7, because page 7 will not be used until reference 18.
 The page 0 will be used at 5, and page 1 at 14.
 With only nine page-faults, optimal replacement is much better than a FIFO algorithm, which
results in fifteen faults.
• Advantage:
1) Guarantees the lowest possible page-fault rate for a fixed number of frames.
• Disadvantage:
1) Difficult to implement, because it requires future knowledge of the reference string.

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4.4.5 LRU Page Replacement

• The key difference between FIFO and OPT:
→ FIFO uses the time when a page was brought into memory.
→ OPT uses the time when a page is to be used.
• Working principle: Replace the page that has not been used for the longest period of time.
• Each page is associated with the time of that page's last use (Figure 4.10).
• Example: Consider the following reference string:

Figure 4.10 LRU page-replacement algorithm

 The first five faults are the same as those for optimal replacement.
 When the reference to page 4 occurs, LRU sees that of the three frames, page 2 was used
least recently. Thus, the LRU replaces page 2.
 The LRU algorithm produces twelve faults.
• Two methods of implementing LRU:
1) Counters
 Each page-table entry is associated with a time-of-use field.
 A counter(or logical clock) is added to the CPU.
 The clock is incremented for every memory-reference.
 Whenever a reference to a page is made, the contents of the clock register are copied to the
time-of-use field in the page-table entry for that page.
 We replace the page with the smallest time value.
2) Stack
 Keep a stack of page-numbers (Figure 4.11).
 Whenever a page is referenced, the page is removed from the stack and put on the top.
 The most recently used page is always at the top of the stack.
The least recently used page is always at the bottom.
 Stack is best implement by a doubly linked-list.
 Advantage:
1) Does not suffer from Belady's anomaly.
 Disadvantage:
1) Few computer systems provide sufficient h/w support for true LRU page replacement.
 Both LRU & OPT are called stack algorithms.

Figure 4.11 Use of a stack to record the most recent page references

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4.4.6 LRU-Approximation Page Replacement

• Some systems provide a reference bit for each page.
• Initially, all bits are cleared(to 0) by the OS.
• As a user-process executes, the bit associated with each page referenced is set (to 1) by the
hardware.
• By examining the reference bits, we can determine
→ which pages have been used and
→ which have not been used.
• This information is the basis for many page-replacement algorithms that approximate LRU
replacement.

4.4.6.1 Additional-Reference-Bits Algorithm

• We can gain additional ordering information by recording the reference bits at regular intervals.
• A 8-bit byte is used for each page in a table in memory.
• At regular intervals, a timer-interrupt transfers control to the OS.
• The OS shifts the reference bit for each page into the high-order bit of its 8-bit byte.
• These 8-bit shift registers contain the history of page use, for the last eight time periods.
• Examples:
00000000 - This page has not been used in the last 8 time units (800 ms).
11111111 - Page has been used every time unit in the past 8 time units.
11000100 has been used more recently than 01110111.
• The page with the lowest number is the LRU page, and it can be replaced.
• If numbers are equal, FCFS is used

4.4.6.2 Second-Chance Algorithm

• The number of bits of history included in the shift register can be varied to make the updating as fast
as possible.
• In the extreme case, the number can be reduced to zero, leaving only the reference bit itself. This
algorithm is called the second-chance algorithm.
• Basic algorithm is a FIFO replacement algorithm.
• Procedure:
 When a page has been selected, we inspect its reference bit.
 If reference bit=0, we proceed to replace this page.
 If reference bit=1, we give the page a second chance & move on to select next FIFO page.
 When a page gets a second chance, its reference bit is cleared, and its arrival time is reset.

Figure 4.12 Second-chance (clock) page-replacement algorithm

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• A circular queue can be used to implement the second-chance algorithm (Figure 4.12).
 A pointer (that is, a hand on the clock) indicates which page is to be replaced next.
 When a frame is needed, the pointer advances until it finds a page with a 0 reference bit.
 As it advances, it clears the reference bits.
 Once a victim page is found, the page is replaced, and the new page is inserted in the circular
queue in that position.

4.4.6.3 Enhanced Second-Chance Algorithm

• We can enhance the second-chance algorithm by considering
1) Reference bit and
2) modify-bit.
• We have following 4 possible classes:
1) (0, 0) neither recently used nor modified -best page to replace.
2) (0, 1) not recently used hut modified-not quite as good, because the page will need to be
written out before replacement.
3) (1, 0) recently used but clean-probably will be used again soon.
4) (1, 1) recently used and modified -probably will be used again soon, and the page will be
need to be written out to disk before it can be replaced.
• Each page is in one of these four classes.
• When page replacement is called for, we examine the class to which that page belongs.
• We replace the first page encountered in the lowest nonempty class.

4.4.7 Counting-Based Page Replacement

1) LFU page-replacement algorithm
 Working principle: The page with the smallest count will be replaced.
 The reason for this selection is that an actively used page should have a large reference
count.
 Problem:
When a page is used heavily during initial phase of a process but then is never used again.
Since it was used heavily, it has a large count and remains in memory even though it is no
longer needed.
Solution:
Shift the counts right by 1 bit at regular intervals, forming an exponentially decaying
average usage count.
2) MFU (Most Frequently Used) page-replacement algorithm
 Working principle: The page with the smallest count was probably just brought in and has yet
to be used.

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4.5 Allocation of Frames

4.5.1 Minimum Number of Frames
• We must also allocate at least a minimum number of frames. One reason for this is performance.
• As the number of frames allocated to each process decreases, the page-fault rate increases, slowing
process execution.
• In addition, when a page-fault occurs before an executing instruction is complete, the instruction
must be restarted.
• The minimum number of frames is defined by the computer architecture.

4.5.2 Allocation Algorithms

1) Equal Allocation
 We split m frames among n processes is to give everyone an equal share, m/n frames. (For
ex: if there are 93 frames and five processes, each process will get 18 frames. The three
leftover frames can be used as a free-frame buffer pool).
2) Proportional Allocation
 We can allocate available memory to each process according to its size.
• In both 1 & 2, the allocation may vary according to the multiprogramming level.
• If the multiprogramming level is increased, each process will lose some frames to provide the
memory needed for the new process.
• Conversely, if the multiprogramming level decreases, the frames that were allocated to the departed
process can be spread over the remaining processes.

4.5.3 Global versus Local Allocation

Global Replacement Local Replacement
Allows a process to a replacement frame Each process selects from only its own set of
from the set of all frames. allocated frames.
A process may happen to select only frames Number of frames allocated to a process
allocated to other processes, thus increasing does not change.
the number of frames allocated to it.
Disadvantage: Disadvantage:
A process cannot control its own page-fault Might prevent a process by not making
rate. available to it other less used pages of
memory.
Advantage:
Results in greater system throughput.

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4.6 Thrashing
• If a process does not have "enough" pages, the page-fault rate is very high. This leads to:
→ low CPU utilization
→ operating system thinks that it needs to increase the degree of multiprogramming
→ another process added to the system.
• If the number of frames allocated to a low-priority process falls below the minimum number required,
it must be suspended.
• A process is thrashing if it is spending more time paging than executing.

4.6.1 Cause of Thrashing

• Thrashing results in severe performance-problems (Figure 4.13).
• The thrashing phenomenon:
 As processes keep faulting, they queue up for the paging device, so CPU utilization decreases
 The CPU scheduler sees the decreasing CPU utilization and increases the degree of
multiprogramming as a result.
 The new process causes even more page-faults and a longer queue!

Figure 4.13 Thrashing

• Methods to avoid thrashing:

1) Use Local Replacement
 If one process starts thrashing, it cannot
→ steal frames from another process and
→ cause the latter to thrash as well.
2) We must provide a process with as many frames as it needs. This approach defines the
locality model of process execution.
 Locality Model states that
As a process executes, it moves from locality to locality.
 A locality is a set of pages that are actively used together.
 A program may consist of several different localities, which may overlap.

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EXERCISE PROBLEMS

1) Consider following page reference string:

70120304230321201701
For a memory with 3 frames, how many page faults would occur for
(i) LRU algorithm
(ii) FIFO algorithm and
(iii) Optimal page replacement
algorithm? Which is the most efficient among
them?

Solution:

(i) LRU with 3 frames:

Frames 7 0 1 2 0 3 0 4 2 3 0 3 2 1 2 0 1 7 0 1
1 7 7 7 2 2 2 2 4 4 4 0 0 0 1 1 1 1 1 1 1
2 0 0 0 0 0 0 0 0 3 3 3 3 3 3 0 0 0 0 0
3 1 1 1 3 3 3 2 2 2 2 2 2 2 2 2 7 7 7
No. of Page faults √ √ √ √ √ √ √ √ √ √ √ √
No of page faults=12

(ii) FIFO with 3 frames:

Frames 7 0 1 2 0 3 0 4 2 3 0 3 2 1 2 0 1 7 0 1
1 7 0 1 2 2 3 0 4 2 3 0 0 0 1 2 2 2 7 0 1
2 7 0 1 1 2 3 0 4 2 3 3 3 0 1 1 1 2 7 0
3 7 0 0 1 2 3 0 4 2 2 2 3 0 0 0 1 2 7
No. of Page faults √ √ √ √ √ √ √ √ √ √ √ √ √ √ √
No of page faults=15

(iii) Optimal with 3 frames:

Frames 7 0 1 2 0 3 0 4 2 3 0 3 2 1 2 0 1 7 0 1
1 7 7 7 2 2 2 2 2 2 2 2 2 2 2 2 2 2 7 7 7
2 0 0 0 0 0 0 4 4 4 0 0 0 0 0 0 0 0 0 0
3 1 1 1 3 3 3 3 3 3 3 3 1 1 1 1 1 1 1
No. of Page faults √ √ √ √ √ √ √ √ √
No of page faults=9

Conclusion: The optimal page replacement algorithm is most efficient among three algorithms, as it
has lowest page faults i.e. 9.

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2) Consider the following page reference string

1, 2, 3, 4, 2, 1, 5, 6, 2, 1, 2, 3, 7, 6, 3, 2, 1, 2, 3, 6
How many page fault would occur for the following page replacement algorithms assuming 3 and 5
frames.
(i) LRU
(ii) Optimal

Solution:

LRU with 3 frames:

Frames 1 2 3 4 2 1 5 6 2 1 2 3 7 6 3 2 1 2 3 6
1 1 1 1 4 4 4 5 5 5 1 1 1 7 7 7 2 2 2 2 2
2 2 2 2 2 2 2 6 6 6 6 3 3 3 3 3 3 3 3 3
3 3 3 3 1 1 1 2 2 2 2 2 6 6 6 1 1 1 6
No. of Page faults √ √ √ √ √ √ √ √ √ √ √ √ √ √ √
No of page faults= 15

LRU with 5 frames:

Frames 1 2 3 4 2 1 5 6 2 1 2 3 7 6 3 2 1 2 3 6
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
3 3 3 3 3 3 6 6 6 6 6 6 6 6 6 6 6 6 6
4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 3
5 5 5 5 5 5 5 7 7 7 7 7 7 7 7
No. of Page faults √ √ √ √ √ √ √ √
No of page faults= 8

Optimal with 3 frames:

Frames 1 2 3 4 2 1 5 6 2 1 2 3 7 6 3 2 1 2 3 6
1 1 1 1 1 1 1 1 1 1 1 1 3 3 3 3 3 3 3 3 6
2 2 2 2 2 2 2 2 2 2 2 2 7 7 7 2 2 2 2 2
3 3 4 4 4 5 6 6 6 6 6 6 6 6 6 1 1 1 1
No. of Page faults √ √ √ √ √ √ √ √ √ √ √
No of page faults= 11

Optimal with 5 frames:

Frames 1 2 3 4 2 1 5 6 2 1 2 3 7 6 3 2 1 2 3 6
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
4 4 4 4 4 6 6 6 6 6 6 6 6 6 6 6 6 6
5 5 5 5 5 5 5 7 7 7 7 7 7 7 7
No. of Page faults √ √ √ √ √ √ √
No of page faults= 7

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3) For the following page reference, calculate the page faults that occur using FIFO and LRU for 3 and 4
page frames respectively
5, 4, 3, 2, 1, 4, 3, 5, 4, 3, 2, 1, 5.
Solution:

(i) LRU with 3 frames:

Frames 5 4 3 2 1 4 3 5 4 3 2 1 5
1 5 5 5 2 2 2 3 3 3 3 3 3 5
2 4 4 4 1 1 1 5 5 5 2 2 2
3 3 3 3 4 4 4 4 4 4 1 1
No. of Page faults √ √ √ √ √ √ √ √ √ √ √
No of page faults=11

(ii) LRU with 4 frames:

Frames 5 4 3 2 1 4 3 5 4 3 2 1 5
1 5 5 5 5 1 1 1 1 1 1 2 2 2
2 4 4 4 4 4 4 4 4 4 4 4 5
3 3 3 3 3 3 3 3 3 3 3 3
4 2 2 2 2 5 5 5 5 1 1
No. of Page faults √ √ √ √ √ √ √ √ √
No of page faults=9

(iii) LRU with 4 frames::

Frames 5 4 3 2 1 4 3 5 4 3 2 1 5
1 5 4 3 2 1 4 3 5 5 5 2 1 1
2 5 4 3 2 1 4 3 3 3 5 2 2
3 5 4 3 2 1 4 4 4 3 5 5
No. of Page faults √ √ √ √ √ √ √ √ √ √
No of page faults=10

(iv) FIFO with 4 frames:

Frames 5 4 3 2 1 4 3 5 4 3 2 1 5
1 5 4 3 2 1 1 1 5 4 3 2 1 5
2 5 4 3 2 2 2 1 5 4 3 2 1
3 5 4 3 3 3 2 1 5 4 3 2
4 5 4 4 4 3 2 1 5 4 3
No. of Page faults √ √ √ √ √ √ √ √ √ √ √
No of page faults=11

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4) What is Belady's anomaly? Explain with an example.

Solution:
Belady's Anomaly:
“On increasing the number of page frames, the no. of page faults do not necessarily decrease,
they may also increase”.
• Example: Consider the following reference string when number of frame used is 3 and 4:
1, 2, 3, 4, 1, 2, 5, 1, 2, 3, 4, 5
(i) FIFO with 3 frames:
Frames 1 2 3 4 1 2 5 1 2 3 4 5
1 1 2 3 4 1 2 5 5 5 3 4 4
2 1 2 3 4 1 2 2 2 5 3 3
3 1 2 3 4 1 1 1 2 5 5
No. of Page faults √ √ √ √ √ √ √ √ √
No. of page faults=9

(ii) FIFO with 4 frames:

Frames 1 2 3 4 1 2 5 1 2 3 4 5
1 1 2 3 4 4 4 5 1 2 3 4 5
2 1 2 3 3 3 4 5 1 2 3 4
3 1 2 2 2 3 4 5 1 2 3
4 1 1 1 2 3 4 5 1 2
No. of Page faults √ √ √ √ √ √ √ √ √ √
No. of page faults=10

Conclusion: With 3 frames, No. of page faults=9.

With 4 frames, No. of page faults=10.
Thus, Belady's anomaly has occurred, when no. of frames are increased from 3 to 4.

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