Computer Architecture

Ngo Lam Trung, Pham Ngoc Hung, Hoang Van Hiep

Department of Computer Engineering
School of Information and Communication Technology (SoICT)
Hanoi University of Science and Technology
E-mail: [trungnl, hungpn, hiephv]@soict.hust.edu.vn

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 Chapter 3: Instruction Set Architecture
(Language of the Computer)

[with materials from COD, RISC-V 2nd Edition, Patterson & Hennessy 2021,
M.J. Irwin’s presentation, PSU 2008,
The RISC-V Instruction Set Manual, Volume I, ver. 2.2]
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 Content
❑ Introduction
❑ RISC-V Instruction Set Architecture
l Operands
l Instruction set (basic RV32I variant)
l RISC-V instruction formats
l Other RISC-V instructions

❑ Basic programming structures

l Branch and loop
l Procedure call
l Array and string

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 What is RISC-V and its advantages (over ARM, x86)?
❑ Developed at UC Berkeley as open ISA (2010).
❑ Typical of many modern ISAs, which have a large share
of embedded market.
l RISC CPUs: Pioneers of Modern Computer Architecture
Receive ACM A.M. Turing Award

❑ Now managed by the RISC-V Foundation/RISC-V

International (https://riscv.org/, since 2015).

❑ “RISC-V combines a modular technical approach with an open,

royalty-free ISA — meaning that anyone, anywhere can benefit
from the IP contributed and produced by RISC-V.” - RISC-V
International.

❑ “RISC-V does not take a political position on behalf of any

geography.” - RISC-V International.

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 Computer language: hardware operation
❑ Want to command the computer?
➔ You need to speak its language!!!

❑ Example: RISC-V assembly instruction

add a, b, c #a  b + c
❑ Operation performed
add b and c,
then store result into a

add a, b, c #a  b + c

operation operands comments

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 Hardware operation
❑ What does the following code do?
add t0, g, h # t0 = g + h
add t1, i, j # t1 = i + j
sub f, t0, t1 # f = t0 - t1

❑ Equivalent C code
f = (g + h) – (i + j)

➔ Why not making 4- or 5-input instructions?

Instruction format significantly influences
hardware design.
➔ DP1: Simplicity favors regularity!
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 Operands
❑ Object of operation
l Source operand: provides input data
l Destination operand: stores the result of operation

❑ RISC-V operands
l Registers
l Memory
l Constant/Immediate

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 Data types in RISC-V

Byte =Byte
8 bits

Halfword= 2 bytes
Halfword

Word =Word
4 bytes

Doubleword = 8 bytes
Doubleword

RV32 registers hold 32-bit (4-byte) words. Other common

data sizes include byte, halfword, and doubleword.

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 Register operand: RISC-V Register File
❑ Special memory inside CPU, called register file
❑ 32 slots, each slot is called a register (RV32I)
❑ Each register holds 32 bits of data
❑ Each register has a unique 5-bit address

Register File
32 bits
5 32 src1
Read ports src1 addr
5 data
addresses src2 addr 32 Read ports
5 locations
dst addr data
Write ports
32 src2
address and 32
write data data
data

write control
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 RISC-V Register Convention
❑ RISC-V: load/store machine
❑ Data processing done on registers inside CPU

RISC-V integer registers

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 Register operand: RISC-V Register File
❑ Register file: “work place” right inside CPU.
❑ Larger register file should be better, more flexibility for
CPU operation.
❑ Moore’s law: doubled number of transistor every 18 mo.
❑ Why only 32 registers, not more?

➔ DP2: Smaller is faster!

Effective use of register file is critical!

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 Memory operand
❑ Memory operands are stored in main memory
l Large size
l Outsize CPU →Slower than register file (100 to 500 times)

❑ High level language programs use memory operands

l Variables
l Array and string
l Composite data structures

❑ Operations with memory operands

l Units of byte/half word/word/double word
l Load data from memory to register
l Store data from register to memory

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 RISC-V memory organization

Byte 0x0f
❑ Byte addressable
address 0x0e
Word 3 ❑ Words are accessed
(32 bit) 0x0d
0x0c via byte address
0x0b
❑ Only accessible via
0x0a load/store instructions
Word 2
0x09
0x08
0x07
0x06
Word 1 Data alignment
0x05
0x04 word address = 4 * word
0x03
number
0x02
Word 0 RISC-V does not require
0x01
data alignment, but it is
0x00
strongly recommended.
➔ handled by compiler

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 RISC-V memory organization

Byte 0x0f
Is this optimized to
address 0x0e
Word 3 declare a struct in C like
(32 bit) 0x0d
this?
0x0c
0x0b Struct data
0x0a {
Word 2
0x09 char x;
0x08 short y;
0x07 int z;
0x06 }
Word 1
0x05
0x04 Aligned Data
0x03 • Primitive data type requires K
0x02 bytes
Word 0 • Address must be multiple of K
0x01
0x00

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 Example: z = x + y
❑ x, y, z are allocated in mem, but must transfer to reg before adding
❑ Note: currently focus on instruction set first, assembly programming
will be presented later

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 Byte Order

❑ Big Endian: word address points to MSB

IBM 360/370, Motorola 68k, Sparc, HP PA

❑ Little Endian: word address points to LSB

Intel 80x86, DEC, MIPS, RISC-V

little endian order

3 2 1 0
MSB LSB
(most significant byte) (least significant byte)
0 1 2 3
big endian order

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 Example
❑ Consider a word in RISC-V memory consists of 4 byte
with hexa value as below
❑ What is the word’s value?

address value

X 68
X+1 1B
X+2 5D
X+3 FA

❑ RISC-V is little-endian: address of LSB is X

➔ word’s value: FA5D1B68

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 Immediate operand
❑ Immediate value specified by a constant number
❑ Examples:
l Assignment: int x = 2024;
l Const in expression: x = y + 10;
l Branching: if.. else.., goto,…

❑ Does not need to be stored in register file or memory

l Value stored right in instruction → faster
l Fixed value specified at design time
l Cannot change value at run time

❑ What is the most-used constant?

l 0 value is stored in the special register: zero (x0)
l Make common cases fast!

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 Instruction set
❑ Instruction: binary string represent opcode + operands
❑ RISC-V (RV32 variant) base instructions are 32 bits long.
l Must be word-aligned in memory.

❑ 6 instruction formats

➔ Why not only one format? Or 20 formats?

➔ DP3: Good design demands good compromises!
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 Instruction categories
❑ Arithmetic: addition, subtraction,…
❑ Data transfer: transfer data between registers, memory,
and immediate
❑ Logical and bitwise: and, or, xor, shift left/right…
❑ Branch: conditional and unconditional

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 Overview of RISC-V instruction set

Fig. 2.1

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 Overview of RISC-V instruction set

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 RISC-V Instruction set: Arithmetic operations
❑ RISC-V arithmetic statement
add rd, rs1, rs2 #rd  rs1 + rs2
sub rd, rs1, rs2 #rd  rs1 – rs2
addi rd, rs1, imm #rd  rs1 + imm

• rs1 5-bits register file address of the 1st source operand

• rs2 5-bits register file address of the 2nd source operand
• rd 5-bits register file address of the result’s destination

Why there is no subi instruction?

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 Example
❑ Currently s1 = 6
❑ What is value of s1 after executing the following
instruction
addi s2, s1, 3
addi s1, s1, -2
sub s1, s2, s1

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 RISC-V Instruction set: Logical operations
❑ Bitwise operations

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 RISC-V Instruction set: Logical operations
❑ Basic logic operations
and rd, rs1, rs2 #rd  rs & rs2
andi rd, rs1, imm #rd  rs & imm
or rd, rs1, rs2 #rd  rs | rs2
ori rd, rs1, imm #rd  rs | imm
xor rd, rs1, rs2 #rd  rs ^ rs2
xor rd, rs1, imm #rd  rs ^ imm
❑ Example s1 = 8 = 0000 1000, s2 = 14 = 0000 1110
and s3, s1, s2
or s4, s1, s2
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 RISC-V Instruction set: Shift operations
❑ Logical shift and arithmetic shift: move all the bits left or
right
sll rd, rs1, rs2 #rd  rs1 << rs2
srl rd, rs1, rs2 #rd  rs1 >> rs2
sra rd, rs1, rs2 #rd  rs1 >> rs2
(keep sign bit)
slli rd, rs1, imm #rd  rs1 << imm
srli rd, rs1, imm #rd  rs1 >> imm
srai rd, rs1, imm #rd  rs1 >> imm
(keep sign bit)

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 RISC-V Instruction set: Memory access instructions

❑ RISC-V has two basic data transfer instructions for

accessing memory
lw rd, imm(rs1) #load word from memory
sw rs2, imm(rs1) #store word to memory
❑ The data is loaded into (lw) or stored from (sw) a register
in the register file

❑ The memory address is formed by adding the contents of

the base address register to the offset value
❑ Offset can be negative
❑ Data alignment is strongly recommended
❑ Why not the instruction is just like this: lw rd, imm?
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 RISC-V Instruction set: Load Instruction
❑ Load/Store Instruction Format:
lw t0, 24(s3) #t0 mem at 24+s3

Which memory word will be loaded to t0?

Memory
2410 + $s3 = 0xf f f f f f f f

. 0001 1000 (24) $t0 0x120040ac

+ . 1001 0100 (94) 24
. 1010 1100 (ac) $s3 0x12004094
= 0x1200 40ac
0x0000000c
0x00000008
0x00000004
0x00000000
data word address (hex)
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 RISC-V Instruction set: Load Instruction
❑ Given the integer array A stored in memory, with base
address stored in x13.
int A[100]; //x13 holds address of A[0]
❑ What is equivalent C code of this?
lw x10, 12(x13)
addi x12, x10, 10
sw x12, 40(x13)

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 RISC-V control flow instructions
❑ RISC-V conditional branch instructions:
bne rs1, rs2, Dest #go to Dest if rs1rs2
beq rs1, rs2, Dest #go to Dest if rs1=rs2
bge rs1, rs2, Dest #go to Dest if rs1>=rs2
blt rs1, rs2, Dest #go to Dest if rs1<rs2
bgeu/bltu: unsigned comparison

Ex: if (i==j)
h = i + j;

bne s0, s1, Exit

add s3, s0, s1
Exit : ...

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 Example

start:
addi s0, zero, 2 #load value for s0
addi s1, zero, 2
addi s3, zero, 0
beq s0, s1, Exit
add s3, s2, s1
Exit: add s2, s3, s1
.end start

What is final value of s2?

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 Unconditional branch
❑ Unconditional branch instruction or jump instruction:

j Dest #go to Dest

❑ Note: this is a pseudo-instruction implemented with the

jal instruction, and auipc instruction if necessary

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 Comparison instruction
❑ Set flag based on condition: slt
❑ Set on less than instruction:
slt $t0, $s0, $s1 # if $s0 < $s1 then
# $t0 = 1 else
# $t0 = 0
❑ Alternate versions of slt
slti $t0, $s0, 25 # if $s0 < 25 then $t0=1 ...
sltu $t0, $s0, $s1 # if $s0 < $s1 then $t0=1 ...
sltiu $t0, $s0, 25 # if $s0 < 25 then $t0=1 ...
❑ Can be combined with bne/beq for conditional branches

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 Example
❑ Write assembly code to do the following
if (i<5)
X = 3;
else
X = 10;

Solution
slti t0,s1,5 # i<5? (inverse condition)
beq t0,zero,else # if i>=5 goto else part
addi t1,zero,3 # X = 3
j endif # skip the else part
else: addi t1,zero,10 # X = 10
endif:...

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 Representation of RISC-V instruction

❑ All RISC-V instructions are 32 bits wide

The RISC-V Instruction Set Manual, Volume I: User-Level ISA

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 R-format instruction: all operands are registers
❑ All fields are encoded by mnemonic names

❑ Examples

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 Example of R-format instruction

add s1, s4, s5

add x9, x20, x21

0 21 20 0 9 51

0000000 10101 10100 000 01001 0110011

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 I-format instruction: 2 registers + 1 immediate
❑ Combines the funct7 and rs2 for 12-bit immediate

❑ Examples

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 Example
❑ Find machine codes of the following instructions
lw t0, 0(s1) # initialize maximum to A[0]
addi t1, zero, 0 # initialize index i to 0
addi t1, t1, 1 # increment index i by 1

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 S-format instruction: 2 registers + 1 immediate
❑ Combines the funct7 and rd for 12-bit immediate
❑ Used for the store instructions, which does not require rd

❑ Examples

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 B-format instruction: 2 registers + 1 immediate
❑ Combines the funct7 and rd for 13-bit immediate
l Lsb = 0 (imm[12:1] for half-word instruction address, more on
this later).
l Keep the same bit position as S-format
l Msb always in bit 31 of instruction word (simplified sign-
extension, also more on this later)

❑ As a result: position of 13 bits immediate are mixed

❑ Used for conditional jump instructions

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 U- and J-format instruction: 1 register + 1 immediate
❑ Combines the funct7, funct3, rs1 and rs2 for 20-bit
immediate

❑ U-format: for load/add 20 bit upper-immediate to register

lui rd, upimm # rd  {upimm,000}

auipc rd, upimm # rd  PC + {upimm,000}

❑ J-format: for jump and link

jal rd, label # PC  PC+addr, rd  PC+4
addr = SignExt{imm,0}

❑ Pseudo-instruction j label ➔ jal x0, label

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 Working with wide immediates and addresses
❑ Many operations need 32-bit immediates
l Loading 32-bit immediates to registers
l Loading addresses to registers

❑ However, instructions are only 32 bit-long

l Not sufficient to store 32-bit immediates in one instruction
l →combine 2 instructions to support wide immediates

❑ Example: load the value 0x3D0100 into s0

lui s0, 0x003D0 #s0  0x003D0000
addi s0, s0, 0x0100 #s0  0x003D0100
❑ Pseudo-instructions: combination of real instructions, for
convenience
l li, la
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 Working with wide immediates and addresses
❑ Special case: long jump
❑ Conditional branches: blt, bne,..
l B-format, with 12 bit immediates
l Limited to 4 KB → limit branching distance
l Solution: change to jal
beq x10, x0, L1 #limit 4KB bne x10, x0, L2
jal x0, L1 #limit 1MB
L2:
❑ Unconditional jump (jal)
l Distance is limited to 1MB
l Solution: use jalr, combine with auipc if necessary

jalr rd, rs1, imm # PC = rs1 + SignExt(imm), rd = PC+4

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 Exercise
❑ How branch instruction is executed?
❑ ➔ PC-relative addressing mode
slti t0, s1, 5

bne t0, zero, else How can CPU jump from here
to the “else” label?
addi t1, zero, 3

j endif

else: addi t1, zero, 10

endif:...

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 Example

The simple switch Solution

switch(test) { beq s1,t0,case_0
case 0:
beq s1,t1,case_1
beq s1,t2,case_2
a=a+1; break;
j default
case 1: case_0:
a=a-1; break; addi s2,s2,1 #a=a+1
case 2: j continue
b=2*b; break; case_1:
default:
sub s2,s2,t1 #a=a-1
j continue
}
case_2:
Assuming that: test,a,b are add s3,s3,s3 #b=2*b
stored in $s1,$s2,$s3 j continue
default:
continue:

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 Example
❑ Write assembly code correspond to the following C code
for (i = 0; i < n; i++)
sum = sum + A[i];
loop:
addi s1,s1,1 #i=i+step
add t1,s1,s1 #t1=2*s1
add t1,t1,t1 #t1=4*s1
add t1,t1,a0 #t1 <- address of A[i]
lw t0,0(t1) #load value of A[i] in t0
add s0,s0,t0 #sum = sum+A[i]
bne s1,a1,loop #if i != n, goto loop
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 Example

The simple while loop: while (A[i]==k) i=i+1;

Assuming that: i, k, A are stored in x22,x24,x25

Solution

Loop:
slli x10, x22, 2 #i*4
add x10, x10, x25 #A[i] address
lw x9, 0(x10) #A[i] value
bne x9, x24, Exit #break if != k
addi x22, x22, 1 #next element
beq x0, x0, Loop
Exit: …

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 Procedures

❑ Stack structure P(…) {

•
❑ Passing control •
y = Q(x);
l To beginning of procedure code
print(y)
l Back to return point •
}
❑ Passing data
l Procedure arguments
l Return value int Q(int i)
{
❑ Register saving conventions int t = 3*i;
int v[10];
❑ Memory management •
•
l Allocate during procedure execution return v[t];
l Deallocate upon return }

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 Stack structure
❑ A region of memory operating on a Last In First Out
(LIFO) principle
❑ The bottom of stack is at the highest location
❑ sp: point to the top of the stack

Lo
var
Sa
reg

$sp c
b Frame for
a current
.. procedure
.
$fp

Before calling
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 Stack structure

❑ To push data into stack

l addi sp, sp, -4
l sw t0, 0(sp)

❑ To pop data from the stack

l lw t0, 0(sp)
l addi sp, sp, 4
l Note that: the data is still there in the stack, but we
are not going to work with it anymore.

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 Passing control flow
❑ Procedure call: using RISC-V procedure call instruction
jal rd, ProcAddress #jump and link

l Saves the return address (PC+4) in destination register rd

(usually in ra or x1)
l Jump to the ProcAddress

❑ Return address:
l Address of the next instruction right after call

❑ Procedure return: procedure return with

jalr x0, 0(x1)

l Update the value of PC = ra

l Jump to the address of PC (the next instruction right after
procedure call)
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 Passing control

main
Prepare
to call
PC jal proc
Prepare
to continue proc
Save, etc.

Restore
jrx0, $ra
jalr 0(x1)

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 Passing control
❑ Demonstrate on the Rars simulator

❑ Take care the value of the pc and ra register!

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 Procedure call and nested procedure call

Question: how can the CPU resume the main program execution?

Example of nested procedure call

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 Passing data
❑ Use registers
l Input arguments:
- a0-a7
- 8 parameters (arguments) maximum
l Return value:
- a0

❑ What if we want to pass more than 8 arguments

→ use the stack:
l Caller pushes arguments into stack before calling the
callee
l Callee get arguments from the stack
l (Optional) Callee saves the return value to the stack
l Question: who clean the stack, caller or callee?
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 Register saving convention

❑ Registers to be saved by the caller

l ra, t0-t6, a0-a7

❑ Registers must be saved by the callee

l sp, s0-s11

❑ Note: save the registers just in case you need to

modify them.
❑ Question: where to save the above registers?

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 Memory management

❑ Question: where to locate the P(…) {

•
local variables: t and v? •
l Use registers: # of registers is y = Q(x);
limited print(y)
•
l Use Stack }

int Q(int i)
{
int t = 3*i;
int v[10];
•
•
return v[t];
}

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 Carnegie Mellon

Stack Frame
❑ Current Stack Frame (“Top” to
Bottom)
l “Argument build:”
Parameters for function about to call
l Local variables Caller
If can’t keep in registers Frame
Arguments
l Saved register context 9+
l Old frame pointer (optional) Frame pointer Return Addr
fp Old fp
(Optional)
Saved
❑ Caller Stack Frame Registers
+
l Return address Local
- Pushed by jal instruction Variables
l Arguments for this call
Argument
Stack pointer Build
sp (Optional)
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 Six Steps in the Execution of a Procedure
1. Main routine (caller) places parameters in a place
where the procedure (callee) can access them
l a0 – a7 (x10 – x17): 8 argument registers

2. Caller transfers control to the callee (jal)

3. Callee acquires the storage resources needed
4. Callee performs the desired task
5. Callee places the result value in a place where the
caller can access it
l a0 – a1: two value registers for result values

6. Callee returns control to the caller (jalr)

l ra (x1): one return address register to return to caller

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 Procedure that does not call another proc.
❑ C code:

int leaf_example (int g, h, i, j)

{
int f;
f = (g + h) - (i + j);
return f;
}
l g, h, i, j stored in a0, a1, a2, a3
l f in s0 (need to be saved)
l t0 and t1 used for temporary data
l Preserve all s0, t0, t1 for safety
l Result in a0

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 Sample code

leaf_example:
addi sp, sp, -12 # room for 3 items
sw t1, 8(sp) # save t1
sw t0, 4(sp) # save t0
sw s0, 0(sp) # save s0
add t0, a0, a1 # t0 = g+h
add t1, a2, a3 # t1 = i+j
sub s0, t0, t1 # s0 = (g+h)-(i+j)
add a0, s0, zero # return value in a0
lw s0, 0(sp) # restore s0
lw t0, 4(sp) # restore t0
lw t1, 8(sp) # restore t1
addi sp, sp, 12 # deallocate
jalr zero, 0(ra) # return to caller

Exercise: write code to utilize the procedure above

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 Stack usage

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 Procedure with nested proc.
❑ C code:

int fact (int n)

{
if (n < 1) return (1);
else return n * fact(n - 1);
}
l n in $a0
l Result in $a0

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 Sample code
fact:
addi sp, sp, -8 #2 items in stack
sw ra, 4(sp) #save return address
sw a0, 0(sp) #and current n
addi t0, a0, -1 #n-1 > 0
bge t0, zero, L1 #continue
addi a0, zero, 1 #the base case, return 1
addi sp, sp, 8 #deallocate 2 words
jr ra #and return
L1: addi a0, a0, -1 #otherwise reduce n
jal fact #then call fact again
add a1, a0, zero #restore n
lw a0, 0(sp) #and return address
lw ra, 4(sp) #shrink stack
addi sp, sp, 8 #value for normal case
mul a0, a0, a1 #multiply with n
jalr x0, 0(ra) #and return
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 RISC-V memory configuration
❑ Program text: stores machine code of program, declared
with .text
❑ Static data: data segment, declared with .data
❑ Heap: for dynamic allocation
❑ Stack: for local variable and dynamic allocation (LIFO)

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 Accessing characters and string
❑ String is accessed as array of characters
❑ Accessing 1-byte characters
lb rd, imm(rs1) #load byte with sign-extension
lbu rd, imm(rs1) #load byte with zero-extension
sb rs2, 0(rs1) #store LSB to memory

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 Accessing characters and string
❑ Accessing 2-byte characters
lh rd, imm(rs1) #load half with sign-extension
lhu rd, imm(rs1) #load half with zero-extension
sh rs2, 0(rs1) #store 2 LSB to memory
❑ Example: string copy

void strcpy (char x[], char y[])

{
int i = 0;
while ((x[i] = y[i]) != ‘\0’)
i += 1;
}
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 Accessing characters and string

#x and y are in a0 and a1, i in s0

strcpy:
addi sp,sp,–4 # adjust stack for 1 more item
sw s0, 0(sp) # save s0
add s0, zero, zero # i = 0
L1: add t1, s0, a1 # address of y[i] in t1
lbu t2, 0(t1) # t2 = y[i]
add t3, s0, a0 # address of x[i] in t3
sb t2, 0(t3) # x[i] = y[i]
beq t2, zero,L2 # if y[i] == 0, go to L2
addi s0, s0, 1 # i = i + 1
beq x0, x0, L1 # go to L1
L2: lw s0, 0(sp) # y[i] == 0: end of string.
# Restore old $s0
addi sp,sp,4 # pop 1 word off stack
jalr ra # return

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 Interchange sort function
void sort (int v[], int n)
{
int i, j;
for (i = 0; i < n; i += 1)
{
for (j = i – 1; j >= 0 && v[j] > v[j + 1]; j-=1)
{
swap(v,j);
}
}
}
void swap(int v[], int k)
{
int temp;
temp = v[k];
v[k] = v[k+1];
v[k+1] = temp;
}
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 RISC-V Instruction Set Extensions
❑ The RV31I Instruction Set (that we have learnt so far)
l Instruction word: 32 bits
l Only work on integers
l Supports arithmetic, logic and shift, data transfer, branches

❑ How about:
l Other instruction word length?
l Data other than integers?
l Additional operations: multiplication, division…?

❑ Instruction Set Extensions

l Additional operations and data types
l Additional formats and customed formats
l → RISC-V scalable ISA

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 RISC-V Standard Extensions
❑ 32-bit instruction extensions
l “M”: Integer Multiplication and Division Instructions
l “A”: Atomic (Memory) Instructions
l “F”: Single-Precision Floating-Point Instructions
l “D”: Double-Precision Floating-Point Instructions

❑ 16-bit: “C”: Compressed Instructions

RISC-V instruction length encoding

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 RV32M: Integer Multiplication and Division Extension
❑ Support integer multiplication, division (div and rem)
operations.
❑ All are R-format.

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 RV32A: Atomic Extension
❑ Support synchronized “atomic” memory access.
l Load + data op + Store become atomic.
l Similar to semaphore/mutex in multithread software.
l Basically R-format, with aq (acquire) and rl (release) bits.

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 RV32F / D Floating-Point Extensions
❑ Support floating point operations.
l Additional floating point register file for new data type.
l Additional instructions to work with the new register file.
l Additional load/store instructions.

❑ Data representation and computation are compliant with

the IEEE 754-2008 standard (chapter 4).
l “F”: 32-bit single precision floating point numbers (float in C).
l “D”: 64-bit double precision floating point numbers (double in C).

RISC-V floating point register file

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 RV32F / D Floating-Point Extensions
❑ Single precisision instructions
❑ .s for single, .d for double

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 RVC Compressed Extension
❑ 16-bit length instructions
l Double code density compared to 32-bit instructions.
l Limited to most frequently-used instructions/operands.
l Overall 25% - 30% code-size reduction.

RVC Instruction Formats

RVC Registers for CIW, CL, CS, CB instructions

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 RVC Compressed Instructions

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 Further reading
❑ MIPS instruction set
❑ ARM instruction set
❑ x86 instruction set

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 The end

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