Novel BCD Adders and Their Reversible Logic

Implementation for IEEE 754r Format

Himanshu Thapliyal, Saurabh Kotiyal and M.B Srinivas

Center for VLSI and Embedded System Technologies,
International Institute of Information Technology, Hyderabad-500019, India
*Department of Computer Engineering, SIT, Kukas, Jaipur, India
([email protected], [email protected], [email protected])

Abstract Since, the decimal arithmetic is getting significant

attention; specifications for it have recently been added
IEEE 754r is the ongoing revision to the IEEE 754 to the draft revision of the IEEE 754 standard for
floating point standard and a major enhancement to Floating-Point Arithmetic. IEEE 754r is an ongoing
the standard is the addition of decimal format. This revision to the IEEE 754 floating point standard [2,3].
paper proposes two novel BCD adders called carry Some of the major enhancements so far incorporated
skip and carry look-ahead BCD adders respectively. are the addition of 128-bit and decimal formats.
Furthermore, in the recent years, reversible logic has Furthermore, three new decimal formats are described,
emerged as a promising technology having its matching the lengths of the binary formats. These
applications in low power CMOS, quantum computing, have led to the decimal formats with 7, 16, and 34-
nanotechnology, and optical computing. It is not digit significands, which may be normalized or
possible to realize quantum computing without unnormalized. In the proposed IEEE 754r format, for
reversible logic. Thus, this paper also paper provides maximum range and precision, the formats merge part
the reversible logic implementation of the conventional of the exponent and significand into a combination
BCD adder as the well as the proposed Carry Skip field, and compress the remainder of the significand
BCD adder using a recently proposed TSG gate. using densely packed decimal encoding [2,3]. It is
Furthermore, a new reversible gate called TS-3 is also anticipated that, once the IEEE 754r Standard is finally
being proposed and it has been shown that the approved, hardware support for decimal floating-
proposed reversible logic implementation of the BCD point arithmetic on the processors will come into
Adders is much better compared to recently proposed existence for financial, commercial, and Internet-based
one, in terms of number of reversible gates used and applications. Still, the major consideration while
garbage outputs produced. The reversible BCD implementing BCD arithmetic will be to enhance its
circuits designed and proposed here form the basis of speed as much as possible.
the decimal ALU of a primitive quantum CPU. Furthermore, researchers like Landauer have shown
that for irreversible logic computations, each bit of
1. Introduction information lost, generates kTlog2 joules of heat
energy, where k is Boltzmann’s constant and T the
Nowadays, the decimal arithmetic is receiving absolute temperature at which computation is
significant attention as the financial, commercial, and performed [4]. Bennett showed that kTln2 energy
Internet-based applications cannot tolerate errors dissipation would not occur, if a computation is carried
generated by conversion between decimal and binary out in a reversible way [5], since the amount of energy
formats. Furthermore, a number of decimal numbers, dissipated in a system bears a direct relationship to the
such as 0.110, cannot be exactly represented in binary, number of bits erased during computation. Reversible
thus, these applications often store data in decimal circuits are those circuits that do not lose information
format and process data using decimal arithmetic and reversible computation in a system can be
software [1]. The advantage of decimal arithmetic in performed only when the system comprises of
eliminating conversion errors also comes with a reversible gates. These circuits can generate unique
drawback; it is typically 100 to 1,000 times slower output vector from each input vector, and vice versa,
than binary arithmetic implemented in hardware. that is, there is a one-to-one mapping between input

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 and output vectors. Classical logic gates are being shown the proposed reversible implementation
irreversible since input vector states cannot be of the BCD adders is better than reversible BCD adder
uniquely reconstructed from the output vector states. proposed in [11]. One new reversible gate, TS-3, is
There is a number of existing reversible gates such as also proposed in this paper. Thus, an attempt has been
Fredkin gate [6,7,8], Toffoli Gate (TG) [6, 7] and the tried to design faster BCD adders as well as to provide
New Gate (NG) [8]. As the Moore’s law continues to the platform for building decimal ALU of a Quantum
hold, the processing power doubles every 18 months. CPU.
The current irreversible technologies will dissipate a
lot of heat and can reduce the life of the circuit. The
reversible logic operations do not erase (lose) 2. Conventional BCD Adder
information and dissipate very less heat. Thus,
reversible logic is likely to be in demand in high speed A BCD adder is a circuit that adds two BCD digits in
power aware circuits. Reversible circuits are of high parallel and produces a sum digit also in BCD. Fig. 1
interest in low-power CMOS design, optical shows the conventional BCD adder. A BCD adder
computing, nanotechnology and quantum computing. must also include the correction logic in its internal
construction. The two decimal digits, together with the
The most prominent application of reversible logic lies input carry, are first added in the top 4-bit binary adder
in quantum computers [10]. A quantum computer will to produce the binary sum. When the output carry is
be viewed as a quantum network (or a family of equal to zero, nothing is added to the binary sum.
quantum networks) composed of quantum logic gates; When it is equal to one, binary 0110 is added to the
each gate performing an elementary unitary operation binary sum using another 4-bit binary adder (bottom
on one, two or more two–state quantum systems called binary adder). The output carry generated from the
qubits. Each qubit represents an elementary unit of bottom binary adder is ignored, since it supplies
information; corresponding to the classical bit values 0 information already available at the output carry
and 1. Any unitary operation is reversible and hence terminal.
quantum networks effecting elementary arithmetic
operations such as addition, multiplication and
exponentiation cannot be directly deduced from their
classical Boolean counterparts (classical logic gates
such as AND or OR are clearly irreversible).Thus,
quantum arithmetic must be built from reversible
logical components.
One of the major constraints in reversible logic is to
minimize the reversible gate used and garbage output
produced. Firstly, this paper introduces, two novel
BCD adder architectures termed CLA BCD (Carry
look-ahead BCD) and CS BCD (Carry Skip BCD)
adders respectively. The proposed BCD architectures
are designed especially, to make them suitable for
reversible logic synthesis. The first proposed CLA Figure 1. Conventional BCD Adder
BCD adder is an improvement over the adder proposed
in [13] and is modified to make it suitable for the 3. Proposed Carry Look Ahead Adder
reversible logic implementation. The second carry
skip BCD adder is proposed to cater the need of carry A Carry Look Ahead BCD Adder is proposed which
skip adder in decimal arithmetic. Recently, a reversible is modification over the architecture proposed in [13]
conventional BCD adder was proposed in [11] using and is especially improved for making it suitable for
conventional reversible gates. Furthermore, this paper CMOS as well as reversible logic implementation. In
introduces a novel implementation of the BCD adders the proposed CLA BCD adder, OR gates used in the
using a recently proposed TSG gate [12]. The TSG equations proposed in [13] are selectively chosen and
gate has the advantage that it can work singly as a replaced by XOR gates. One cannot replace randomly,
reversible Full adder with only two garbage outputs. the OR gates in equations of [13], thus a rigorous study
Thus, TSG gate is the most optimized gate for has been done and OR gates in equations of [13] have
implementation of a reversible Full adder as far as been replaced at selective places. The functional
known literature and our knowledge is concerned. It is

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 verification of the proposed CLA BCD adder is done S[2]=(p[2]·g[1]) (p[3]·h[2]·p[1]) ((g[3] (h[2]·h[1]))·C1)
in Verilog HDL using ModelSim simulator. Following (((p[3] · p[2] · p[1]) (g[2] · g[1]) (p[3] · p[2])) · C1)
are the advantages of using this approach
S[3]=((m· n)·C1) (((g[3] · h[3]) (h[3] · h[2] · h[1])) · C1)
1. In the conventional CMOS logic, XOR gate can be
Cout = m + (n · C1)
designed, with less number of transistors compared to
OR gate. In the above equations, S[3], S[2],S[1],S[0] represents
the sum bits produced by addition of BCD numbers,
2. Recently, novel 2T-MUX architecture has been
a and b and having a input carry Cin. The output
proposed in which the 2:1 MUX can be designed with
carry produced by the CLA BCD adder is represented
only 2 transistors [14].
by Cout.
3. The advantage of the 2T MUX is that in addition
to reduced transition activity and charge recycling
capability, it has no direct connections to the power- 4. Proposed Carry Skip Adder
supply nodes, leading to a noticeable reduction in
short-current power consumption. The proposed Carry Skip BCD Adder is being
constructed in such a way that, the first full adder
4. The XOR gate can be realized by using two 2T block consisting of 4 full adders can generate the
MUX as shown in the Fig.2 below output carry ‘Cout’ instantaneously, depending on the
input signal and ‘Cin’, without waiting for the carry to
be propagated in the ripple carry fashion. Fig.3 shows
the proposed Carry Skip BCD adder. The working of
the proposed Carry Skip BCD Adder (CS BCD Adder)
can be explained as follows.
In the single bit full adder operation, if either input
Figure 2. (a) 2T MUX architecture is a logical one, the cell will propagate the carry input
(b) XOR using 2T MUX to its carry output. Hence, the ith full adder carry input
Ci, will propagate to its carry output, Ci+1, when Pi=
5. In the reversible logic, the multi-input XOR gate Xi Yi where Xi and Yi represents the input signal to
can be realized with less number of gates and garbage the ith full adder. In addition, the four full adders at
outputs compared to multi-input OR gate. For the first level making a block can generate a “block”
example, the equation a b c can be realized with propagate signal ‘P’. When ‘P’ is one, it will make the
only one reversible gate and two garbage output block carry input ‘Cin’, to propagate as the carry
compared to a+b+c ( here + refers an OR gate), which output ‘Cout’ of the BCD adder, without waiting for
can be realized with two reversible gates and five the actual propagation of carry, in the ripple carry
garbage outputs. This advantage of XOR gate will fashion. An AND gate is used to generate a block
become more dominant as the input size is increased propagate signal ‘P’. Furthermore, depending on the
beyond three. value of ‘Cout’, appropriate action is taken. When it is
Consider two BCD numbers a and b of 4 bits each, equal to one, binary 0110 is added to the binary sum
using the proposed approach, the functions used to using another 4-bit binary adder (Second level or
generate Carry Look-Ahead BCD Adder are as bottom binary adder). The output carry generated from
follows the bottom binary adder is ignored, since it supplies
g[j] = a[j] · b[j] 0≤ j ≤ 3 “generate” information already available at the output carry
terminal.
p[j] = a[j] + b[j] 0≤ j ≤ 3 “propagate”
h[j] = a[j] b[j] 0≤ j ≤ 3 “half-adder”
m = g[3] (p[3] · p[2]) (p[3] · p[1]) (g[2] · p[1])
n= p[3] g[2] (p[2] · g[1])
C1 = g[0] + (p[0] · Cin) “carry out of 1’s position”
S[0] = h[0] Cin
S[1] = ((h[1] m) · C1) + ((h[1] n) · C1)

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 Figure 4. Reversible 4 *4 TSG proposed in [12]

Figure 3. Proposed Carry Skip BCD Adder

Figure 5. TSG Gate working Singly as a
Reversible Full Adder
5. Reversible Logic Implementation of
BCD Adders 5.2 Novel Reversible TS-3 Gate
The proposed reversible TS-3 gate is a 3*3 two
In order to implement the reversible logic design of the through gate as shown in Fig. 6. It can be verified
conventional and the proposed BCD adders, some of from that in TS-3 gate, the input pattern corresponding
the basic concepts of the reversible logic are discussed. to a particular output pattern can be uniquely
determined.
5.1. Basic Reversible Gates
There are number of a existing reversible gates in
literature such as Fredkin gate [6,7,8], Toffoli Gate
(TG) [6,7] and the New Gate (NG) [8]. Since, the
major reversible gate used in designing the BCD
adders is TSG gate, hence only the TSG gate is
discussed in this section.
5.1.1. TSG Gate Figure 6. Proposed 3 *3 Reversible TS-3 Gate
Recently, a 4 * 4 one through reversible gate called TS
gate “TSG” is proposed [12]. The reversible TSG gate The proposed TS-3 gate can be used to implement any
is shown in Fig. 4. The TSG gate can implement all Boolean function, since its third output can work as a
Boolean functions. One of the prominent functionality three input XOR gate. Further, the proposed gate will
of the TSG gate is that it can work singly as a be of great help in avoiding the fan out problem, since
reversible Full adder unit. Fig.5 shows the two its inputs are directly passed as output.
implementation of the TSG gate as a reversible Full
adder. A number of reversible full adders were
proposed in [15,16,17,18]. The full adder designed 6. Reversible Logic Implementation of
using TSG in Fig. 5 requires only one reversible gate Conventional BCD Adder
(one TSG gate) and produces only two garbage outputs
(Garbage output refers to the output that is not used for Figure 7 shows the reversible implementation of the
further computations. In other words, it is not used as a conventional BCD using the reversible TSG gates. For
primary output or as an input to other gate.). It is optimized implementation of the BCD adder; New
shown that the full-adder design in Fig. 5 using TSG Gate (NG) is also used for producing the best
gate is better than the existing full-adder designs [12]. optimized BCD adder. Recently the reversible
implementation of the conventional BCD adder is
proposed in [11]. The BCD adder using the TSG gate
is found to be much better than the architecture
proposed in [11]; both in terms of number of reversible
gates and garbage outputs produced. The proposed
BCD adder architecture in Fig. 7 using TSG gates uses

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 only 11 reversible gates and produces only 22 garbage the spirit of carry skip addition, by propagating the
outputs, compared to 23 reversible gates and 22 correct value of ‘Cin’ to ‘Cout’. In the AND-OR logic
garbage outputs implementation of [11]. Table 1 shows combination in Fig. 3 generation of ‘Cout’ will be
the result which compares the proposed reversible postponed until ‘C4’ is resolved, while in the
BCD adder using TSG gate with the BCD adder proposed reversible architecture, Fredkin carry skip
proposed in [11]. logic passes ‘Cin’ to ‘Cout’ whenever ‘P’=1,
regardless of the value of ‘C4’, thus time saving is
significant. Furthermore, in the proposed carry skip
adder of Fig.3, it has been observed that the 3 input
OR gate, used for generating the ‘Cout’ can be
replaced by three input XOR gate. Thus, the novel
proposed ‘TS-3’ gate helps in the realization of
3 inputs XOR gate, with bare minimum of one
reversible gate. Additionally, it can also help in
avoiding the problem of fan out, as two of the inputs
are directly passed as outputs. The numbers of
reversible gates used in the proposed reversible logic
implementation of the Carry Skip BCD adder are 15
and the garbage outputs produced are 27.

Figure 7. Reversible Logic Implementation of

the Conventional BCD Adder Using TSG and
NG Gates

7. Reversible Logic Implementation of

Carry Skip BCD Adder
The proposed Carry Skip Adder is further been
modified to make it more suitable for reversible logic
implementation. Fig. 8 shows the block diagram of the
carry skip adder block constructed with TSG gates and Figure 8. Reversible Logic Implementation of
Fredkin gates (F). The three Fredkins in the middle of the Proposed Carry Skip BCD Adder
Fig. 8 are used to perform the AND4 operation. This
will generate the block propagate signal ‘P’. The single The proposed reversible implementation of the
FG in the right side of Fig. 8 performs the AND-OR Carry Skip BCD adder is still better, compared to the
function while in conventional logic, the carry skip reversible logic implementation of the conventional
block in Fig.3 uses the AND-OR gate combination to BCD adder proposed in [11], in terms of reversible
create the carry skip logic. gates used. A comparative analysis of the BCD adders
is shown in Table 1. Furthermore, the time saving in
In the proposed carry Skip adder, the FG propagates the proposed reversible carry skip BCD adder is
the block’s carry input ‘Cin’ to the next block if the significant compared to [11]. This is due to carry
block propagate signal ‘P’ is one ; otherwise, the skipping and this feature was not available in the
most significant full adder carry ‘C4’ is propagated to reversible BCD adder of [11], since it was a mere
the next block. The traditional carry skip AND-OR conventional BCD adder.
logic in Fig.3 and the carry skip logic in Fig. 8 do not
have equivalent truth tables, but it must be noted that
the Fredkin carry skip logic more faithfully adheres to

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 Table 1. Comparative Analysis of the [3] http://www2.hursley.ibm.com/decimal/754r-status.html
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ongoing revision to the IEEE 754 floating point
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