PO

Sno CO Content
Related

1 Utilise the knowledge Digital systems, Number systems, Counting in radix, 1

of number systems in Conversion of one radix to other, Complements of
digital design and numbers, Signed binary numbers, Arithmetic 2
evaluate the errors in addition and subtraction, 4-bit codes: BCD codes,
Excess-3, Gray code, r’s and r-1’s complement, Error 3
digital transmission of
data using error codes detecting & Error correcting codes, Basic logic 4
gates, Universal gates, Ex-OR , Ex-NOR gates.
5
6
7
8
9
10
11
12
Utilise laws of Basic Theorems and Properties of Boolean algebra, 1
Boolean algebra and Boolean Functions, Canonical and Standard Forms,
minimization Min-terms and Max- terms, Products of Sum 2
techniques to simplify Simplification, Sum of Products Simplification, Gate 3
and design logic level Minimization: Map Method, Two-Variable K-
circuits Map, Three-Variable K-Map, Four Variable K-Maps, 4
Five
Variable K-Maps, Don’t – Care Conditions, Quine–Mc 5
Cluskey method, NAND and NOR Implementation,
Exclusive‐ORfunction, Code converters. 6
2
7
8
9
10
11
12
Design and analyse the Introduction, Adder, Subtractor, 4-Bit binary adder, 1
operation of 4-Bit binary Subtractor, BCD adder circuit, Carry
Combinational look-a-head adder circuit, Decoders, Encoders, 2
Circuits and Multiplexers, Higher order multiplexers, De-
Programmable Logic Multiplexers, Priority encoder, Magnitude 3
Devices comparator. 4
from the description of a Programmable Logic Devices: PROM, PAL, PLA-Basics
logical structures, Realization of boolean function with 5
function PLDs, Programmingtables of PLDs, merits &
demerits of PROM, PAL, PLA comparison, Realization 6
3
of Boolean functions using PROM, PAL, PLA, 7
Programming tables of PROM, PAL
8
9
10
 11
12
4 Design and analyse Introduction to sequential circuits, Storage elements: 1
the Latches, Flip‐flops, RS- Latch using NAND and NOR
operation of sequential Gates, RS, JK, T and D Flip Flops, Master Slave 2
Circuits JK flip flop, Excitation tables and Characteristic
from the description of a equations, Conversion of flip flops. Registers, Shift 3
logical registers, Universal shift register, Asynchronous 4
function counters,
Synchronous counters, Ring counter, Johnson 5
counter
6
4
7
8
9
10
11
12
5 Write HDL code for Design flow, Program structure, Levels of 1
the design of digital logic abstraction, Elements of VHDL: Data types, Data
circuits objects, operators and identifiers. Packages, 2
Libraries and
Bindings, Subprograms. VHDL Programming using 3
structural and data flow modelling. HDL 4
implementation of combinational and Sequential
Logic 5
Circuits.
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5
7
8
9
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 Effected
Total Number
Effected Key elements Corresponding to Key
of Key
that PO Elements
Elements
Number

1,3, 4 4 3
3,5 6 2
3
5
5
3
2
2
2
4
2
3
1,3,4 4 3
2,3,5 6 3
3 3 1
2 5 1
1 5 1
3
2
2
2
4
2
3
1,3,4 4 3
3,5 6 2
3 3 1
2,5 5 2
1 5 1
3
2
2
2
4
 2
3
1,3,4 4 2
3,5 6 1
3 3 1
5
1 5 1
3
2
2
2
4
2
3
1,3,4 4 2
2,5 6 2
3
5
1,2,4 5 3
3
2
2
2
4
2 2 1
1,2 3 2
Total 164 33
Total
Ratio (%) 20.1