Effected Key

elements Total Number

Corresponding of Key
Sno CO Content PO Related to that PO Elements
1 Utilise the Digital systems, 1 1,3, 4 4
knowledge of Number systems, 2 3,5 6
number systems Counting in radix,
in digital design Conversion of one 3 3
and evaluate radix to other, 4 5
the errors in Complements
numbers, Signed
of
5 5
digital binary numbers,
transmission of Arithmetic 6 3
data using error addition and 7 2
codes subtraction, 4-bit 8 2
codes: BCD codes,
Excess-3, Gray 9 2
code, r’s and r-1’s 10 4
complement, Error 11 2
detecting & Error
correcting codes, 12 3
Utilise laws of Basic Theorems 1 1,3,4 4
Boolean algebra and Properties of 2 2,3,5 6
and Boolean algebra,
minimization Boolean Functions, 3 3 3
techniques to Canonical and 4 2 5
simplify and Standard Forms,
Min-terms and 5 1 5
design logic Max- terms,
circuits 6 3
Products of Sum
Simplification, Sum 7 2
of Products 8 2
Simplification,
Gate level 9 2
Minimization: Map 10 4
Method, Two- 11 2
Variable K-Map,
2 Three-Variable K- 12 3
Design and Introduction, 1 1,3,4
analyse the Adder, Subtractor, 4
operation of 4-Bit binary adder, 2 3,5 6
Combinational 4-Bit binary
Circuits and Subtractor, BCD 3 3 3
Programmable adder circuit, Carry 4 2 5
Logic Devices look-a-head adder
from the circuit, Decoders, 5 1 5
description of a Encoders, 6 3
logical Multiplexers,
function Higher order 7 2
multiplexers, De- 8 2
Multiplexers,
Priority encoder, 9 2
Magnitude 10 4
comparator. 11 2
Programmable
3 Logic Devices: 12 3
4 Design and Introduction to 1 1,3,4
analyse the sequential circuits, 4
operation of Storage elements: 2 3,5 6
sequential Latches, Flip‐flops,
Circuits RS- Latch using 3 3 3
from the NAND and NOR 4 2 5
description of a Gates, RS, JK, T and
logical
function
 analyse the
operation of
sequential
Circuits
from the
description of a Gates, RS, JK, T and
logical D Flip Flops, 5 1 5
function Master Slave 6 3
JK flip flop,
Excitation tables 7 2
and Characteristic 8 2
equations,
Conversion of flip 9 2
flops. Registers, 10 4
Shift registers, 11 2
Universal shift
4 register, 12 3
5 Write HDL code Design flow, 1 4
for the design of Program structure, 4
digital logic Levels of 2 2,5 6
circuits abstraction,
Elements of VHDL: 3 3
Data types, Data 4 5
objects, operators
and identifiers. 5 1,2,4 5
Packages, Libraries 6 3
and
Bindings, 7 2
Subprograms. 8 2
VHDL 9 2
Programming using
structural and data 10 4
flow modelling. 11 2 2
HDL
5 implementation of 12 1,2 3
combinational and
Total 164
Total
Ratio (%)
Effected Key
Elements
Number
3
2

3
3
1
1
1

3
2
1
1
1

3
2
1
1
1

1
2

1
2
39

23.8
 CO - PO MAPPING BASED
4 6 3 5
CO/PO PO1 PO2 PO3 PO4
CO1 3 2
CO2 3 3 1 1
CO3 3 2 1 1
CO4 3 2 1 1
CO5 1 2

CO/PO PO1 PO2 PO3 PO4

CO1 0.75 0.33 0.00 0.00
CO2 0.75 0.50 0.33 0.20
CO3 0.75 0.33 0.33 0.20
CO4 0.75 0.33 0.33 0.20
CO5 0.25 0.33 0.00 0.00
Average 0.65 0.37 0.20 0.04
Observed Minimum is 0.20 , Max
< 0.383 = Level 1 between 0.383 an

CO/PO PO1 PO2 PO3 PO4

CO 2 1 1 1.00
 - PO MAPPING BASED ON KEY ELEMENTS
5 3 2 2 2 4 2
PO5 PO6 PO7 PO8 PO9 PO10 PO11

1
1
1
3 1

PO5 PO6 PO7 PO8 PO9 PO10 PO11

0.00 0.00 0.00 0.00 0.00 0.00 0.00
0.20 0.00 0.00 0.00 0.00 0.00 0.00
0.20 0.00 0.00 0.00 0.00 0.00 0.00
0.20 0.00 0.00 0.00 0.00 0.00 0.00
0.60 0.00 0.00 0.00 0.00 0.00 0.50
0.24 0.00 0.00 0.00 0.00 0.00 0.1
ved Minimum is 0.20 , Maximum is 0.75 Range is 0.55 range/3=0.183
evel 1 between 0.383 and 0.566 = Level 2 and 0.749 and above = Level 3

PO5 PO6 PO7 PO8 PO9 PO10 PO11

1 0 0.00 0 0 0.00 1.00
 3 5 3
PO12 PSO1 PSO2
2 2
2 2
2 2
2 2
2 2 2

PO12 PSO1 PSO2

0.00 0.40 0.67
0.00 0.40 0.67
0.00 0.40 0.67
0.00 0.40 0.67
0.67 0.40 0.67
0.13 0.40 0.67

PO12 PSO1 PSO2

1 2 2