0800CST203122004

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APJ ABDUL KALAM TECHNOLOGICAL UNIVERSITY

Scheme for Valuation/Answer Key
Scheme of evaluation (marks in brackets) and answers of problems/key
Third Semester B.Tech Degree Examination December 2021 (2019 scheme)
Course Code: CST203
Course Name: Logic System Design
Max. Marks: 100 Duration: 3 Hours

PART A
Answer all questions. Each question carries 3 marks Marks
1 a)Conversion of hexadecimal to octal Ans 113336 (1.5)
b)Conversion of binary to octal Ans 1330 (1.5)
2 Subtraction using 2’s complement representation (1.5)
and 1’s complement representation Ans 0100011=+35 (1.5)
3 Statement (1)
Proof of extended De Morgan’s theorem (2)
4 Using Huntington’s postulates proof of
a) (x + x ). 1= (x +x)(x + x’)=x+xx’=x+0=x (1.5)
b)1.( x + 1) = (x+x’).(x+1)=x+x’.1=x+x’=1 (1.5)
5 Differences between decoder and demultiplexer (3)
6 Truth table (1) (1) (1)
Boolean function
Circuit of half adder
7 Excitation table and characteristic equation of T flip-flop Q(t+1)=T XOR Qt (1.5)
Excitation table and characteristic equation of D flip-flop Q(t+1)=D (1.5)
8 Explanation of race around problem (1.5)
Explanation of elimination (1.5)
9 algorithm for addition of two binary numbers in 2’s complement form (3)
10 Explanation of programmable logic array (1.5)

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Explanation of application area (1.5)

PART B
Answer any one full question from each module. Each question carries 14 marks
Module 1
11 a) Conversion of i) (214)10 to binary=11010110, octal=326, (4x1)
BCD=001000010100 and hexadecimal=D6 (4x1)
Conversion of ii) (128) to binary=10000000, octal=200, (3x2)
BCD=000100101000 and hexadecimal=80
b) Representation of -219 and -114 in
i) sign magnitude form 1 11011011 , 1 1110010
ii) 1’s complement form 100100100, 10001101
iii) 2’s complement form 100100101, 10001110
12 a) Addition in i) octal 114 ii) BCD 0001 0010 0111 + (3x2)
0111001100101
1000 1000 1100 +
0110
1000 1001 0010 =892
iii) hexadecimal 88C
b) Subtraction in i) octal 7’s comp of 157=620 615+ 620= 436
ii) BCD 9’s comp of 157= 842
0110 0001 0101 +
1000 0100 0010
1110 0101 0111
0110
1 0100 0101 0111+
1
0100 0101 1000 =458

iii) hexadecimal 15’s comp of 157=EA8

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615 +EA8=4BE (3x2)

c) subtraction using 2’s complement form
01001100111 +
11101100011
1 00111001010
Discard carry Ans 00111001010= +458

Module 2
13 a)Define Boolean algebra. (4) (4)
example (3)
b) implementation using NAND (3)
implementation using NOR
14 a) Simplification of Boolean function F(a,b,c,d) = ∑ (7)
(0,1,2,5,7,8,9,10,11,13,15) using K map Ans b’d’ + b’c’ + bd+ ad or b’d’ +
c’d + bd+ad or b’d’ +c’d + ab’ +bd (7)
b) Simplification using tabulation method. 7 minterm groups a’c’d , a’bd,b’c’
,b’d’,ab’,c’d,bd,ad
Essential PI=b’d’
F= b’d’ + b’c’ + bd+ ad or b’d’ + c’d + bd+ad or b’d’ +c’d + ab’ +bd
Same ans in tabulation and k-map
Module 3
15 a)Logic diagram of parallel adder/subtractor circuit (8)
Explanation of parallel adder/subtractor circuit
b)carry look ahead adder circuit for four bit binary addition (3)
explanation (3)
16 a)K map (2)
Simplified Boolean function (2)
Logic diagram for converting binary number to BCD number (4)
b)logic diagram of 4x2 encoder circuit (3)

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explanation (3)
Module 4
17 a) logic diagram (3)
timing sequence (3)
explanation of 3 bit binary asynchronous counter (2)
b) logic diagram (3)
explanation of asynchronous BCD counter (3)
18 a)excitation table, characteristic equation and explanation of i)SR flip-flop (4)
excitation table, characteristic equation and explanation of ii) JK flip-flop (4)
excitation table, characteristic equation and explanation of iii) master-slave (4)
flip-flop
b) Explanation of edge triggered flip-flop (2)
Module 5
19 a)logic diagram, (2)
timing sequence (2)
state diagram (2)
explanation of a ring counter (4)
b) logic diagram of a serial in parallel out shift register (2)
explanation (2)
20 a)algorithm for addition and subtraction of two BCD numbers (4)
Illustration with an example (4)
b)Explanation of PLA (3)
Illustration of implementation of simple functions with using PLA (3)

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