08000CST203122301 Pages 4

Scheme of Valuation/Answer Key

Scheme of evaluation (marks in brackets) and answers of problems/key
APJ ABDUL KALAM TECHNOLOGICAL UNIVERSITY
B. Tech Degree S3 (S,FE)/S1 (PT)(S) June 2024 (2019 Scheme)/S3 (WP)(R)
December 2023 Examination
Course Code: CST203
Course Name: Logic System Design
Max. Marks: 100 Duration: 3 Hours

PART A
Answer all questions. Each question carries 3 marks Marks
1 a) (CF8E)16 = (1100111110001110)2 (1.5)
b) (359)10 = (547)8 (1.5)

2 1 000000000101011 1010000000000000 (3)

The first bit (leftmost bit) represents the sign, where 1 indicates a negative
number, and 0 indicates a positive number. The next 15 bits represent the
integer part (in binary), and the last 16 bits represent the fractional part (also in
binary).
3 (A+B)(A+C) = A.A+A.C+A.B+B.C (3)
= A(1+C)+AB+BC
= A.1+AB+BC
= A+AB+BC
=A(1+B)+BC
=A.1+BC
=A+BC
4 Define De Morgan’s Theorem (1.5 marks) (3)
(A+B)′ = (A)′. (B)′
(A.B)′ = (A)′+ (B)′
Reduce the expression F= ((AB)′ + A′ +AB)′ using De Morgan’s Theorem
Answer is F=0 (1.5 marks)

5 Boolean function (1 marks) (3)

Logic diagram of a 4x1 multiplexer circuit (2marks)

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6 Truth table (1 marks) (3)

Boolean function (1 marks)
Circuit of half subtractor (1 marks)
7 Excitation table (1 marks) (3)
K Map (1 marks)
Characteristic equation of a D flip flop (1 marks)
8 Explanation of edge triggered flip-flop (3)
9 Explanation (1.5 marks) (3)
Diagram (1.5 marks)
10 Explanation of PROM, EPROM, EEPROM. (1mark each) (3)
PART B
Answer any one full question from each module. Each question carries 14 marks
Module 1
11a) i) (5C7)16 = (1479)10 (3marks) (6)
ii)(756.603)8 = (1EE.C18)16 (3marks)

b) i) (1776)8 +(1345)8 = (3343)8 (4marks) (8)

ii) (ADD)16 + (DAD)16 = (188A)16 (4marks)
12a) 8 bit signed binary number form for +25 is 00011001 (6)
-25 in sign magnitude form:- 10011001 (2 marks)
-25 in 1’s complement form:- 11100110 (2 marks)
-25 in 2’s complement form:- 11100111 (2 marks)

b) (5)
i) 9’s complement of 812 = 187
Add 9’s complement of 812 to 983
1001 1000 0011 +
0001 1000 0111
---------------------
1011 0000 1010
Add 0110 to Invalid BCD Code in the result
1011 0000 1010 +
0110 0110 0110
-----------------------
0001 0111 0001

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ii)Add (147)8 to (261)8 :- Answer (430)8

(3)
Module 2
13a) Kmap (5 marks) (8)
Reduced SOP :- A′B′ + CD (3 marks)

b) implementation using NAND

(3)
implementation using NOR (3)

14a) Answer :- B′C′+ CD (10)

b) F = (A+B′+C)(A+B′+C′)(A+B+C)(A′+B+C)(A+B+C′) (4)
Module 3
15a) Half adder logic diagram with equation (3)
(2)
Full adder characteristic equation
Design of Full adder with 2 half adders. (3)

(b) Truth table (2)

(2)
Equations
Logic diagram (2)
16a) logic diagram of 8x3 encoder circuit (3)
(3)
Explanation

b) carry look ahead adder circuit diagram for three bit binary addition
(3)
explanation (2)
sum and carry generation and propagation expressions.
(3)

Module 4
17a) State diagram and state table (3)
Characteristic Equation (2)
logic diagram of Synchronous counter (2)

b)
logic diagram (3)
(2)
timing sequence
(2)

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explanation of 2 bit binary asynchronous up counter

18a) excitation table, characteristic equation and explanation of i)SR flip-flop (4)
excitation table, characteristic equation and explanation of ii) JK flip-flop
(4)
excitation table, characteristic equation and explanation of iii) T flip-flop (4)

b) Explanation of race around problem. (2)

Module 5
19a) logic diagram, (3)
(2)
timing sequence
(2)
state diagram
(2)
explanation of a ring counter

(2)
b) k map
PLA implementation diagram (3)
20a) logic diagram, (2)
(2)
timing sequence
state diagram (2)
explanation of a Johnson counter
(2)

b) algorithm for addition and subtraction two binary numbers in sign

(4)
magnitude form
Illustration with example
(2)

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