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Tutorial 7cache

Tutorial 7Cache

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Sasuke Uchiha
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37 views

Tutorial 7cache

Tutorial 7Cache

Uploaded by

Sasuke Uchiha
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Tutorial problems on memory systems

1. A two-way set-associative cache of 8KB capacity has lines of 16 bytes each. Main
memory is 64MB and is byte addressable. Find the format of main memory address
(tag, set address etc.)

2. Consider a 32-bit microprocessor that has on-chip 16-KB 4-way set-associative cache.
Line size in cache is four 32-bit words (128 bits). How are the different address fields
used to determine a cache hit or miss. Where in the cache is the word from memory
location ABCDE8F8 mapped?

3. Given cache specifications: four-way set-associative; line size of two 16-bit words;
can accommodate 4K 32-bit words; used with a 16-bit processor that issues 24 bit
addresses. Design the cache structure and show how it interprets the processor’s
address.

4. Consider a cache of 4 lines of 16 bytes each. Main memory has blocks of 16 byte each.
Thus block 0 has bytes with addresses 0 through 15, and block 1 has addresses 16
through 31 etc.. Consider a program that accesses memory in following sequence of
addresses:
Once: 63 through 70
Loop 10 times: 15 through 32; 80 through 95
(a) Assuming direct mapping, calculate the hit ratio for the program
(b) Assume that the cache is two-way set-associative with two sets of two lines each.
Even numbered blocks are assigned to set 0 and odd-numbered blocks are
assigned to set 1. Compute the hit ratio assuming LRU policy for replacement

5. Consider a single-level cache with an access time of 2.5 ns, a line size of 64 bytes,
and a hit ratio of 0.95. Main memory uses a block transfer capability that has a first
word (4 bytes) access time of 50 ns and an access time of 5ns for each subsequent
word.
(a) Find the access time when there is a cache miss. Assume that the cache waits until
the line has been fetched from main memory and then re-executes for a hit.
(b) Suppose the line size increased to 128 bytes which increases H to 0.97. Does this
reduce the average memory access time?

6. A system with 350 MHz clock uses a separate data and instruction cache and a
unified second-level cache. The first level cache is direct–mapped, write-through,
and writes-allocate cache with 8kBytes of data total and 8 Byte blocks, and has a
perfect write buffer (never causes and stalls). The first level instruction cache is a
direct-mapped cache with 4kBytes of total data and 8 Bytes blocks. The second level
cache is a two way set associative, write-back, write-allocate cache with 2Mbytes of
total data and 32-Byte blocks.
The 1st level instruction cache has a miss rate of 2%. The first level data cache has a
miss rate of 17%. The unified second level cache has a local miss rate of 12%.
Assume that 30% of all instructions are data memory accesses; 50% of those are
loads and 50% are stores. Assume that 50% of the blocks in the second-level cache
are dirty at any time. Assume that there is no optimization for fast reads on L1 or L2
cache miss.
All the first-level cache hits cause no stalls. The second-level hit times is 10 cycles.
(That means that the L1 miss penalty, assuming a hit in the L2 cache is, 10 cycles.)
Main memory access time is 100 cycles to the first bus width of data; after that, the
memory system can deliver consecutive bus widths of data on each following cycle.
Outstanding non-consecutive memory requests cannot overlap; an access to one
memory location must complete before an access to another location can begin.
There is a 128-bit memory to the L2 cache and a 64-bit bus from both the L1 caches
to the L2 cache. Assume a perfect TLB for this problem.
a. What percent of all data memory references cause a main memory access
(main memory is accessed before the memory request is satisfied)?
b. How many bits are used to index each of the caches? Assume you can use
physical addresses for cache.
c. How many cycles can the longest possible data memory access take?
d. What is the average memory access time in cycles (including instruction and
data memory references)?

7. A computer system has 16 MB of addressable memory and a 256 KB cache with 16


bytes per line. Find for all three mapping strategies Direct, Associative and 4-way set
associative (i) Number of sets and lines in cache, (ii) Number of blocks in main
memory, and (iii) Number of address bits used for tag, set and line number. For
following references with LRU, find the hit ratio in all three mapping cases. Assume
the cache is empty in the beginning. We start executing a program that refers to
following 10 memory addresses (Hexadecimal values) in the given order: 3C2B20,
3C2324, 172B24, 3C2B27, 258032, 222B28, 172B28, 3C2B22, 3C2326, 172B21.

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