UNIT 2 ARCHITECTURE OF 8085

Architecture of 8085 microprocessor

The 8085 microprocessor is an 8-bit microprocessor that was developed by Intel in the mid-1970s. It was
widely used in the early days of personal computing and was a popular choice for hobbyists and enthusiasts
due to its simplicity and ease of use. The architecture of the 8085 microprocessor consists of several key
components, including the accumulator, registers, program counter, stack pointer, instruction register, flags
register, data bus, address bus, and control bus.
The accumulator is an 8-bit register that is used to store arithmetic and logical results. It is the most commonly
used register in the 8085 microprocessor and is used to perform arithmetic and logical operations such as
addition, subtraction, and bitwise operations.
1.
The 8085 microprocessor has six general-purpose registers, including B, C, D, E, H, and L, which can be
combined to form 16-bit register pairs. The B and C registers can be combined to form the BC register pair, the
D and E registers can be combined to form the DE register pair, and the H and L registers can be combined to
form the HL register pair. These register pairs are commonly used to store memory addresses and other data.
The program counter is a 16-bit register that contains the memory address of the next instruction to be
executed. The program counter is incremented after each instruction is executed, which allows the
microprocessor to execute instructions in sequence.
The stack pointer is a 16-bit register that is used to manage the stack. The stack is a section of memory that is
used to store data temporarily, such as subroutine addresses and other data. The stack pointer is used to keep
track of the top of the stack.
The instruction register is an 8-bit register that contains the current instruction being executed. The instruction
register is used by the microprocessor to decode and execute instructions.
2.
The flags register is an 8-bit register that contains status flags that indicate the result of an arithmetic or logical
operation. These flags include the carry flag, zero flag, sign flag, and parity flag. The carry flag is set when an
arithmetic operation generates a carry, the zero flag is set when the result of an arithmetic or logical operation is
zero, the sign flag is set when the result of an arithmetic or logical operation is negative, and the parity flag is
set when the result of an arithmetic or logical operation has an even number of 1 bits.
3.
The data bus is an 8-bit bus that is used to transfer data between the microprocessor and memory or other
devices. The data bus is bidirectional, which means that it can be used to read data from memory or write data
to memory.
The address bus is a 16-bit bus that is used to address memory and other devices. The address bus is used to
select the memory location or device that the microprocessor wants to access.
4.
The control bus is a set of signals that controls the operations of the microprocessor, including the read and
write operations. The control bus includes signals such as the read signal, write signal, interrupt signal, and
reset signal. The read signal is used to read data from memory or other devices, the write signal is used to write
data to memory or other devices, the interrupt signal is used to signal the microprocessor that an interrupt has
occurred, and the reset signal is used to reset the microprocessor to its initial state.
8085 is an 8-bit, general-purpose microprocessor. It consists of the following functional units:
Arithmetic and Logic Unit (ALU) :
It is used to perform mathematical operations like addition, multiplication, subtraction, division, decrement,
increment, etc. Different operations are carried out in ALU: Logical operations, Bit-Shifting Operations, and
Arithmetic Operations.

Flag Register:
It is an 8-bit register that stores either 0 or 1 depending upon which value is stored in the accumulator. Flag
Register contains 8-bit out of which 5-bits are important and the rest of 3-bits are “don’t Care conditions”. The
flag register is a dynamic register because after each operation to check whether the result is zero, positive or
negative, whether there is any overflow occurred or not, or for comparison of two 8-bit numbers carry flag is
checked. So for numerous operations to check the contents of the accumulator and from that contents if we
want to check the behavior of given result then we can use Flag register to verify and check. So we can say that
the flag register is a status register and it is used to check the status of the current operation which is being
carried out by ALU.
Different Fields of Flag Register:
1. Carry Flag
2. Parity Flag
3. Auxiliary Carry Flag
4. Zero Flag
5. Sign Flag

Accumulator:
Accumulator is used to perform I/O, arithmetic, and logical operations. It is connected to ALU and the internal
data bus. The accumulator is the heart of the microprocessor because for all arithmetic operations
Accumulator’s 8-bit pin will always there connected with ALU and in most-off times all the operations carried
by different instructions will be stored in the accumulator after operation performance.

General Purpose Registers:

There are six general-purpose registers. These registers can hold 8-bit values. These 8-bit registers are
B,C,D,E,H,L. These registers work as 16-bit registers when they work in pairs like B-C, D-E, and H-L. Here
registers W and Z are reserved registers. We can’t use these registers in arithmetic operations. It is reserved for
microprocessors for internal operations like swapping two 16-bit numbers. We know that to swap two numbers
we need a third variable hence here W-Z register pair works as temporary registers and we can swap two
16-bit numbers using this pair.

Program Counter :
Program Counter holds the address value of the memory to the next instruction that is to be executed. It is a
16-bit register.

Stack Pointer :
It works like a stack. In stack, the content of the register is stored that is later used in the program. It is a 16-bit
special register. The stack pointer is part of memory but it is part of Stack operations, unlike random memory
access. Stack pointer works in a continuous and contiguous part of the memory. whereas Program Counter(PC)
works in random memory locations. This pointer is very useful in stack-related operations like PUSH, POP, and
nested CALL requests initiated by Microprocessor. It reserves the address of the most recent stack entry.

Temporary Register:
It is an 8-bit register that holds data values during arithmetic and logical operations.

Instruction register and decoder:

It is an 8-bit register that holds the instruction code that is being decoded. The instruction is fetched from the
memory.

Timing and control unit:

The timing and control unit comes under the CPU section, and it controls the flow of data from the CPU to other
devices. It is also used to control the operations performed by the microprocessor and the devices connected to
it. There are certain timing and control signals like Control signals, DMA Signals, RESET signals and Status
signals.

Interrupt control:
Whenever a microprocessor is executing the main program and if suddenly an interrupt occurs, the
microprocessor shifts the control from the main program to process the incoming request. After the request is
completed, the control goes back to the main program. There are 5 interrupt signals in 8085 microprocessors:
INTR, TRAP, RST 7.5, RST 6.5, and RST 5.5.
Priorities of Interrupts: TRAP > RST 7.5 > RST 6.5 > RST 5.5 > INTR

Address bus and data bus:

The data bus is bidirectional and carries the data which is to be stored. The address bus is unidirectional and
carries the location where data is to be stored.
In the 8085 microprocessor, the address bus and data bus are two separate buses that are used for
communication between the microprocessor and external devices.
The Address bus is used to transfer the memory address of the data that needs to be read or written. The
address bus is a 16-bit bus, allowing the 8085 to access up to 65,536 memory locations.
The Data bus is used to transfer data between the microprocessor and external devices such as memory and I/O
devices. The data bus is an 8-bit bus, allowing the 8085 to transfer 8-bit data at a time. The data bus can also
be used for instruction fetch operations, where the microprocessor fetches the instruction code from memory
and decodes it.
The combination of the address bus and data bus allows the 8085 to communicate with and control external
devices, allowing it to execute its program and perform various operations.

Serial Input/output control:

It controls the serial data communication by using Serial input data and Serial output data.
Serial Input/Output control in the 8085 microprocessor refers to the communication of data between the
microprocessor and external devices in a serial manner, i.e., one bit at a time. The 8085 has a serial I/O port
(SID/SOD) for serial communication. The SID pin is used for serial input and the SOD pin is used for serial
output. The timing and control of serial communication is managed by the 8085’s internal circuitry. The 8085
also has two special purpose registers, the Serial Control Register (SC) and the Serial Shift Register (SS), which
are used to control and monitor the serial communication.

The flow of an Instruction Cycle in 8085 Architecture :

1. Execution starts with Program Counter. It starts program execution with the next address field. it
fetches an instruction from the memory location pointed by Program Counter.
2. For address fetching from the memory, multiplexed address/data bus acts as an address bus and
after fetching instruction this address bus will now acts as a data bus and extract data from the
specified memory location and send this data on an 8-bit internal bus. For multiplexed
address/data bus Address Latch Enable(ALE) Pin is used. If ALE = 1 (Multiplexed bus is Address
Bus otherwise it acts as Data Bus).
3. After data fetching data will go into the Instruction Register it will store data fetched from memory
and now data is ready for decoding so for this Instruction decoder register is used.
4. After that timing and control signal circuit comes into the picture. It sends control signals all over
the microprocessor to tell the microprocessor whether the given instruction is for READ/WRITE
and whether it is for MEMORY/I-O Device activity.
5. Hence according to timing and control signal pins, logical and arithmetic operations are performed
and according to that data fetching from the different registers is done by a microprocessor, and
mathematical operation is carried out by ALU. And according to operations Flag register changes
dynamically.
6. With the help of Serial I/O data pin(SID or SOD Pins) we can send or receive input/output to
external devices .in this way execution cycle is carried out.
7. While execution is going on if there is any interrupt detected then it will stop execution of the
current process and Invoke Interrupt Service Routine (ISR) Function. Which will stop the current
execution and do execution of the current occurred interrupt after that normal execution will be
performed.
Uses of 8085 microprocessor :
The 8085 microprocessor is a versatile 8-bit microprocessor that has been used in a wide variety of
applications, including:
1. Embedded Systems: The 8085 microprocessor is commonly used in embedded systems, such as
industrial control systems, automotive electronics, and medical equipment.
2. Computer Peripherals: The 8085 microprocessor has been used in a variety of computer
peripherals, such as printers, scanners, and disk drives.
3. Communication Systems: The 8085 microprocessor has been used in communication systems,
such as modems and network interface cards.
4. Instrumentation and Control Systems: The 8085 microprocessor is commonly used in
instrumentation and control systems, such as temperature and pressure controllers.
5. Home Appliances: The 8085 microprocessor is used in various home appliances, such as washing
machines, refrigerators, and microwave ovens.
6. Educational Purposes: The 8085 microprocessor is also used for educational purposes, as it is an
inexpensive and easily accessible microprocessor that is widely used in universities and technical
schools.
Pin Diagram and Description of 8085 Microprocessor
Definition: 8085 is an 8-bit microprocessor as it operates on 8 bits. The size of the address bus in 8085 is 16
bits. Thus, can address 64 KB memory. An 8085 microprocessor is an IC with 40 pins and operates with +5V
power supply.
The pin configuration plays a very important role in understanding the architecture of 8085 microprocessor. So,
now let’s move further and understand how the processor operates inside any system with these 40 pins.
Pin Diagram of 8085 Microprocessor
The figure below shows the pin diagram of 8085 showing 40 pin configuration:
The signals of this 40 pin IC is grouped into 7 categories, which are given below:
1. Power supply and clock signals
2. Data bus
3. Address bus
 4. Serial I/O ports
5. Control and status signals
6. Interrupts and externally generated signals
7. Direct memory access
These are the categories among which the 40 pin configuration of 8085 is divided. So, let us proceed to
understand the role of each pin inside the 8085 microprocessor.
Pin Description of 8085 Microprocessor
1.Power supply and clock signals:
In 40 pin configuration, 4 pins are allotted to this particular category.

● VCC – Pin number 40 denotes VCC, and an external power supply of + 5 V is provided at this pin.
● VSS – Its pin number is 20. This pin shows the grounded connection of the microprocessor.
● X1 and X2 – These are represented by pin number 1 and 2 respectively in the pin configuration.
These 2 pins are connected with a crystal or LC network to maintain the internal frequency of the
clock generator.
● CLK (OUT) – It is the 37th pin of the 8085 IC and acts as the system clock that keeps the record of
time duration required by each operation to get completed.
2.Address Bus – This category contains 8 pins.
The address bus has 16 lines i.e.; it can carry 16 bits at a time. However, out of 16, 8 are multiplexed with the
data bus and the leftover 8 are separately shown by pin number 21 to 28 in the pin configuration.
These are used to carry the address of data and instruction from the processor to the memory location and is
unidirectional in nature. These are denoted by A8 to A15 that represents the 8 MSB of the memory location or
input-output address.
3.Data Bus with multiplexed address bus – This category also contains 8 pins.
The size of the data bus of the 8085 microprocessor is 8 bits. However, to reduce the number of bus lines these
8-bit data bus lines are multiplexed with the 8-bit address bus.
These are shown by pin number 12 to 19. The address bus is denoted by A whereas the data bus is denoted by
D. The pin configuration denotes the lower order multiplexed address and data bus bits from AD0 to AD7.
We have already discussed that the address bus contains the address of the desired memory location from
where the data or instruction is to be fetched. While the data bus contains the data or instruction that is needed to
be fetched from the memory.
4.Serial I/O ports :
It has basically 2 pins.
● SID – SID denotes serial input data pin and its pin is numbered as 5. With this pin, data is serially
fed to the processor directly through the input devices.
● SOD – SOD denotes serial output data pin and its pin number is 4, in the pin configuration of
8085. Once the data is processed in the microprocessor then this pin represents bit by bit results at
the output devices.
5.Control and status signals :
Basically, 6 pins of the pin configuration are used by control and status signals.
● ALE – ALE is an acronym for address latch enable and is pin number 30 in the configuration. We
know that 8 lower order bits of the 16-bit address bus are multiplexed with the 8-bit data bus.
This pin gets enabled at the time when the address is present at the multiplexed address and data bus.
Otherwise, it gets disabled showing the absence of an address on the bus.
● RD – This pin is numbered 32 in the configuration and a low signal in this pin shows the read
operation either from I/O devices or from the memory unit. Thereby indicating that the data bus is
now in a state or position to accept the data from the memory or I/O devices.
● WR – It is the 31st pin in the pin diagram and a low signal in this pin represents the write operation
at the memory or I/O devices. This indicates that the data present in the data bus is to be written
into the desired memory address or I/O device by the processor.
● IO/M – It is pin number 34 and indicates the selection of a memory address or input-output device.
This shows whether the read/write operation is to be carried out at the memory location or at the
I/O device.
The low signal at this pin shows that operation is performing over memory location. As against, a high signal at
this pin represents the operation at I/O device.
● S0 and S1 – The pins S0 and S1 represent the status signal at pin number 29 and 33
respectively. These signals show the type of recent operation of the microprocessor. The table
below represents the status of the data bus under different conditions:
Machine Cycle in 8085 Microprocessor:The seven Machine Cycle in 8085 Microprocessor are :
1. Opcode Fetch Cycle
2. Memory Read
3. Memory Write
4. I/O Read
5. I/O Write
6. Interrupt Acknowledge
7. Bus Idle
1. Opcode Fetch Cycle:The first Machine Cycle of 8085 Microprocessor of every instruction is opcode fetch
cycle in which the 8085 finds the nature of the instruction to be executed. In this Machine Cycle in 8085,
processor places the contents of the Program Counter on the address lines, and through the read process, reads
the opcode of the instruction. Fig. 1.15 (a) shows flow of data (opcode) from memory to the microprocessor and
Fig. 1.15 (b) shows the timing diagram for Opcode Fetch Machine Cycle 8085. The length of this cycle is not
fixed. It varies from 4T states to 6T states as per the instruction. The following section describes the opcode fetch
cycle in step by step manner.
Step 1 : (State T1): In T1 state, the 8085 places the contents of program counter on the address bus. The
high-order byte of the PC is placed on the A8 – A15 lines. The low-order byte of the PC is placed on the AD0 –
AD7 lines which stays on only during T1. Thus microprocessor activates ALE (Address Latch Enable) which is
used to latch the low-order byte of the address in external latch before it disappears.In T1, 8085 also sends
status signals IO/M, S1, and S0. IO/M specifies whether it is a memory or I/O operation, S1 status specifies
whether it is read/write operation; S1 and S0 together indicates read, write, opcode fetch, machine cycle
operation, or whether it is in HALT state. In opcode fetch machine cycle status signals are : IO/M = 0, S1 = 1, S0
= 1.
Step 2 : (State T2) In T2, low-order address disappears from the AD0 – AD7 lines. (However A0 – A7 remain
available as they were latched during T1). In T2, 8085 sends RD signal low to enable the addressed memory
location. The memory device then places the contents of addressed memory location on the data bus (AD0 –
AD7).
Step 3 : (State T3) During T3, 8085 loads the data from the data bus in its Instruction Register and raises RD to
high which disables the memory device.
Step 4 : (State T4) In T4, microprocessor decodes the opcode, and on the basis of the instruction received, it
decides whether to enter state T5 or to enter state T1 of the next Machine Cycle of 8085 Microprocessor. One
byte instructions those operate on eight bit data (8 bit operand) are executed in T4.
For example : MOV A, B, ANA D, ADD B, INR L, DCR C, RAL and many more.
Note : For one byte instructions which operate on eight bit data, data is always available in the internal memory
of 8085 i.e. registers.
Step 5 : (State T5 and T6) State T5 and T6, when entered, are used for internal microprocessor operations
required by the instruction. During T5 and T6 , 8085 performs stack write, internal 16 bit; and conditional return
operations depending upon the type of instruction. One byte instructions those operate on sixteen bit data (16 bit
operand) are executed in T5 and T6. For example DCX H, PCHL, SPHL, INX H, etc.

2.Memory Read Cycle:

The 8085 executes the memory read cycle to read the contents of R/W memory or ROM. The length of this
machine cycle is 3-T states (T1 – T3). In this Machine Cycle in 8085, processor places the address on the
address lines from the stack pointer, general purpose register pair or program counter, and through the read
process, reads the data from the addressed memory location. Fig. 1.16 (a) shows flow of data from memory to
the microprocessor and Fig. 1.16 (b) shows the timing diagram for memory read machine cycle. Memory read
machine cycle is similar to the opcode fetch machine cycle. However, they use only states T1 to T3, and the
status signal values (IO/M = 0, S1 = 1, S0 = 0) appropriate for memory read machine cycle are issued in T1.
The following section describes the memory read machine cycle in step by step manner.
Step 1 : (State T1) In T1 state, microprocessor places the address on the address lines from stack pointer,
general purpose register pair or program counter and activates ALE signal in order to latch low-order byte of
address.
During T1, 8085 sends status signals : IO/M = 0, S1 = 1, and S0 = 0 for memory read machine cycle.
Step 2 : (State T2) In T2, 8085 sends RD signal low to enable the addressed memory location. The memory
device then places the contents of addressed memory location on the data bus (AD0 -AD7).
Step 3 : (State T3) During T3, 8085 loads the data from the data bus into specified register (F, A, B, C, D, E, H,
and L) and raises RD to high which disables the memory device.
3.Memory Write Cycle:
The 8085 executes the memory write cycle to store the data into data memory or stack memory. The length of
this machine cycle is 3T states. (T1 – T3). In this Machine Cycle of 8085 Microprocessor, processor places the
address on the address lines from the stack pointer or general purpose register pair and through the write
process, stores the data into the addressed memory location. Fig. 1.17 shows the timing diagram for memory
write machine cycle. The memory write timing diagram is similar to the memory read timing diagram, except that
instead of RD, WR signal goes low during T2 and T3. The status signals for memory write cycle are : IO/M = 0,
S1 = 0, S0 = 1. The following section describes the memory write machine cycle in step by step manner.

Step 1 : (State T1) In T1 state, the 8085 places the address on the address lines from stack pointer or general
purpose register pair and activates ALE signal in order to latch low-order byte of address. During T1, 8085 sends
status signals :
IO/M = 0, S1 = 0 and S0 = 1 for memory write machine cycle.
Step 2 : (State T2) In T2, 8085 places data on the data bus and sends WR signal low for writing into the
addressed memory location.
Step 3 : (State T3) During T3, WR signal goes high, which disables the memory device and terminates the write
operation.
4, 5. I/O Read and I/O Write cycles:
The I/O read and I/O write machine cycles are similar to the memory read and memory write machine cycles,
respectively, except that the 10/M signal is high for I/O read and I/O write machine cycles. High IO/M signal
indicates that it is an I/O operation. Fig. 1.18 (b) and Fig. 1.19 (b) show the timing diagrams for I/O read and I/O
write cycles, respectively.
6. Interrupt Acknowledge Cycle:
In response to INTR signal, 8085 executes interrupt acknowledge machine cycle to read an instruction from the
external device. Theoretically, the external device can place any instruction on the data bus in response to INTA.
However, only RST and CALL, save the PC contents (return address) before transferring control to the interrupt
service routine. The next sections explain Interrupt Acknowledge Cycle of 8085 for RST and CALL instructions.
Interrupt Acknowledge Cycle for RST instruction:

1. The INTA signal is activated instead of the RD signal.

2. The status lines (IO/M, S0 and S1) are 111 instead of 011:
 During interrupt acknowledge
machine cycle (M1), the RST is
decoded, which initiates 1 byte
CALL instruction to the specific
vector location. The machine cycles
M2 and M3 are memory write cycles
that store the contents of the
program counter on the stack, and
then a new instruction cycle begins.
Interrupt Acknowledge Cycle for
CALL instruction:
Fig. 1.21 shows the timing diagram
of the Interrupt Acknowledge Cycle
of 8085 and execution of a CALL
instruction. For CALL instruction, it is
necessary to fetch the two bytes of
the CALL address through two
additional interrupt acknowledge
machine cycles (M2 and M3 in the
1.21). The machine cycles M4 and
M5 are memory write cycles that
store the contents of the program
counter on the stack, and then a
new instruction cycle begins.
7. Bus Idle Cycle:
There are few situations where the
machine cycles are neither Read nor
Write. These situations are:
1.For execution of DAD instruction
(this instruction adds the contents of
a specified register pair to the
contents of HL register pair) ten T states are required. This means that after execution of opcode fetch machine
cycle, DAD instruction requires 6 extra T-states to add 16 bit contents of a specified register pair to the contents
of HL register pair. These extra T-states which are divided into two machine cycles do not involve any memory or
I/O operation. These Machine Cycle in 8085 are called BUS IDLE machine cycles. Fig. 1.22 shows Bus Idle
Machine Cycle of 8085 Microprocessor for DAD instruction.
In the case of DAD, these Bus Idle cycles are similar to memory read cycles, except RD and ALE signals are not
activated.
2.During internal opcode generations, for TRAP and RST interrupts, 8085 executes Bus Idle Machine Cycles.
Fig. 1.23 shows the Bus Idle Machine Cycle of 8085 Microprocessor for TRAP. In response to TRAP interrupt,
8085 enters into a Bus Idle Machine Cycle during which it invokes restart instruction, stores the contents of PC
onto the stack and places 0024H (Vector address of TRAP) onto_ the program counter.

The number of machine cycles required to fetch complete instruction depends on the instruction type :
1. One byte 2. Two byte or 3. Three byte
One byte instruction doesn’t require any additional machine cycle. Two byte instruction requires one additional
memory read machine cycle, whereas three byte instruction requires two additional memory read machine
cycles.
The number of Machine Cycle in 8085 required to execute the instruction depends on the particular instruction.
The total number of machine cycles required varies from one to five. It is possible that memory read and memory
write machine cycles occur more than once in a single instruction cycle. The following examples illustrate the
timing diagrams and machine cycles used for few 8085 instructions.
Concept of Wait States in 8085:
In some applications, speed of memory system and I/O system are not compatible with the microprocessor’s
timings. This means that they take longer time to read/write data. in such situations, the microprocessor has to
confirm whether a peripheral is ready to transfer data or not. If READY pin is high, the peripheral is ready
otherwise 8085 enters wait state.
Fig. 1.24 shows the timing diagram for memory read machine cycle with and without wait state.

Concept of Wait States in 8085 continue to be inserted as long as READY is low. After the wait state, 8085
continues with T3 of the machine cycle. During a wait state the contents of the address bus, the data bus, and
the control bus are all held constant.
The wait state then gives an addressed memory or I/O port an extra clock cycle time to output valid data on the
data bus. This feature allows to use cheaper memory or I/O devices that have longer access times.
6.Interrupts and Externally generated signals:
Interrupts are the signals that are generated to break the sequence of an ongoing operation. When an interrupt
signal is generated then CPU immediately stops its recent task under operation and switches to some other
program known as interrupt service routine (ISR).
However, after handling ISR, the CPU gets back to its main program for execution.
In the pin configuration, 5 types of interrupts are shown by 5 different pins from pin number 6 to 10. These pins
are used to manage the interrupt.
Basically, there exist 2 types of interrupts:
Maskable Interrupt and Non- maskable interrupt
Out of the 5 major interrupts 4 are the maskable interrupts. These are INTR, RST5.5, RST6.5, RST7.5 and are
easily manageable interrupts.
However, TRAP is a non-maskable interrupt and holds the topmost priority among all interrupts in the 8085
microprocessor.
● RESET IN – It is pin number 36 in the pin diagram. An active low signal at this pin resets the PC of
the microprocessor to 0. Or we can say, after resetting the PC holds its initial memory address.
● RESET OUT – It is the 3rd pin in the pin diagram. This pin generates a signal to provide
information about the resetting of the microprocessor. Also, we can say that once a processor is
reset then all the connected devices must also be reset.
So, enabling this signal shows the resetting of the interconnected devices.
● INTA: It is the 11th pin of the 8085 pin configuration. A signal at this pin acknowledges the
generated interrupt.
7.Direct Memory Access (DMA) :
We are aware of the fact that memory and I/O devices are connected with each other by the microprocessor. So,
the intermediator i.e., CPU manages the data transfer between the input-output device and memory.
However, when data in a large amount is to be transferred between I/O devices and memory the CPU gets
disabled by tri-stating its buses. And this transfer is manageable by external control circuits. The DMA has 2 pins.
● HOLD – This signal is generated at pin number 39. This pin generates a signal to notify the
processor that more than one request is present to access the data and address bus.
When this signal gets enabled, the CPU frees the bus after completion of the recent operation. Once the hold
signal gets disabled, the processor can access the bus again.
● HLDA -This signal is generated at pin number 38. This signal is enabled at the time when the
processor gets HOLD signal and it releases HLDA i.e., hold acknowledge signal. In order to show
that the multiple requests are kept on hold and will be considered once the bus gets free after the
recent operation.
After the disabling of hold request, the HLDA signal becomes low.
● READY -This is the 35th numbered pin in the pin diagram that maintains synchronization between
the processor and peripherals, memory. It is clear that a microprocessor has a much faster
response than peripherals and memory.
So, this pin is enabled when the processor as well as the peripherals and memory both become ready to begin
the next operation.
In the case when the READY pin is disabled, then the microprocessor is in the WAIT state.
Instruction Format of 8085:
Each Instruction Format of 8085 and Data Format of 8085 microprocessor has specific information fields. These
information fields of instructions are called elements of instruction. These are :
● Operation code : The operation code field in the instruction specifies the operation to be
performed. The operation is specified by binary code, hence the name operation code or
simply opcode. For example, for 8085 processor operation code for ADD B instruction is 80H.
 ● Source / destination operand : The source/destination operand field directly specifies the
source/destination operand for the instruction. In the Instruction Format of 8085, the
instruction MOV A,B has B register contents as a source operand and A register contents as a
destination operand because this instruction copies the contents of register B to register A.
● Source operand address : We know that the operation specified by the instruction may require
one or more operands. The source operand may be in the 8085 register or in the memory.
Many times the Instruction Format of 8085 specifies the address of the source operand so
that operand(s) can be accessed and operated by the 8085 according to the instruction.
In 8085, the source operand address for instruction ADD M is given by HL register pair.
● Destination operand address : The operation executed by the 8085 may produce result. Most
of the times the result is stored in one of the operand. Such operand is known as destination
operand. The Instruction and Data Format of 8085 which produce result specifies the
destination operand address. In 8085, the destination operand address for instruction INR M
is given by HL register pair because INR M instruction increments the contents of memory
location specified by HL register pair and stores the result in the same memory location.
● Next instruction address : The next instruction address tells the 8085 from where to fetch the
next instruction after completion of execution of current instruction. For BRANCH instructions
the address of the next instruction is specified within the instruction. However, for other
instructions, the next instruction to be fetched immediately follows the current instruction. For
example, in 8085, instruction after INR B follows it. The instruction JMP 2000H specifies the
next instruction address as 2000H.
Instruction Formats:
The Instruction Format of 8085 set consists of one, two and three byte instructions. The first byte is always the
opcode; in two-byte instructions the second byte is usually data; in three byte instructions the last two bytes
present address or 16-bit data.
1. One byte instruction :

For Example : MOV A, B whose opcode is 78H which is one byte. This Instruction and Data Format of 8085 copies
the contents of B register in A register.
2. Two byte instruction :

For Example : MVI B, 02H. The opcode for this instruction is 06H and is always followed by a byte data (02H in
this case). This instruction is a two byte instruction which copies immediate data into B register.
3. Three byte instruction :

For Example : JMP 6200H. The opcode for this instruction is C3H and is always followed by 16 bit address
(6200H in this case). This instruction is a three byte instruction which loads 16 bit address into program counter.
Opcode Format of 8085:
The 8085A microprocessor has 8-bit opcodes. The opcode is unique for each Instruction and Data Format of
8085 and contains the information about operation, register to be used, memory to be used etc. The 8085A
identifies all operations, registers and flags with a specific code. For example, all internal registers are identified
as shown in the Tables 2.1(a) and 2.2(b).
Similarly, there are different codes for each opera are identified as follows :

Note : DDD defines the destination register, SSS defines the source register and DD defines the register pair.
Data Format of 8085 Microprocessor:
The operand is an another name for data. It may appear in different forms :
● Addresses
● Numbers/Logical data and
● Characters
Addresses : The address is a 16-bit unsigned integer ,number used to refer a memory location.
Numbers/Data : The 8085 supports following numeric data types.
● Signed Integer : A signed integer number is either a positive number or a negative number. In
8085, 8-bits are assigned for signed integer, in which most significant bit is used for sign and
remaining seven bits are used for Sign bit 0 indicates positive number whereas sign bit 1
indicates negative number.
● Unsigned Integer : The 8085 microprocessor supports 8-bit unsigned integer.
● BCD : The term BCD number stands for binary coded decimal number. It uses ten digits from
0 through 9. The 8-bit register of 8085 can store two digit BCD
Characters : The 8085 uses ASCII code to represent characters. It is a 7-bit alphanumeric code that represents
decimal numbers, English alphabets, and other special characters.

Addressing modes in 8085 microprocessor

Addressing Modes– The term addressing modes refers to the way in which the operand of an instruction is
specified. The addressing mode specifies a rule for interpreting or modifying the address field of the instruction
before the operand is actually executed.
Addressing modes for 8086 instructions are divided into two categories:
1) Addressing modes for data
2) Addressing modes for branch
The 8086 memory addressing modes provide flexible access to memory, allowing you to easily access
variables, arrays, records, pointers, and other complex data types. The key to good assembly language
programming is the proper use of memory addressing modes.
An assembly language program instruction consists of two parts

The memory address of an operand consists of two components:

IMPORTANT TERMS
● Starting address of memory segment.
● Effective address or Offset: An offset is determined by adding any combination of three address
elements: displacement, base and index.
● Displacement: It is an 8 bit or 16 bit immediate value given in the instruction.
● Base: Contents of base register, BX or BP.
● Index: Content of index register SI or DI.
According to different ways of specifying an operand by 8086 microprocessor, different addressing modes are
used by 8086.
Addressing modes used by 8086 microprocessor are discussed below:
● Implied mode:: In implied addressing the operand is specified in the instruction itself. In this mode
the data is 8 bits or 16 bits long and data is the part of instruction.Zero address instruction are
designed with implied addressing mode.

Example: CLC (used to reset Carry flag to 0)

● Immediate addressing mode (symbol #):In this mode data is present in address field of
instruction .Designed like one address instruction format.
Note:Limitation in the immediate mode is that the range of constants are restricted by size of
address field.

Example: MOV AL, 35H (move the data 35H into AL register)
● Register mode: In register addressing the operand is placed in one of 8 bit or 16 bit general
purpose registers. The data is in the register that is specified by the instruction.
Here one register reference is required to access the data.

Example: MOV AX,CX (move the contents of CX register to AX register)

Register Indirect mode: In this addressing the operand’s offset is placed in any one of the registers BX,BP,SI,DI
as specified in the instruction. The effective address of the data is in the base register or an index register that is
specified by the instruction.
Here two register reference is required to access the data.
The 8086 CPUs let you access memory indirectly through a register using the register indirect addressing
modes.
MOV AX, [BX](move the contents of memory location s
● addressed by the register BX to the register AX)
Auto Indexed (increment mode): Effective address of the operand is the contents of a register specified in the
instruction. After accessing the operand, the contents of this register are automatically incremented to point to
the next consecutive memory location.(R1)+.
Here one register reference,one memory reference and one ALU operation is required to access the data.
Example:
Add R1, (R2)+ // OR
R1 = R1 +M[R2]
● R2 = R2 + d
Useful for stepping through arrays in a loop. R2 – start of array d – size of an element
● Auto indexed ( decrement mode): Effective address of the operand is the contents of a register
specified in the instruction. Before accessing the operand, the contents of this register are
automatically decremented to point to the previous consecutive memory location. –(R1)
Here one register reference,one memory reference and one ALU operation is required to access the
data.
Example:
Add R1,-(R2) //OR
R2 = R2-d
● R1 = R1 + M[R2]
Auto decrement mode is same as auto increment mode. Both can also be used to implement a
stack as push and pop . Auto increment and Auto decrement modes are useful for implementing
“Last-In-First-Out” data structures.Direct addressing/ Absolute addressing Mode (symbol [ ]):
The operand’s offset is given in the instruction as an 8 bit or 16 bit displacement element. In this
addressing mode the 16 bit effective address of the data is the part of the instruction.
Here only one memory reference operation is required to access the data.

Example:ADD AL,[0301] //add the contents of offset address 0301 to AL

● Indirect addressing Mode (symbol @ or () ):In this mode address field of instruction contains the
address of effective address.Here two references are required.
1st reference to get effective address.
2nd reference to access the data.
Based on the availability of Effective address, Indirect mode is of two kind:
1. Register Indirect:In this mode effective address is in the register, and corresponding
register name will be maintained in the address field of an instruction.
Here one register reference,one memory reference is required to access the data.
2. Memory Indirect:In this mode effective address is in the memory, and corresponding
memory address will be maintained in the address field of an instruction.
Here two memory reference is required to access the data.
● Indexed addressing mode: The operand’s offset is the sum of the content of an index register SI or
DI and an 8 bit or 16 bit displacement.
Example:MOV AX, [SI +05]
● Based Indexed Addressing: The operand’s offset is sum of the content of a base register BX or
BP and an index register SI or DI.
Example: ADD AX, [BX+SI]
 ● Based on Transfer of control, addressing modes are:
PC relative addressing mode: PC relative addressing mode is used to implement intra segment transfer of
control, In this mode effective address is obtained by adding displacement to PC.
EA= PC + Address field value
1. PC= PC + Relative value.
Base register addressing mode:Base register addressing mode is used to implement inter segment transfer of
control.In this mode effective address is obtained by adding base register value to address field value.
EA= Base register + Address field value.
PC= Base register + Relative value.
2. Note:
1. PC relative and based register both addressing modes are suitable for
program relocation at runtime.
2. Based register addressing mode is best suitable to write position
independent codes.
● Advantages of Addressing Modes
1. To give programmers to facilities such as Pointers, counters for loop controls, indexing of
data and program relocation.
2. To reduce the number bits in the addressing field of the Instruction.
The 8085 microprocessor has several addressing modes that are used to access memory locations. Some of
the most commonly used addressing modes in the 8085 microprocessor are:
The way of specifying data to be operated by an instruction is called addressing mode.
Why use addressing modes in 8085 microprocessor ?
Here are some reasons why addressing modes are used in the 8085 microprocessor:
● Flexibility: Addressing modes provide a flexible way to access data and instructions in memory.
Different addressing modes allow programmers to choose the most appropriate addressing
technique for a particular task, depending on the type of data being accessed, the size of the data,
and other factors.
● Memory optimization: Addressing modes can help to optimize the use of memory resources by
allowing data and instructions to be accessed in the most efficient way possible. For example,
using indirect addressing modes can reduce the amount of memory needed to store addresses,
while using indexed addressing modes can reduce the number of memory accesses needed to
access a large array of data.
● Performance optimization: Addressing modes can also help to optimize the performance of the
microprocessor by reducing the number of memory accesses needed to fetch data or instructions.
This can help to speed up the execution of programs and improve the overall efficiency of the
microprocessor.
● Reduced code size: Addressing modes can help to reduce the size of code needed to perform a
particular task. By using addressing modes that allow data and instructions to be accessed using
fewer instructions, programmers can write more compact and efficient code.
Types of addressing modes –
In 8085 microprocessor there are 5 types of addressing modes:

1. Immediate Addressing Mode –

In immediate addressing mode the source operand is always data. If the data is 8-bit, then the
instruction will be of 2 bytes, if the data is of 16-bit then the instruction will be of 3 bytes.
Examples:
MVI B 45 (move the data 45H immediately to register B)
LXI H 3050 (load the H-L pair with the operand 3050H immediately)
JMP address (jump to the operand address immediately)

2. Register Addressing Mode –

In register addressing mode, the data to be operated is available inside the register(s) and
register(s) is(are) operands. Therefore the operation is performed within various registers of the
microprocessor.
Examples:
MOV A, B (move the contents of register B to register A)
 ADD B (add contents of registers A and B and store the result in register A)
INR A (increment the contents of register A by one)

3. Direct Addressing Mode –

In direct addressing mode, the data to be operated is available inside a memory location and that
memory location is directly specified as an operand. The operand is directly available in the
instruction itself.
Examples:
LDA 2050 (load the contents of memory location into accumulator A)
LHLD address (load contents of 16-bit memory location into H-L register pair)
IN 35 (read the data from port whose address is 35)

4. Register Indirect Addressing Mode –

In register indirect addressing mode, the data to be operated is available inside a memory location
and that memory location is indirectly specified by a register pair.
Examples:
MOV A, M (move the contents of the memory location pointed by the H-L pair to the accumulator)
LDAX B (move contents of B-C register to the accumulator)
STAX B (store accumulator contents in memory pointed by register pair B-C)

5. Implied/Implicit Addressing Mode –

In implied/implicit addressing mode the operand is hidden and the data to be operated is available
in the instruction itself.
Examples:
CMA (finds and stores the 1’s complement of the contents of accumulator A in A)
RRC (rotate accumulator A right by one bit)
RLC (rotate accumulator A left by one bit)
6.Relative Addressing Mode:
In this mode, the operand is a memory location specified by the contents of the program counter plus a
constant value.
example:
MOV R0,#05H
AGAIN:
MVI A,#55H
ADD A,R0
JMP AGAIN
In this example, the instruction JMP AGAIN uses the Relative Addressing Mode. The instruction jumps to the
label AGAIN by adding the contents of the program counter with the specified constant value. The constant
value is calculated based on the distance between the current instruction and the label AGAIN.
In this case, the instruction JMP AGAIN is executing a loop that loads the accumulator with the value 55H, adds
the contents of the register R0 to the accumulator, and then jumps back to the label AGAIN to repeat the loop.

Features of the addressing modes in the 8085 microprocessor:

1. Immediate addressing: In immediate addressing mode, the operand is a constant value that is part
of the instruction. The immediate addressing mode is used for instructions that require a fixed
value, such as loading a constant value into a register.
2. Direct addressing: In direct addressing mode, the operand is a memory address specified directly
in the instruction. The direct addressing mode is used for instructions that access data stored in
memory.
3. Indirect addressing: In indirect addressing mode, the operand is a memory address specified
indirectly by a register or memory location. The indirect addressing mode is used for instructions
that access data stored in memory, where the memory address is not known in advance.
4. Register addressing: In register addressing mode, the operand is stored in one of the processor
registers. The register addressing mode is used for instructions that manipulate the contents of the
registers.
 5. Indexed addressing: In indexed addressing mode, the operand is obtained by adding an offset
value to a base address stored in a register. The indexed addressing mode is used for instructions
that access data stored in memory using a computed address.
6. Relative addressing: In relative addressing mode, the operand is specified as an offset relative to
the current program counter value. The relative addressing mode is used for instructions that
perform conditional branching or looping.
7. Memory-mapped I/O addressing: In memory-mapped I/O addressing mode, the processor
accesses input/output devices using memory addresses instead of specialized I/O instructions.
Memory-mapped I/O addressing mode is used for interfacing with peripherals such as displays,
keyboards, and printers.
Data Transfer Instructions In 8085
There are 5 types of instruction sets available in the 8085 microprocessor. Today we are going to learn about the
data transfer instructions in 8085 microprocessor.
Data transfer instructions in 8085 microprocessors are used to move data between processor registers, memory,
and I/O devices.
Data transfer instructions copied data from source to destination without modifying the contents of the source.
he various types of data transfer that are possible between direct data, registers, and memory locations are as
follows:
Sr. No Data Transfer Example

1. Between registers Register B -> Register D

2. Specific data byte to register or a memory location Data Byte -> Register B

3. Between memory location and register Memory Location -> Register A

4. Between the I/O device and the accumulator Input Device -> Register A

5. Between a register pair and the stack Register Pair data -> Stack Location

The data transfer instructions in 8085 include the following instructions:

1. MOV Rd, Rs 2. MOV R, M 3. MOV M, R

4. MVI R, data 5. MVI M, data 6. LXI Rp, 16-bit data

7. LDA address 8. STA address 9. LHLD address

10. SHLD address 11. LDAX Rp 12. STAX Rp

13. XCHG

Now, we will see each instruction which we have to describe above table in detail.
MOV Rd, Rs

Mnemonics MOV Rd, Rs

Operation Rd = Rs

No. of Bytes 1 byte

Machine Cycles 1 (OF)

 Algorithm Rd <- Rs

Flags No flags are modified

Addr. Mode Register addressing mode

T-States 4

Description This instruction copies data from the source register Rd to the destination register Rs.
The source register Rd and destination register Rs can be any general-purpose register like A,
B, C, D, E, H, or L.
The contents of the source register remain unchanged.

Example This instruction will copy the contents of register C to register B. The contents of register C
MOV C, M remain unchanged.
Example MOV B, C
Suppose B = 20H, C = 10H, and the instruction MOV B, C is executed. After the execution B
10H and C= 10H.

Machine Cycle Details:

1. Opcode Fetch: For this cycle the address given by the program counter. The program counter
places the address on the lower order address bus and the higher order address bus. The
program counter is incremented by one to point to the next instruction.
MOV R, M

Mnemonics MOV R, M

Operation R = M or R = (HL)

No. of Bytes 1 byte

Machine Cycles 2 (OF + MR)

Algorithm R <- M or R <- (HL)

Flags No flags are modified

Addr. Mode Indirect addressing mode

T-States 4+3=7

Description This instruction copied data from memory M to register R.

The term M specifies the HL memory pointer. The contents of the HL register pair are used
as the address of the memory location. The contents of that memory location are transferred
to the specified register R.
The register R can be any general-purpose register like A, B, C, D, E, H, or L.
 Example This instruction will copy the data from the memory location pointed by the HL pair to the C
MOV C, M register.
Let the contents of the HL register pair be F000H, register C = 20H. At the address F000H:
10H is stored. The HL register pair contents are used as the address i.e HL= F000H.
The contents of memory location F000H are copied to register C. So the content of the C
register will change from 20H to 10H.
The contents of the memory location remain unchanged.

Machine Cycle Details:

1. Opcode Fetch: The program counter places the address on the higher order and lower order
address bus. This cycle fetches OPCODE from program memory using a PC. The opcode is read
into the microprocessor and is decided. 4T states are required for the completion of this
operation. The PC is then incremented by 1 to point to the next instruction.
2. Memory Read: The address will be specified by the HL register pair. The data present at the
memory location pointed by the HL register pair is read into the register specified. The PC is
then incremented by one and points to the next instruction.
The example of instruction MOV R, M are:
MOV A, M MOV B, M MOV C, M MOV D, M

MOV E, M MOV L, M MOV H, M

Note:
1. Whenever the term M comes in an instruction, it is a memory pointer. The address will be given
by the HL register pair.
2. Brackets around HL specify that the contents are used as an address. Henceforth the brackets
will be used to specify the contents used ad address.
MOV M, R

Mnemonics MOV M, R

Operation M = R or (HL) = R

No. of Bytes 1 byte

Machine Cycles 2 (OF + MW)

Algorithm M <- R or (HL) <- R

Flags No flags are modified

Addr. Mode Indirect addressing mode

T-States 4+3=7

Description This instruction copied data from register R to memory M.

The term M specifies the HL memory pointer. The contents of the specified register are
copied to that memory location pointed by the HL register pair.
The register R can be any general-purpose register like A, B, C, D, E, H, or L.
The contents of the memory location remain unchanged.
 Example Let the contents of the HL pair be E200H, register C = 20H, at address E200: 10H is stored.
MOV M, C On the instruction MOV M, C the data is transferred from the C register to memory.
The contents of register C are copied to memory location E200H, so the contents of memory
location C200H will change from 10H to 20H.

Machine Cycle Details:

1. Opcode fetch: The program counter places the address on the higher order and lower order
address bus. The opcode at this memory location is read into the microprocessor. The PC is then
incremented by 1 to point to the next instruction. This machine cycle required 4T states.
2. Memory Write: This machine cycle is required for writing the data from the specified register
to a memory location that is specified by the HL register pair.
Other examples of the instruction MOV M, R is:
MOV M, A MOV M, B MOV M, C MOV M, D

MOV M, E MOV M, L MOV M, H

MVI R, Data

Mnemonics MVI R, Data

Operation R = data

No. of Bytes 2 bytes

Machine Cycles 2 (OF + MR)

Algorithm R <- data

Flags No flags are modified

Addr. Mode Immediate addressing mode

T-States 4+3=7

Description This instruction moves the 8-bit immediate data to the specified register.
The data is specified within the instruction.
It is a two-byte instruction, so the first byte of instruction will be OPCODE, and the second
byte will be 8-bit data.
The register R can be any general-purpose register like A, B, C, D, E, H, or L.

Example This instruction will load the immediate data 07H in register D.
MVI D, 07H Let the contents of register D = 10H. Then after execution of instruction MVI D, 07H the
content of register D will be changed from 10H to 07H.

Machine Cycle Details:

1. Opcode fetch: The program counter places the address on the higher order and the lower
order address bus. The opcode at this memory location is read into the microprocessor. The PC
is then incremented by 1 to point to the next byte. The machine cycles required 4T states.
2. Memory Read: The data is read from the addressed memory location into the specified
register. The PC is again incremented by one to point to the next instruction after MVI.
The example of instruction MVI R, data are:
 MVI A, data MVI B, data MVI C, data MVI D, data

MVI E, data MVI L, data MVI H, data

MVI M, data

Mnemonics MVI M, data

Operation M = data or (HL) = data

No. of Bytes 2 bytes

Machine Cycles 3 (OF + MR + MW)

Algorithm M <- data or (HL) <- data

Flags No flags are affected

Addr. Indirect addressing mode/Immediate

Mode addressing mode

T-States 4 + 3 + 3 = 10

Description This instruction moves immediate data to memory.

The HL register pair is used as a memory pointer. The contents of the HL register pair are
used as memory addresses and the immediate data is transferred to that memory location.

Example 10H is transferred to the H register.

MVI H, 10H 00H is transferred to the L register.
MVI L, 00H 20H is transferred to memory.
MVI M, 20H When the instruction MVI M, 20H is executed, the data 20H will be stored in the memory
location addressed by the HL register pair. i.e 1000H.

Machine Cycle Details:

1. Opcode Fetch: The program counter places the address on the higher order and the lower
order address bus. The opcode at this memory location is read into the microprocessor. The PC
is then incremented by 1 to point to the next byte. This machine cycle requires 4T states.
2. Memory Read: The program counter places the address on the lower and higher order
address bus. The data given within the instruction is read. PC is then incremented by one and
points to the next instruction.
3. Memory Write: HL contents will appear on the address bus. The contents of the H register
are higher order byte of the address and the contents of the L register are the lower order byte of
the address.
4. ��‾
5. WR
6. signal is generated to perform a write operation in data memory.
LXI Rp, 16-bit Data

Mnemonics LXI Rp, 16-bit data

 Operation Rp = 16-bit data

No. of Bytes 3 bytes

Machine Cycles 3 (OF + MR + MR)

Algorithm Rp <- 16-bit data

Flags No flags are affected

Addr. Mode Immediate addressing mode

T-States 4 + 3 + 3 = 10

Description This instruction will load the register pair with 16-bit data.
This instruction loads 16-bit data specified within the instruction to the specific register pair
or stack pointer.
In the instruction, only high order register is specified for the register pair. I.e if the HL pair
is to be loaded only the H register will be specified in the instruction.
The register pair Rp can be BC, DE, HL register pairs, or the stack pointer SP.

Example Load HL pair with 2030H. 20H will be loaded in the H register and 30H in the L register.
LXI H, 2030H The instruction will load stack pointer SP with 7FFFH.
LXI SP, 7FFFH

Machine Cycle Details:

1. Opcode Fetch: The program counter places the address bus on the higher order and the lower
order address bus. This cycle will fetch opcode from program memory using the PC. The PC is
then incremented by 1 to point to the next byte.
2. Memory Read: The program counter places the address on the lower order address bus and
the higher order address bus. The lower order byte is read using PC into the lower order byte of
the specified register pair. The PC is then incremented by one to point next byte.
3. Memory Read: The program counter retains the addresson the lower order address bud and
the higher order address bus. The higher order byte is read using PC into the higher order byte
of the specified register pair. The PC is then incremented by one to point to the next instruction.
The example of the instruction LXI Rp, 16-bit data are:
LXI B, 16-bit data LXI D, 16-bit data

LXI H, 16-bit data LXI SP, 16-bit data

LDA Address

Mnemonics LDA Address

Operation A = (address)

No. of Bytes 3 bytes

 Machine Cycles 4 (OF + MR + MR + MR)

Algorithm A <- (address)

Flags No flags are affected

Addr. Mode Direct addressing mode

T-States 4 + 3 + 3 + 3 = 13

Description Load accumulator direct from memory.

This instruction copies the contents of the memory location whose address is specified in the
instruction to the accumulator.
The contents of the memory location remain unchanged.

Example This instruction will load the accumulator with the contents of memory location 5820H.
LDA 5820H Let initially A = F0H, contents of memory location 5820H = 15H.
Then after the execution of instruction LDA 5820H, the accumulator will be loaded with 15H.
The content of the accumulator will change from F0H to 15H.

Machine Cycle Details:

1. Opcode Fetch: The program counter places the address on the higher order and the lower
order address bus. This cycle will fetch Opcode from program memory using a PC. The PC is
then incremented by 1 to point to the next byte.
2. Memory Read: The program counter places the address on the lower order address bus and
the higher order address bus. The lower-order byte of the address specified is read using a PC.
The PC is then incremented by one to point to the next byte.
3. Memory Read: The program counter places the address on the lower order address bus and
the higher order address bus. The higher-order byte of the address is read using a PC. The PC is
then incremented by one to point to the next instruction.
4. Memory Read: This machine cycle is used for reading the data into the accumulator from the
addressed memory location. The address for this is given by the above 2 memory read cycles
that have taken the higher and lower order address.
STA Address

Mnemonics STA Address

Operation (address) = A

No. of Bytes 3 bytes

Machine Cycles 4 (OF + MR + MR + MW)

Algorithm (address) <- A

Flags No flags are affected

Addr. Mode Direct addressing mode

 T-States 4 + 3 + 3 + 3 = 13

Description Store accumulator direct to memory.

his instruction will store the contents of the accumulator to the memory location specified in
the instruction.
The contents of the memory location remain unchanged.
It is a 3-byte instruction. The first byte is the opcode, the second byte is the lower-order
address and the third byte is the higher-order address.

Example This instruction will store the contents of the accumulator at location 5820H.
LDA 5820H

Machine Cycle Details:

1. OPCODE fetch: The program counter places the address on the higher order and the lower
order address bus. This cycle will fetch OPCODE from program memory using a PC. The PC is
then incremented by 1 to point to the next byte. The opcode of this instruction is 32 H.
2. Memory read: The program counter places the address on the lower order address bus and
the higher order address bus. The lower-order byte of the address specified is read using a PC.
The PC is then incremented by one to point to the next byte.
3. Memory read: The program counter retains the address on the lower order address bus and
the higher order address bus. The higher-order byte of the address is read using a PC. The PC is
then incremented by one to point to the next instruction.
4. Memory write: This machine cycle is used for writing the data from the accumulator to the
addressed memory location. The address for this is given by the above 2 memory read cycles
that have taken the higher and lower order address.
LHLD Address

Mnemonics LHLD Address

Operation L = (address)
H = (Address + 1)

No. of Bytes 3 bytes

Machine Cycles 5 (OF + MR + MR + MR + MR)

Algorithm L <- (address)

H <- (address + 1)

Flags No flags are affected

Addr. Mode Direct addressing mode

T-States 4 + 3 + 3 + 3 + 3 = 16
 Description Load HL pairs directly from memory.
This instruction loads the contents of the memory location to the H and L registers. The
address of memory is specified along with the instruction.
The contents of the memory location whose address is specified in the instruction are
transferred to the L register and the contents of the next memory location i.e. (address + 1)
to the H register.
This instruction is used to load the H and L registers from memory.
It is a 3-byte instruction. The first byte is the opcode, the second byte is the lower-order
address and the third byte is the higher-order address.

Example Load HL pair from memory locations 4000H and 4001H.

LHLD 4000H Let H = 05 H, L = 04 H, at memory locations 4000 H and 4001 H the data 20H, 30H is
stored.
The instruction LHLD will load the contents of memory location 4000 H to the L register,
and the contents of memory location 4001 H to the H register.
So the contents of register L will change from 04 to 20 H and the contents of register H will
change from 05 H to 30 H.

Machine Cycle Details:

1. OPCODE fetch: The program counter places the address on the lower order address bus and
the higher order address bus. This cycle is used to read the OPCODE of LHLD instruction. The
opcode of the LHLD instruction is 2A H. The address for this machine cycle is given by PC. The
PC is then incremented by 1 to point to the next byte.
2. Memory read: The program counter places the address on the lower order address bus and
the higher order address bus. The lower-order byte of the address specified is read using a PC.
The PC is then incremented by one to point to the next byte.
3. Memory read: The program counter retains the address on the lower order address bus and
the higher order address bus. The higher-order byte of the address is read using a PC. The PC is
then incremented by one to point to the next instruction.
4. Memory read: It is used to read data from the addressed memory. This data will be stored in
the L register. The address for this is given by the above 2 memory reads. This address will be
incremented by 1.
5. Memory read: It is used to read data from addressed memory. This data will be stored in the
H register.
SHLD Address

Mnemonics SHLD Address

Operation (address) = L register

(Address + 1) = H register

No. of Bytes 3 bytes

Machine Cycles 5 (OF + MR + MR + MW + MW)

Algorithm (address) <- L

(address + 1) <- H

Flags No flags are affected

Addr. Mode Direct addressing mode

 T-States 4 + 3 + 3 + 3 + 3 = 16

Description Store HL pair to memory locations 4000 and 4001.

Let H = 05H, L = 04H, at memory locations 4000H and 4001H the data 20H and 30H is
stored and the instruction SHLD 4000H has executed the contents of register L are copied to
memory location 4000H and contents of register H are copied to memory location 4001H.

Example Store HL pair to memory locations 4000 and 4001.

SHLD 4000H Let H = 05H, L = 04H, at memory locations 4000H and 4001H the data 20H and 30H is
stored and the instruction SHLD 4000H has executed the contents of register L are copied to
memory location 4000H and contents of register H are copied memory location 4001H.

Machine Cycle Details:

1. OPCODE fetch: The program counter places the address on the lower order address bus and
the higher order address bus. This cycle is used to read the OPCODE of SHLD instruction. The
opcode of the SHLD instruction is 22 H. The address for this machine cycle is given by PC. The
PC is then incremented by 1 to point to the next byte.
2. Memory read: The program counter places the address on the lower order address bus and
the higher order address bus. The lower-order byte of the address specified is read using a PC.
The PC is then incremented by one to point to the next byte.
3. Memory read: The program counter retains the address on the lower order address bus and
the higher order address bus. The higher-order byte of the address is read using a PC. The PC is
then incremented by one to point to the next instruction.
4. Memory write: It is used to write data i.e. contents of the L register to the addressed memory.
The address for this is given by the above 2 memory reads. This address will be incremented by
1.
5. Memory write: It is used to write data in the H register to address the memory. This data will
be stored at the memory location with incremented address.
LDAX Rp

Mnemonics LDAX Rp

Operation A = (Rp)

No. of Bytes 1 byte

Machine Cycles 2 (OF + MR)

Algorithm A <- (Rp)

Flags No flags are affected

Addr. Mode Indirect addressing mode

T-States 4+3=7
 Description Load accumulator indirectly by using a memory pointer.
This instruction copies the contents of the memory location to the accumulator.
The address of memory location is given by R, register pair specified along with the
instruction.
The register pair Rp can be BC or DE only.
The contents of the memory location remain unchanged.

Example This instruction will load the accumulator with the contents of the memory location whose
LDAX B address is given by the BC register pair.
Let A = 1F H, B = 20H, C = 25H, at memory location 2025 : 56H is stored.
Then after the execution of instruction LDAX B, the accumulator will be loaded with the
contents of memory location 2025 i.e. 56 H.

Machine Cycle Details:

1. OPCODE fetch: The program counter places the address on the higher order and the lower
order address bus. This cycle will fetch OPCODE (e.g. 0A H for LDAX B) from program memory
using PC. The PC is then incremented by 1 to point to the next instruction.
2. Memory read: The address will be specified by the register pair. The data present at the
memory location pointed by the specified register pair is read into the accumulator. In this
machine cycle the higher order register contents are placed on the higher order address bus and
lower order register contents are placed on the lower order address bus.
The example of instruction LDAX Rp are:
1. LDAX B 2. LDAX D

STAX Rp

Mnemonics STAX Rp

Operation (Rp) = A

No. of Bytes 1 byte

Machine Cycles 2 (OF + MW)

Algorithm (Rp) <- A

Flags No flags are affected

Addr. Mode Indirect addressing mode

T-States 4+3=7

Description Store accumulator indirectly by using a memory pointer.

This instruction copies the contents of the accumulator to memory location.
The address of the memory location is given by the Rp register pair specified in the
instruction.
The register pair Rp can be a valid register pair like BC or DE only.
The contents of the accumulator remain unchanged.
 Example Store accumulator indirectly by using a memory pointer.
STAX B This instruction copies the contents of the accumulator to the memory location.
The address of the memory location is given by the Rp register pair specified in the
instruction.
The register pair Rp can be a valid register pair like BC or DE only.
The contents of the accumulator remain unchanged.

Machine Cycle Details:

1. OPCODE fetch: The program counter places the address on the higher order and the lower
order address bus. This cycle will fetch OPCODE from program memory using a PC. The PC is
then incremented by 1 to point to the next instruction.
2. Memory write: Higher order address is obtained from higher order register and lower order
address is obtained from lower order register. The contents of the accumulator are stored in the
addressed memory location. Thus, this machine cycle is required for writing the data from the
accumulator to the memory location that is pointed by the specified register pair.
The example of instruction LDAX Rp are:
1. STAX B 2. STAX D

XCHG

Mnemonics XCHG

Operation H <-> D, L <-> E

No. of Bytes 1 byte

Machine Cycles 1 (OF)

Algorithm H <-> D, L <-> E

Flags No flags are affected

Addr. Mode Register addressing mode

T-States 4

Description Exchange the contents of HL with DE pair.

This instruction exchanges the contents of the H register with the D register and the L
register with the E register.

Example Let H = 12H, L = 11H, D = 30H, E executed. 40H and the instruction XCHG is executed.
XCHG

Machine Cycle Details:

1. OPCODE fetch: For this cycle, the address is given by the program counter. The program
address counterlaces the lower order on the address bus and the higher order address bus. The
program counter is incremented by one, to point to the next instruction.
Arithmetic Operations
The 8085 microprocessor performs various arithmetic operations, such as addition, subtraction, increment, and
decrement. These arithmetic operations have the following mnemonics.
INTRODUCTION TO 8085 ARITHMETIC INSTRUCTIONS
ADD: Add Add the contents of a register.
 ADI: Add Immediately Add 8-bit data.

SUB: Subtract Subtract the contents of a register.

SUI: Subtract Immediately Subtract 8-bit data.

INR: Increment Increase the content of register by1.

DCR: Decrement Decrease the content of register by1.

The arithmetic operations ADD and Subtract are performed in relation to the contents of the accumulator.
However, the Increment or the Decrement operations can be performed in any register. The instructions for these
operations are explained below:
INSTRUCTIONS
These arithmetic instructions(except INR and DCR)
1. assume implicitly that the accumulator is one of the operands.
2. modify all the flags according to the data conditions of the result.
3. place the result in the accumulator.
4. do not affect the contents of the operand register.
The instructions INR and DCR
1. affects the content of the specified register.
2. affect all flags expect the CY flag.
The descriptions of the instructions (including INR and DCR) are as follows:
Opcode Operand Description

ADD
■ This is 1-byte instructions.
ADD R
■ Adds the contents of register R to the contents of the
accumulator.

Add Immediately
■ This is 2-byte instructions.
ADI 8-bit
■ Adds the second byte to the contents of the
accumulator

Subtract
■ This is 1-byte instructions.
SUB R+
■ Subtract the contents of register R from the contents of
the accumulator.

Subtract Immediately
■ This is 2-byte instructions.
SUI 8-bit
■ Subtracts the byte from the contents of the
accumulator.

Increment
■ This is 1-byte instructions.
INR R*
■ Increases the contents of register R by 1
Caution: All flags except the CY are affected
 Decrement
■ This is 1-byte instructions.
DCR R*
■ Decreases the contents of register R by 1
Caution: All flags except the CY are affected.

Logical instructions in 8085 microprocessor

Introduction :
Logical instructions in the 8085 microprocessor are a set of instructions that perform logical operations on data
in registers and memory. Logical operations are operations that manipulate the bits of data without affecting
their numerical value. These operations include AND, OR, XOR, and NOT.
The logical instructions in the 8085 microprocessor include:
1. ANA – Logical AND: This instruction performs a logical AND operation between the accumulator
and a specified register or memory location, and stores the result in the accumulator. For example,
the instruction “ANA B” performs a logical AND operation between the contents of the
accumulator and the contents of the B register.
2. ORA – Logical OR: This instruction performs a logical OR operation between the accumulator and
a specified register or memory location, and stores the result in the accumulator. For example, the
instruction “ORA C” performs a logical OR operation between the contents of the accumulator and
the contents of the C register.
3. XRA – Logical XOR: This instruction performs a logical XOR operation between the accumulator
and a specified register or memory location, and stores the result in the accumulator. For example,
the instruction “XRA M” performs a logical XOR operation between the contents of the
accumulator and the contents of the memory location pointed to by the HL register.
4. CPL – Logical Complement: This instruction performs a logical complement operation on the
contents of the accumulator. This operation flips all the bits of the accumulator, effectively
reversing its value.
5. CMA – Complement Accumulator: This instruction performs a bitwise complement operation on
the contents of the accumulator. This operation flips all the bits of the accumulator, effectively
reversing its value.
Logical instructions are the instructions that perform basic logical operations such as AND, OR, etc. In the 8085
microprocessor, the destination operand is always the accumulator. Here logical operation works on a bitwise
level.

Why use Logical instructions in 8085 microprocessor ?

Here are some specific reasons why logical instructions are used in the 8085 microprocessor:
1. Data comparison: Logical instructions can be used to compare two pieces of data bit-by-bit. For
example, the XOR instruction can be used to compare the contents of two registers or memory
locations and set a flag if they are not equal.

OPCODE OPERAND DESTINATION EXAMPLE

ANA R A = A AND R ANA B

ANA M A = A AND Mc ANA 2050

ANI 8-bit data A = A AND 8-bit data ANI 50

ORA R A = A OR R ORA B

ORA M A = A OR Mc ORA 2050

ORI 8-bit data A = A OR 8-bit data ORI 50

XRA R A = A XOR R XRA B

XRA M A = A XOR Mc XRA 2050

XRI 8-bit data A = A XOR 8-bit data XRI 50

CMA none A = 1’s complement of A CMA

CMP R Compares R with A and triggers the flag register CMP B

Compares Mc with A and triggers the flag

CMP M CMP 2050
register

Compares 8-bit data with A and triggers the flag

CPI 8-bit data CPI 50
register
RRC none Rotate accumulator right without carry RRC

RLC none Rotate accumulator left without carry RLC

RAR none Rotate accumulator right with carry RAR

RAL none Rotate accumulator left with carry RAR

CMC none Compliments the carry flag CMC

STC none Sets the carry flag STC

2. Data masking: Logical instructions can be used to selectively mask or extract specific bits of data.
For example, the AND instruction can be used to mask off all but a specific set of bits, while the
OR instruction can be used to set specific bits to 1.
3. Data encryption: Logical instructions can be used to perform bitwise encryption of data. By
performing a logical XOR between the data and a secret key, the data can be encrypted in a
reversible way that can only be decrypted with the same key.
4. Decision-making: Logical instructions can be used to make decisions in programs. For example, the
AND instruction can be used to test if multiple conditions are true, while the OR instruction can be
used to test if at least one condition is true.
Following is the table showing the list of logical instructions: In the table,
R stands for register
M stands for memory
Mc stands for memory contents

Applications :
Data processing: The logical instructions in the 8085 microprocessor are used to manipulate and process data
stored in memory or registers. These instructions are used to perform various logical operations, such as AND,
OR, XOR, and complement, which are used to filter, mask, and manipulate data in various ways.
Control systems: The logical instructions are used in control systems to perform logical operations on sensor
data and other inputs. These operations are used to generate control signals that regulate the behavior of the
system.
Signal processing: The logical instructions in the 8085 microprocessor are used in digital signal processing
applications, such as audio and image processing. These instructions are used to perform various logical
operations on the digital signal data, such as masking, filtering, and thresholding.
Communication systems: The logical instructions are used in communication systems to perform logical
operations on data, such as error detection and correction, and encryption/decryption.
Gaming: The logical instructions are used in gaming applications to perform logical operations on game data,
such as collision detection, pathfinding.
Branching instructions
Branching instructions refer to the act of switching execution to a different instruction sequence as a result of
executing a branch instruction.
The three types of branching instructions are:

1. Jump (unconditional and conditional)

2. Call (unconditional and conditional)

3. Return (unconditional and conditional)

1. Jump Instructions – The jump instruction transfers the program sequence to the memory address given in the
operand based on the specified flag. Jump instructions are 2 types: Unconditional Jump Instructions and
Conditional Jump Instructions.
(a) Unconditional Jump Instructions: Transfers the program sequence to the described memory address.

OPCODE OPERAND EXPLANATION EXAMPLE

JMP address Jumps to the address JMP 2050

(b) Conditional Jump Instructions: Transfers the program sequence to the described memory address only if
the condition in satisfied.

OPCODE OPERAND EXPLANATION EXAMPLE

JC address Jumps to the address if carry flag is 1 JC 2050

JNC address Jumps to the address if carry flag is 0 JNC 2050

JZ address Jumps to the address if zero flag is 1 JZ 2050

JNZ address Jumps to the address if zero flag is 0 JNZ 2050

JPE address Jumps to the address if parity flag is 1 JPE 2050

 JPO address Jumps to the address if parity flag is 0 JPO 2050

JM address Jumps to the address if sign flag is 1 JM 2050

JP address Jumps to the address if sign flag 0 JP 2050

2. Call Instructions – The call instruction transfers the program sequence to the memory address given in the
operand. Before transferring, the address of the next instruction after CALL is pushed onto the stack. Call
instructions are 2 types: Unconditional Call Instructions and Conditional Call Instructions.
(a) Unconditional Call Instructions: It transfers the program sequence to the memory address given in the
operand.

OPCODE OPERAND EXPLANATION EXAMPLE

CALL address Unconditionally calls CALL 2050

(b) Conditional Call Instructions: Only if the condition is satisfied, the instructions executes.

OPCODE OPERAND EXPLANATION EXAMPLE

CC address Call if carry flag is 1 CC 2050

CNC address Call if carry flag is 0 CNC 2050

CZ address Calls if zero flag is 1 CZ 2050

CNZ address Calls if zero flag is 0 CNZ 2050

CPE address Calls if parity flag is 1 CPE 2050

 CPO address Calls if parity flag is 0 CPO 2050

CM address Calls if sign flag is 1 CM 2050

CP address Calls if sign flag is 0 CP 2050

3. Return Instructions – The return instruction transfers the program sequence from the subroutine to the
calling program. Return instructions are 2 types: Unconditional Jump Instructions and Conditional Jump
Instructions.
(a) Unconditional Return Instruction: The program sequence is transferred unconditionally from the subroutine
to the calling program.

OPCODE OPERAND EXPLANATION EXAMPLE

RET none Return from the subroutine unconditionally RET

(b) Conditional Return Instruction: The program sequence is transferred unconditionally from the subroutine to
the calling program only is the condition is satisfied.

OPCODE OPERAND EXPLANATION EXAMPLE

RC none Return from the subroutine if carry flag is 1 RC

RNC none Return from the subroutine if carry flag is 0 RNC

RZ none Return from the subroutine if zero flag is 1 RZ

RNZ none Return from the subroutine if zero flag is 0 RNZ

RPE none Return from the subroutine if parity flag is 1 RPE

 RPO none Return from the subroutine if parity flag is 0 RPO

RM none Returns from the subroutine if sign flag is 1 RM

RP none Returns from the subroutine if sign flag is 0 RP

Advantages:
Enables conditional execution: The branching instructions in the 8085 microprocessor allow for conditional
execution of code, which can help optimize program flow and improve overall efficiency.
Simplifies programming: The branching instructions in the 8085 microprocessor simplify programming by
providing a set of dedicated instructions for branching to different memory locations based on conditions.
Supports a wide range of operations: The branching instructions in the 8085 microprocessor support a wide
range of operations, including conditional branching, unconditional branching, and subroutine calls.
Allows for loop execution: The branching instructions in the 8085 microprocessor can be used to implement
loops by branching to a memory location that contains a loop instruction.

Disadvantages:
Limited branching range: The 8085 microprocessor has a limited branching range, which can restrict the
amount of memory that can be accessed. This can be a disadvantage for applications that require a large
number of branching instructions.
Limited number of condition codes: The 8085 microprocessor has a limited number of condition codes, which
can restrict the types of conditions that can be tested.
Complex addressing modes: The addressing modes used in the branching instructions can be complex, which
can make programming more difficult.
Limited instruction set: The 8085 microprocessor has a limited instruction set, which can limit the types of
branching instructions that can be used. This can be a disadvantage for applications that require complex
program flow.

Interrupts in 8085 Microprocessor

Whenever more than one I/O device is connected to a microprocessor-based system, any one of the I/O devices
may ask for service at any time. There are two methods by which the microprocessor can service these I/O
devices.
1. Polling Routine
2. Interrupts
Polling Routine
The Polling routine is a simple program that keeps a check on the occurrences of interrupts.
The polling routine will first transfer the status of the I/O port to the accumulator and then checks the content of
the accumulator to determine if the service request bit is set.
If the bit is set then the I/O port service routine is called
Interrupts
An interrupt is an external asynchronous input that informs the microprocessor to complete the instruction that
is currently executing and fetch a new routine in order to offer service to the I/O device.
Once the I/O device is serviced, the microprocessor will continue with the execution of its normal program.
Table of Contents
Basic Definitions of Interrupts
Types of Interrupts in 8085
Hardware Interrupts in 8085
Interrupt Vector Location
Software Interrupts in 8085
 Comparison of Hardware interrupts and Software interrupts
Masking or unmasking of Interrupts in 8085
1. EI : Enable Interrupt
2. DI : Disable Interrupt
3. SIM : Set Interrupt Mask
4. RIM : Read Interrupt Mask
Basic Definitions of Interrupts
1. Interrupts: It is a mechanism by which an I/O device ( hardware interrupts) or an instruction
(software interrupts) can suspend the normal execution of the processor and get itself serviced.
2. Interrupt Service routine (ISR): A small program or a routine that when executed services
the corresponding interrupting source is called an ISR.
3. Vectored/Non-vectored Interrupts: If the ISR address of an interrupt is to be taken from
the interrupting source itself, it is called a non-vectored interrupt, else it is a vectored interrupt.
4. Maskable/Non-maskable Interrupt: In cases where an interrupt is masked, the
microprocessor will not respond to the interrupt even is the interrupt is activated. The interrupt
which can be masked under the software control is called as maskable Interrupt. The interrupts
which cannot be masked under the software control are called non-maskable interrupts.
Types of Interrupts in 8085
There are two types of interrupts in the 8085 microprocessor. They are:
1. Hardware Interrupts:
● The peripheral device activates the interrupt by activating the respective pin.
● In response to the interrupting request, the microprocessor completes the current
instruction execution in the main program and transfers program control to the
interrupt service routine.
● In the ISR routine, the task is completed. The task may be to read data, write data,
upload the status, update the counter, etc.
● After completing the task, the program control is transferred back to the main
program.
● These types of interrupts where the microprocessor pins are used to receive
interrupt requests are called Hardware Interrupts.
● The 8085 Microprocessor has five hardware interrupts.
1. TRAP
2. RST 7.5
3. RST 6.5
4. RST 5.5
5. INTR
2. Software Interrupts:
● In the case of software interrupts, the cause of the interrupt is the execution of the
instruction.
● The 8085 microprocessor has eight instructions. These eight instructions are RST
0 to RST 7.
● Such interrupts are called software interrupts.
● They allow microprocessors to transfer program control from the main program
to the subroutine program.
● After completing the subroutine program. the program control returns back to the
main program.
Also Read: Instruction Set of 8085 Microprocessor
Hardware Interrupts in 8085
1. TRAP :
● It is a non-maskable, edge and level-triggered interrupt.
● It is unaffected by any mask or interrupt enable.
● The TRAP signal must make a LOW to HIGH transition and remain HIGH until acknowledge.
This avoids false triggering due to noise or glitches.
● It has the highest priority among all interrupts.
● This interrupt transfers the microprocessor’s control to location 0024H.
● Application: It is used for emergency purposes like power failure, parity error checker, smoke
detector, etc.
2. RST 7.5 :
● It is a maskable, edge-triggered interrupt request input line. This interrupt is triggered at the
rising edge of the signal.
● It has the highest priority among all maskable interrupts and the second priority among all
interrupts.
● The interrupt vector location for this interrupt is 003CH.
3. RST 6.5 and RST 5.5 :
● These are level-triggered, maskable interrupt request input lines.
● RST 6.5 transfer the microprocessor’s control to location 0034H while RST 5.5 transfer the
microprocessor’s control to location 002CH.
4. INTR :
●It is a level triggered, maskable interrupt request input line.
●This interrupt works in conjunction with RST N or CALL instruction.
●The INTR logic consists of an INTE flip-flop, OR gate, and inverter. The INTR pin is logically
ANDed with the output of the INTE flip-flop.
Interrupt Vector Location
Interrupt ISR address (Vector Trigger Priority Maskable Vectored
Type Location)

TRAP 0024 H Edge and 1st NO YES

Level (Highest)

RST 7.5 003C H Level 2nd YES YES

RST 6.5 0034 H Level 3rd YES YES

RST 5.5 002C H Level 4th YES YES

INTR No specific location Level 5th YES NO

(Lowest)

Hardware Interrupt Vector Location

Software Interrupts in 8085
● The 8085 microprocessor has eight instructions from RST 0 to RST 7.
● These instructions allow the transfer of program control from the main program to predefined
service routine addresses.
● A predefined service routine is also referred to as ISR.
● After completing the ISR program control is transferred back to the main program.
● 8085 microprocessor provides eight software interrupts RST 0 to RST 7; These instructions are
used to call interrupt service routine.
● Format of RST N Instruction OPCODE is as follows:
D7 D6 D5 D4 D3 D2 D1 D0

1 1 N2 N1 N0 1 1 1

● The vector locations, for RST N instruction, are as follows:

Instruction Address of ISR

RST 0 0000H (8 X 0 ) = 0000H

RTS 1 0008H (8 X 1 ) = 0008H

RST 2 0010H (8 X 2 ) = 0010H

RST 3 0018H (8 X 3 ) = 0018H

RST 4 0020H (8 X 4 ) = 0020H

RST 5 0028H (8 X 5 ) = 0028H

RST 6 0030H (8 X 6 ) = 0030H

RST 7 0038H (8 X 7 ) = 0038H

 ●The difference between two successive locations is only 8 bytes. Hence jump instructions must
be stored in the corresponding location to transfer the microprocessors’ control to the
user-defined ISR address.
● Software interrupts are not used to handle asynchronous events. They are used to call software
routines like single steps, breakpoints, etc.
Comparison of Hardware interrupts and Software interrupts
Sr. Software Interrupt Hardware Interrupt
No

1. It is a synchronous event. It is an asynchronous event.

2. This interrupt is requested by executing instruction. This interrupt is requested by an external

device on a pin.

3. PC in incremented. PC is not incremented.

4. The microprocessor does not execute any interrupt The microprocessor executes either
acknowledge cycle to acknowledge this interrupt. The interrupt acknowledge cycle bus or idle
microprocessor executes a normal instruction cycle. machine cycle to acknowledge this interrupt.

5. It cannot be ignored or masked. It can be masked except for TRAP.

6. It has the highest priority among all interrupts. The priority is lower than that of a software
interrupt.

7. It does not affect interrupt control logic. It affects interrupt control logic.

8. It is not used to interface peripherals that means it It is used to interface peripherals in

does not improve the throughput of the system. It is interrupt-driven I/O. It improves the
used in program debugging. throughput of the system.

Masking or unmasking of Interrupts in 8085

For masking/unmasking of interrupts, there are four instructions:
1. EI
2. DI
3. RIM
4. SIM
1. EI : Enable Interrupt
● This instruction s used to enable all maskable interrupts. i.e interrupts RST 7.5, RST 6.5, RST
5.5 and INTR can be enabled/activated using the EI instruction.
● Whenever an interrupt is acknowledged, the interrupt enable flip-flop will reset and all the
interrupts ae disabled.
● If the interrupts are to be enabled, then the EI instruction is to be executed within the ISR.
2. DI : Disable Interrupt
● This instruction resets the interrupt enable flip-flop i.e it can be used to disable RST 7.5, RST
6.5, RST 5.5 and INTR interrupts.
3. SIM : Set Interrupt Mask
● This instrction is used to enable/disable the RST 7.5, RST 6.5 and RST 5.5 interrupts.
● This instruction does not affect on the TRAP and INTR inputs.
● It ccan also be used for serial data transmission.
● It transfer the control word from accumulator to the interrupt control logic, and the serial
control logic.
● So, it is essential to load the control word into the accumulator before the xecution of SIM
instruction.
SIM Formate
● Bits D7 and D6 are serial port control. The SDE is enable bit used to enable/disable serial output
data. If D6 bit is enables, D7 bit is transferred to SOD pin.
● Bit D4 is R 7.5 part of interrupt control logic. It is used to reset R 7.5 flip-flop regardless of RST
7.5 masking.
● Bits D3 and D0 are partof interrupt control logic. These bits are used to mask RST 5.5, RST 6.5
and RST 7.5 interupts.
● The MSE bit is master control over M 7.5, M 6.5 abd M 5.5 bits. If MSE = 0, the M bits have no
effect, but if MSE=1, the M bits decides mask or unmask of respective interrupts.
4. RIM : Read Interrupt Mask
● This instruction is used to check the status of all pending and maskable interrupts.
● It can also transfer serial data bit from the serial input data line to the D7 bit of the accumulator.
● This instruction transfer the contents of the interrupt control logic and seria control logic to the
accumulator. Hence accumulator is loaded with the status fprate after execution of the RIM
instruction.
● At a time there can be more than one interrupt request may occur. In such cases if the priority of
interrputs is higher then they are serviced.
● The programmer can monitor the status of these pendinginterrupts using RIM instruction.

RIM Formate
● Bit D7 is status of SID pin on serial port. When RIm instruction is ecexuted the logic level of SID
pin is copied at bit D7.
● Bits D6, D5 and D4 are status of pending interrupts.
● Bits D3 to D0 are status of interrupt enable flip-flop, mask 7.5, mask 6.5 and mask 5.5. When
RIm instruction is executed the status of masking is loaded at bit D3 to D0.
Programming in 8085
Let's see some simple example to demonstrate the use of some important instructions of 8085.

The memory addresses given in the program are for a particular microprocessor kit. These addresses can be
changed to suit the microprocessor kit available in your system.

Store 8-bit data in memory

Program

Store 8-bit data in memory using direct addressing

1. MVI A, 49H : "Store 49H in the accumulator"

2. STA 2501H : "Copy accumulator contents at address 2501H"

3. HLT : "Stop"

Store 8-bit data in memory using indirect addressing

1. LXI H : "Load H-L pair with 2501H"

2. MVI M : "Store 49H in memory location pointed by H-L register pair (2501H)"

3. HLT : "Stop"

Add two 8-bit numbers

Example
(2501 H) = 99H
(2502 H) = 39H
Result (2503 H) = 99H + 39H = D2H
Since,
1 0 0 1 1 0 0 1 (99H)
+ 0 0 1 1 1 0 0 1 (39H)
1 1 0 1 0 0 1 0 (D2H)

Program

1. LXI H, 2501H : "Get address of first number in H-L pair. Now H-L points to 2501H"
2. MOV A, M : "Get first operand in accumulator"
3. INX H : "Increment content of H-L pair. Now, H-L points 2502H"
4. ADD M : "Add first and second operand"
5. INX H : "H-L points 4002H"
6. MOV M, A : "Store result at 2503H"

7. HLT : "Stop"

Subtract two 8-bit numbers

Example
(2501 H) = 49H
(2502 H) = 32H
Result (2503 H) = 49H - 32H = 17H

Program

1. LXI H, 2501H : "Get address of first number in H-L pair. Now H-L points to 2501H"
2. MOV A, M : "Get first operand in accumulator"
3. INX H : "Increment content of H-L pair. Now, H-L points 2502H"
4. SUB M : "Subtract first to second operand"
5. INX H : "H-L points 4002H"
 6. MOV M, A : "Store result at 2503H"

7. HLT : "Stop"

Add two 16-bits numbers

Add the 16-bit number in memory locations 2501H and 2502H to the 16-bit number in memory locations 2503H
and 2504H. The most significant eight bits of the two numbers to be added are in memory locations 2502H and
4004H. Store the result in memory locations 2505H and 2506H with the most significant byte in memory location
2506H.

Example
(2501H) = 15H
(2502H) = 1CH
(2503H) = B7H
(2504H) = 5AH

Result = 1C15 + 5AB7H = 76CCH

(2505H) = CCH
(2506H) = 76H

Program

Add two 16-bits number with ADD and ADC instruction

1. LHLD 2501H : "Get 1st 16-bit number in H-L pair"

2. XCHG : "Save 1st 16-bit number in DE"
3. LHLD 2503H : "Get 2nd 16-bit number in H-L pair"
4. MOV A, E : "Get lower byte of the 1st number"
5. ADD L : "Add lower byte of the 2nd number"
6. MOV L, A : "Store result in L-register"
7. MOV A, D : "Get higher byte of the 1st number"
8. ADC H : "Add higher byte of the 2nd number with CARRY"
9. MOV H, A : "Store result in H-register"
10. SHLD 4004H : "Store 16-bit result in memory locations 2505H and 2506H"

11. HLT : "Stop"

Add two 16-bits numbers with DAD instruction

1. LHLD 2501H : "Get 1st 16-bit number"

2. XCHG : "Save 1st 16-bit number in DE"
3. LHLD 2503H : "Get 2nd 16-bit number in H-L"
4. DAD D : "Add DE and HL"
5. SHLD 2505H : "Store 16-bit result in memory locations 2505H and 2506H".

6. HLT : "Stop"

Subtract two 16-bit numbers

Example
(2500H) = 19H
(2501H) = 6AH
(2504H) = 15H (2503H) = 5CH
Result = 6A19H ? 5C15H = OE04H
(2504H) = 04H
(2505H) = OEH
 1. LHLD 2500H : "Get first 16-bit number in HL"
2. XCHG : "Save first 16-bit number in DE"
3. LHLD 2502H : "Get second 16-bit number in HL"
4. MOV A, E : "Get lower byte of the first number"
5. SUB L : "Subtract lower byte of the second number"
6. MOV L, A : "Store the result in L register"
7. MOV A, D : "Get higher byte of the first number"
8. SBB H : "Subtract higher byte of second number with borrow"
9. MOV H, A : "Store l6-bit result in memory locations 2504H and 2505H"
10. SHLD 2504H : "Store l6-bit result in memory locations 2504H and 2505H"

11. HLT : "Terminate program execution"

Add contents of two memory locations

Example
(2500H) = 7FH
(2501H) = 89H
Result = 7FH + 89H = lO8H
(2502H) = 08H
(2503H) = 01H

Program

1. LXI H, 2500H : "HL Points 2500H"

2. MOV A, M : "Get first operand"
3. INX H : "HL Points 2501H"
4. ADD M : "Add second operand"
5. INX H : "HL Points 2502H"
6. MOV M, A : "Store the lower byte of result at 2502H"
7. MVIA, 00 : "Initialize higher byte result with 00H"
8. ADC A : "Add carry in the high byte result"
9. INX H : "HL Points 2503H"
10. MOV M, A : "Store the higher byte of result at 2503H"

11. HLT : "Terminate program execution"