UE23CS251A : SoC Design and Computer Architecture (4-0-2-4-5)

# of Sessions: 120

Unit #
Class
Topics to be Covered % of Portion covered
# Chapter Title/Reference
Literature
% of Cumulat
Syllabus ive %
1 T1: Chapter 2 Boolean Functions 25% 25%
2 Combinational Logic K-Maps
Design:2.1, 2.2, 2.7
3 Chapter 5 Digital Building K-Maps
4 Blocks: 5.2.1, 5.2.2 HDL and Verilog Basics
5 Chapter 3 Sequential HDL and Verilog Basics
Logic Design
6 Combinatorial Logic Design- Adder
3.2 (excluding 3.2.7)
7 A1: Verilog Practice Programs
3.3 (excluding 3.3.1,
8 3.3.3) L1: Basic Gates
9 3.4 (excluding 3.4.4) L1: Adder (One bit & N-bit)
10 3.4.1, examples 3.6, Combinatorial Logic Design- Subtracter
3.7, 3.9
11 Combinatorial Logic Design- MUX/Demux
Handout : Link 1
12 Combinatorial Logic Design- MUX/Demux
13 Combinatorial Logic Design- Shifters
14 Sequential Logic Design- Latches & Flip Flop
15 Sequential Logic Design- Latches & Flip Flop
A2: Write a Verilog code and test bench for Flip-Flop,
16
Synchronous Register
17 L2: Design of an ALU
18 L2: Design of an ALU
19 Combinational Logic Design Examples
20 Combinational Logic Design Examples
21 Design of Finite State Machine
22 Design of Finite State Machine
23 Design of Finite State Machine
24 Design of Finite State Machine -Counters
25 A3: Write a Verilog code and test bench for Counters
26 L2: Design of an ALU
27 L2: Design of an ALU
28 Design of Finite State Machine-Counters
29 Design of Finite State Machine-Counters
30 Memory Arrays
31 Adder/Multiplier (Shift Add & Wallace Tree)
32 Adder/Multiplier (Shift Add & Wallace Tree)
33 Adder/Multiplier (Shift Add & Wallace Tree)
A4: Write a Verilog code and test bench for Prefix
34
adders.
35 L3: Design of a Register File.
36 L3: Design of a Register File.
37 Adder/Multiplier (Shift Add & Wallace Tree)
38 Divider Circuit
39 Floating Point Units
R3: Chapter 6 Arithmetic
40 6.4 Assembly Language
41 Handout Assembly Language
42 Link 2 29.2.3, 29.3.2 Machine Language & Addressing Modes
43 Chapter 5 Digital Building Machine Language & Addressing Modes
Blocks
44 Machine Language & Addressing Modes
5.3.2 (excluding
subsections Rounding A5: Write a Verilog code and test bench for Multiplier or
45
and Floating-Point Divider circuit.
Addition) L4: Design of Program Counter and Data Path
46
Design 25% 50%
Chapter 6 Architecture
47 6.1, 6.2 L4: Design of Program Counter and Data Path Design
48 6.3, 6.4.1 Single Cycle Processor Data Path and Control
49 6.4.2, 6.4.3 (exclude Single Cycle Processor Data Path and Control
switch/case statements)
50 Single Cycle Processor Data Path and Control
6.4.4 (exclude magnitude
51 comparison), 6.5 Multi Cycle Processor Data Path and Control
52 Chapter 7 Multi Cycle Processor Data Path and Control
Microarchitecture
53 Multi Cycle Processor Data Path and Control
7.1, 7.2,7.3,7.4
54 Multi Cycle Processor Data Path and Control
55 L5: Control Logic Design
56 L5: Control Logic Design
L6: Fetch/Decode/Execute logic implementation
57
for ARM instruction
L6: Fetch/Decode/Execute logic implementation
58
for ARM instruction
L6: Fetch/Decode/Execute logic implementation
59
for ARM instruction
L6: Fetch/Decode/Execute logic implementation
60
for ARM instruction
61 1.6,2.3 of R2, RISC & CISC Instruction Set Architecture(ISA) 25% 75%
A-3 of T2,
62 RISC & CISC Instruction Set Architecture(ISA)
pg no: 51-55 of R2
63 Chapter 3.1 to 3.5 of T1 RISC & CISC Instruction Set Architecture(ISA)
64 6.8,5.6 of T2 Addressing modes & Operands
65 Appendix C-1, C-2, Addressing modes & Operands
Sec 1.1 , 1.4, 1.5 of T2
Appendix B.1, B.2, B.3 of A6: Implementation of ARM7TDMI-ISA to Block transfer
66
T2 of data items, Find sum of N data items in the memory
67 L7: ARM Instruction Set and Sample Programs
68 L7: ARM Instruction Set and Sample Programs
69 Instruction Set: Encoding, Operations, Control Flow
70 Instruction Set: Encoding, Operations, Control Flow
71 3 and 5 stage Pipe Lining
72 3 and 5 stage Pipe Lining
73 Pipeline Hazards
74 Pipeline Hazards
A7: Consider the following sequence of instructions in
MIPS architecture.
LDR R1, [R2,#40]
ADD R2, R3, R3
ADD R1, R1, R2
75 STR R1, [R2,#20]
a. Find all dependencies in this instruction sequence.
b. Find all hazards in this instruction sequence for a five
stage pipeline with and without data forwarding.
c. Find whether NOPs are required to be introduced
inspite of data forwarding in this instruction sequence
76 L8: ARM Instruction Set and Sample Programs
77 L8: ARM Instruction Set and Sample Programs
78 Stalling & Forwarding
79 Branch Prediction
80 Branch Prediction
81 Cache Memory Basics
82 Direct Mapped and Set Associatice Cache Memories
83 Direct Mapped and Set Associatice Cache Memories
84 Direct Mapped and Set Associatice Cache Memories
85 Direct Mapped and Set Associatice Cache Memories
A8: Consider the following sequence of instructions in
MIPS architecture.
LDR R1, [R6,#40]
BEQ R2, R3, LABEL2 ; BRANCH TAKEN
ADD R1, R6, R4
LABEL2:BEQ R1,R2, LABEL1 ; BRANCH NOT TAKEN
86 STR R2,[R4, #20]
AND R1, R1, R4

a. Draw the pipeline execution diagram for this code,

assuming there are no delay slots and that branches
execute in the EX stage.
b. Repeat the exercise mentioned in a and draw the
 pipeline execution diagram for this code, assuming that
delay slots are used by writing a “SAFE INSTRUCTION”
in the delay slot.
L9: PARACHACHE Simulator & Cache Performace
87
Optimisation
L9: PARACHACHE Simulator & Cache Performace
88
Optimisation
89 Cache Performance (ARM & X86 Case studies)
90 Cache Performance (ARM & X86 Case studies)
91 Memory Hierarchy
92 Memory Hierarchy
93 Address Translation
94 Address Translation
95 Address Translation
L10: Cycle Accurate Instruction Set Simulation with
96
Pipelining
L10: Cycle Accurate Instruction Set Simulation with
97
Pipelining
98 Interrupts and Virtual Memory
99 Interrupts and Virtual Memory
100 Interrupts and Virtual Memory
101 T2: Sec 1.9 ,Sec 3.1, 4.1 Page Table andTLB 25% 100%
Handouts
102 Page Table andTLB
103 Page Table andTLB
104 Page Replacement policies
105 Page Replacement policies
106 I/O Systems
107 Advanced Micro Architectures
108 Advanced Micro Architectures
109 Flynn's Taxonomy and Multicore Architectures
110 Flynn's Taxonomy and Multicore Architectures
111 Flynn's Taxonomy and Multicore Architectures
112-
Project Work
120

Tool/ Languages: ARM Simulator, Verilog IDEs, FPGA programming Tools, ARM Dev Kit and IDE's

Text Books:
1. “Digital Design and Computer Architecture - Arm Edition “, Sarah L Harris and David Money Harris, ,
Morgan Kaufmann, 2016
2. "Computer Architecture : A Quantitative Approach”, J L Hennessey, D A Patterson, 5th Edition,
Morgan Kaufmann, 2011

References:
1. "The Definitive Guide to ARM Processors”, Joseph Yiu, 2nd Edition, Newnes, 2015
2. "ARM System-on-Chip Architecture”, Steve Furber, 2nd Edition, Pearson, 2015
3. Computer Organization, Carl Hamacher, SafwatZaky, ZvonkoVranesic, Fifth Edition,Mc Graw Hill,2002
4. "Computer Organisation and Design”, David A Patterson, John L Hennessey,5th Edftion, Elesevier, 2016
5. "Computer Systems for Programmers – A Programmer's Perspective”, Randal E Bryant, David R
O'Hallaron, 3rd Edition, Pearson, 2019