Module 3

Memory and Peripherals

Interfacing

1
8086 Microprocessor
Memory

Processor Memory
▪ Registers inside a microcomputer
▪ Store data and results temporarily
▪ No speed disparity
▪ Cost 

Primary or Main Memory

▪ Storage area which can be directly
Memory accessed by microprocessor
▪ Store programs and data prior to
Store
execution
Programs
▪ Should not have speed disparity with
and Data
processor  Semi Conductor
memories using CMOS technology
▪ ROM, EPROM, Static RAM, DRAM

Secondary Memory
▪ Storage media comprising of slow
devices such as magnetic tapes and
disks
▪ Hold large data files and programs:
Operating system, compilers,
databases, permanent programs etc. 105
8086 Microprocessor
Memory organization in 8086

Memory IC’s : Byte oriented

8086 : 16-bit

Word : Stored by two

consecutive memory locations;
for LSB and MSB

Address of word : Address of

LSB

Bank 0 : A0 = 0  Even
addressed memory bank

Bank 1 : 𝑩𝑯𝑬 = 0  Odd

addressed memory bank

106
8086 Microprocessor
Memory organization in 8086

Operation 𝑩𝑯𝑬 A0 Data Lines Used

1 Read/ Write byte at an even address 1 0 D7 – D0

2 Read/ Write byte at an odd address 0 1 D15 – D8

3 Read/ Write word at an even address 0 0 D15 – D0

4 Read/ Write word at an odd address 0 1 D15 – D0 in first operation

byte from odd bank is
transferred
1 0 D7 – D0 in first operation
byte from odd bank is
transferred 107
8086 Microprocessor
Memory organization in 8086

Available memory space = EPROM + RAM

Allot equal address space in odd and even

bank for both EPROM and RAM

Can be implemented in two IC’s (one for

even and other for odd) or in multiple IC’s

108
8086 Microprocessor
Interfacing SRAM and EPROM

Typical Semiconductor IC Chip

No of Memory capacity Range of

Address address in
pins hexa
In Decimal In kilo In hexa

20 220= 10,48,576 1024 k = 1M 100000 00000

to
FFFFF

110
 Interfacing Memory to 8086
Memory Device

7
 Memory Chip Size and Numbers

EPROM ICs available

Pin Configuration (EPROM Series)

9
RAM ICs

10
RAM ICs

11
Interface 4KB of EPROM with starting address from 0000H and 2KB of RAM
with starting address followed by EPROM. Assume the processor has 16 address
lines.

Step 1-
Total EPROM required = 4KB
Chip Size available = 4KB (assume IC 2732)
No. of chips required = 4KB / 4KB = 1 Chip1
–
Starting address = 0000H
Chip size = 4KB = 4096 * 8 = 1000H
Ending address = 0FFFH

31
Ending address = 17FFH
Memory Map

36
Decoding Logic
EPROM chip size = 4KB RAM
chip size = 2KB

Smaller chip size is RAM = 2KB = 2^11B

Therefore, neglect lower 11 address lines i.e. A0 to A10
Consider remaining address lines A11 to A15 for decoding.

37
Final Implementation

38
Interface 8KB EPROM and 8KB RAM using 4KB devices. Assume the processor
has 16 address lines.
Step 1-
Total EPROM required = 8KB
Chip Size available
= 4KB (assume IC 2732)
No. of chips required
= 8KB / 4KB = 2
Chip size = 4KB = 1000H
Memory Locations from 00000H to 01000-1= 0FFFH
Chip1 – Starting address for 4KB chip1
= 0000H
Ending address for 4KB chip1
= 1000H - 1H = 0FFFH
Chip 2 – Starting address for 4KB chip2
= Previous ending address of 4KB chip1 + 1
= 0FFFH + 1
= 1000H
Ending address for 4KB chip2
= 1000H + 0FFFH = 1FFFH 35
Step 2-
Total RAM required = 8KB
Chip size available
= 4KB (assume IC 6232)
No of chips required
= 8KB / 4KB = 2
Chip 1- Starting address
= Ending address of EPROM + 1
= 1FFFH + 1
= 2000H
Ending address
= 2000H + 0FFFH = 2FFFH
Chip 2 – Starting address
=Previous Ending address + 1
= 2FFFH + 1
= 3000H
Ending address
= 3000H + 0FFFH = 3FFFH 36
Memory Map

41
Decoding Logic
EPROM Chip Size =4KB = RAM Chip Size = 4KB

Therefore smaller chip size = 4KB = 2^12 B

Therefor neglect lower 12 address lines i.e. A0 to A11

Consider remaining address lines i. e. A12 to A15 for decoding.

Hence 4:16 decoder is required.

42
Design a 8086 based system with the following specifications :
1) 8086 working at 10MHz at minimum mode
2) 32KB EPROM using IC 27128
3) 256KB RAM using IC 62512
Step 1-
Total EPROM required = 32KB
Chip Size available
= 16KB (assume IC 27128)
No. of chips required
= 32KB / 16KB = 2
Number of sets required = No. of chips / No. of Banks
=2/2=1
Set 1 – Ending address = FFFFFH
Set size = chip size * 2
= 16KB * 2 = 32KB = 2^15 = 0000 0111 1111 1111 1111 = 07FFF
Starting address = Ending address – Set size
= FFFFFH – 07FFFH
= F8000H

43
Memory
Map

42
Design a 8086 based system with the following specifications :
1) 8086 working in minimum mode at 6MHz
2) 64 KB monitor program memory (EPROM) using IC 27128
3) 128 KB application memory (RAM) using IC 62256
4) 2 16-bit input ports and 2 16-bit output ports in handshaking mode

Step 1- Total EPROM required = 64KB

Chip Size available
= IC 27128 i.e 128/8 = 16KB
No. of chips required
= 64KB / 16KB = 4
Number of sets required = No. of chips / No. of Banks
=4/2=2
Set size = chip size * 2
= 16KB * 2 = 32KB = 2^15 = 0000 0111 1111 1111 1111= 07FFF
Set 1 – Ending address of set 1= FFFFFH
Starting address = Ending address of set 1 – Set size
= FFFFFH – 07FFFH
= F8000H
Set 2 – Ending address of set 2 = Previous starting address of set 1 – 1
= F8000H – 1 = F7FFFH
Starting address = Ending address of set 2 – Set size
= F7FFFH – 07FFFH
= F0000H 44
Set 2 – Starting address = Previous Ending address of set 1 + 1
= 0FFFFH + 1 = 10000H
Ending address = Starting address of set 2 + Set size
= 10000H + 0FFFFH
= 1FFFFH

46
47
Implementation

48
Design a 8086 based system with the following specifications :
1) 8086 working in minimum mode at 8MHz
2) 32 KB monitor program memory (EPROM) using 16KB device
3) 64 KB application memory (SRAM) using 32KB device

49
8086 Microprocessor

Memory mapping I/O mapping

20 bit address are provided for I/O 8-bit or 16-bit addresses are
devices provided for I/O devices

The I/O ports or peripherals can be Only IN and OUT instructions can be
treated like memory locations and used for data transfer between I/O
so all instructions related to device and processor
memory can be used for data
transmission between I/O device
and processor

Data can be moved from any Data transfer takes place only
register to ports and vice versa between accumulator and ports
When memory mapping is used for Full memory space can be used for
I/O devices, full memory address addressing memory.
space cannot be used for
addressing memory.  Suitable for systems which
require large memory capacity
 Useful only for small systems
where memory requirement is less
For accessing the memory mapped For accessing the I/O mapped
devices, the processor executes devices, the processor executes I/O
memory read or write cycle. read or write cycle.

 M / 𝐈𝐎 is asserted high  M / 𝐈𝐎 is asserted low 114

IO Interfacing
8086 Microprocessor
Interfacing I/O and peripheral devices

I/O devices
 For communication between microprocessor and
outside world

 Keyboards, CRT displays, Printers, Compact Discs

etc.


Ports / Buffer IC’s
Microprocessor I/ O devices
(interface circuitry)

 Data transfer types

Memory mapped
Programmed I/ O
Data transfer is accomplished I/O mapped
through an I/O port
controlled by software

Interrupt driven I/ O
I/O device interrupts the
processor and initiate data
transfer
Direct memory access
Data transfer is achieved by 113
bypassing the microprocessor
• Any application of Microprocessor Based system Requires the transfer of data
between external circuitry to the Microprocessor and Microprocessor to the
External circuitry. User can give information (i.e., input) to the Microprocessor
using keyboard and user can see the result or output information from the
Microprocessor with the help of display.

• Hence interfacing is used to exchange information between two different

applications/devices.
 8255 FEATURES

•The port A lines are identified by symbols PA0-PA7 while the port C lines are
Identified as PC4-PC7.
• Similarly, Group B contains an 8-bit port B, containing lines PB0-PB7 and a 4-bit
port C with lower bits PC0- PC3.

• The port C upper and port C lower can be used in combination as an 8-bit port C.
• Both the port C is assigned the same address.
•Thus one may have either three 8-bit I/O ports or two 8-bit and two 4-bit ports
from 8255.

• All of these ports can function independently either as input or as output ports.
• This can be achieved by programming the bits of an internal register of 8255
called as control word register (CWR).

By Asst Professor Soniya R

8255 PPI
8255 PPI
8255 PPI PIN DIAGRAM
 Register selection

S’ A1 A0 Selection Address

0 0 0 PORT A 80 H

0 0 1 PORT B 81 H

0 1 0 PORT C 82 H
Control
Register
0 1 1 83 H
1 X X No Seletion X
CWR FORMATE
 I/O Modes:
Mode 0 (Basic I/O mode): This mode is also called as basic input/output Mode. This mode
provides simple input and output capabilities using each of the three ports. Data can be
simply read from and written to the input and output ports respectively, after appropriate
initialization.
 Mode 1
Mode 1: (Strobed input/output mode ) In this mode the handshaking control the
input and output action of the specified port. Port C lines PC0-PC2, provide strobe or
handshake lines for port B.
This group which includes port B and PC0-PC2 is called as group B for Strobed data
input/output. Port C lines PC3-PC5 provides strobe lines for port A.

This group including port A and PC3-PC5 from group A. Thus port C is utilized for
generating handshake signals.

The salient features of mode 1 are listed as follows

• Two groups – group A and group B are available for strobed data transfer.
• Each group contains one 8-bit data I/O port and one 4-bit control/data port.
•The 8-bit data port can be either used as input and output port. The inputs and
outputs both are latched.
Out of 8-bit port C, PC0-PC2 are used to generate control signals for port B
andPC3-PC5 are used to generate control signals for port A. the lines PC6, PC7 may be
used as independent data lines.
D0-D7 (Data Bus) –
These are bidirectional, tri-state data bus lines are connected to the system data bus.
They are used to transfer data and control word from microprocessor to 8255 or
receive data or status word from 8255 to the microprocessor.
PA0-PA7 (Port A) –
These are 8 Bit bidirectional I/O pins used to send data to output device and to
receive data from input device. It functions as an 8 Bit data output latch/buffer
when used in output mode and as an 8 Bit data input latch/buffer when used in
input mode.
PB0-PB7 (Port B) –
These are 8 Bit bidirectional I/O pins used to send data to output device and to
receive data from input device. It functions as an 8 Bit data output latch/buffer
when used in output mode and as an 8 Bit data input latch/buffer when used in
input mode.
PC0-PC7(Port C) –
These are 8 bit bidirectional I/O pins divided into two groups PCL (PC3-PC) and PCU
(PC7- PC4).these groups can individually transfer data in or out when programmed for
simple I/O and used as handshake signals when programmed for handshake or bidirectional
modes.
RD –
When this pin is low, the CPU can read data in the ports or the status word through the data
bus buffer.
WR –
When this pin is low, the CPU can write data on the ports or in the control register through
the data bus buffer.
CS –
This pin can be enabled for data transfer operation between the CPU and 8255.
RESET –
This pin is used to reset 8255.i.e control register gets cleared and all the ports are set to the
input mode.
A0-A1 –
The selection of input port and control word register is done by using
A0 and A1 pins in conjunction with RD and WR pins.
Data Bus Buffer
It is used to interface the internal data bus of 8255 to the system data bus by reading
and writing operations.
Read/write Control logic
It accepts the input from the address bus and issues commands to the individual
group blocks. also issues appropriate enabling signals to access the required
data/control words/status words.
Port A
It can be programmed in three modes Mode0, Mode1 and Mode2.
Port B
It can be programmed in modes Mode0 and Mode1.
Port C
It can be programmed for Bit Set/reset operation.
There are two main operational modes of 8255:
1. Input/output mode
2. Bit set/reset mode (BSR Mode).

I/O mode again classified into three types

a. Mode 0
b. Mode 1
c. Mode 2
It is a port c bitset/reset mode.
The individual bit of port c can be set or reset by writing control word in the
control register.
Write set of instructions to perform the following
– 1) Set bit-4 of port C
2) Reset bit-4 of port C
Assume the address PA = 10H, PB = 12H, PC = 14H and Control register = 16H
There are three I/O modes of operation-
1. Mode 0 – Basic I/O
2. Mode 1 – Strobed I/O
3. Mode 2 – Bit-directional I/O
I/O modes are programed using control register.
When 8255 is reset, it will clear control word register contents and all
the ports are set to input mode.
The ports of 8255 can be programmed for other modes by sending
appropriate bit pattern to control register.
Ex. - Write a set of instructions to perform the following –
1. Initialize port A as input, port B as output, port C upper as output and port C lower as input.
2.Use Mode-0 for group A and Mode-1 for group B
The control word format required will be,

The initialization instructions are –

MOVAl, 95H
OUT CWR, AL
Mode 0 – (Simple Input / Output Mode)
In this mode, the ports can be used for simple input/output operations without
handshaking.
If both port A and B are initialized in mode 0, the two halves of port C can be either
used together as an additional 8-bit port, or they can be used as individual 4-bit
ports.
Since the two halves of port C are independent, they may be used such that one-half
is initialized as an input port while the other half is initialized as an output port.

Features -
▪ Two 8-bit ports and two 4-bit ports
▪ Any Port can be input or output
▪ Outputs are latched
▪ Input are not latched
▪ 16 different Input/Output configurations possible
Timing waveform for mode 0 input mode

Timing waveform for mode 0 output mode

Mode 1 – (Strobed I/O)
When we wish to use port A or port B for handshake (strobed) input or
output operation, we initialize that port in mode 1.
For port B in this mode (irrespective of whether is acting as an input
port or output port), PC0, PC1 and PC2 pins function as handshake
lines.

Functions –
▪ Two ports i.e., port A and B can be use as 8-bit i/o port.
▪ Each port uses three lines of port c as handshake signal and remaining
two signals can be function as i/o port.
▪ Interrupt logic is supported.
▪ Input and Output data are latched.
Mode 2 – (Strobed Bi-directional I/O)
Only group A can be initialized in this mode.
Port A can be used for bidirectional handshake data transfer. This means that
data can be input or output on the same eight lines (PA0 - PA7).
Pins PC3 - PC7 are used as handshake lines for port A.
The remaining pins of port C (PC0 - PC2) can be used as input/output lines if
group B is initialized in mode 0.
In this mode, the 8255 may be used to extend the system bus to a slave
microprocessor.
Program Statement –
Write a program to blink port C bit-2 of 8255. Assume address of
control word register of 8255 as 83H. Use Bit Set / Reset mode.

Control word to make bit-2 HIGH

Control word to make bit-2 LOW

DMA Channels
• 8257 has 4 independent DMA channels (CH0 to CH3), hence four I/O
devices can request for DMA simultaneously.
• Each channel consists of two 16-bit registers (i) Address register (ii) Count
Register.
• Address register holds the starting address of the memory block to be
accessed by I/O device.
• Count register holds the number of bytes to be transferred during DMA
action.
The low order 14-bits of count register specify the number of bytes;
therefore, each channel can support data transfer of 2^14=16KB during
DMA process.
The high order 2-bits of count register specify the mode of operation
(read, write or verify)
DMA Cycles:
DMA READ : In this cycle, data is transferred from memory to I/O device.
DMA Write : In this cycle, data is transferred from I/O device to memory.
DMA Verify :
In this cycle, data is not transferred between memory and I/O.
It is used by the peripheral device to verify the data that has been recently transferred.
To avoid overwriting registers of channel 3, update flag in the status register can be
monitored by the CPU.
Data Bus Buffer
This 8-bit Bidirectional buffer is used to interface the 8257 to the system Data
Bus.
It allows the transfer of data and information between 8257 and microprocessor.
In master mode, it is used to output the higher order (A8-A15) of memory
address.
In slave mode, it is used to transfer the data between 8257 and microprocessor.
Read/Write Control Logic
8257 operates in two basic modes, master mode and slave mode.
In the slave mode, read/write logic accepts the read or write signal.
In the master mode, read/write logic generates the signals for DMA write cycle or
and for DMA read cycle.
Priority Resolver
This logic block determines the priorities of the channels when more than one I/O
device request for DMA.
By default, the priority resolver work in fixed priority mode.
In this mode the CH0 has the highest priority while the CH3 has lowest.
In rotating priority, the priority of the channels has a circular sequence.
The channel which has being just serviced move to the lowest priority and channel
next to it move to the highest priority, hence each channel achieves the highest
priority in rotation.
Fixed Priority Mode :
In the fixed priority, channel 0 has the highest priority and channel 3 has the lowest
priority.

In the fixed priority, after recognition of any one channel for service, the other channels are
prevented from interfering with that service until it is completed.
If bit 4 of mode set register is logic 0, Operating Modes of 8257 operates in fixed priority
mode.
Rotating Priority Mode :
In rotating priority mode, the priority of the channels has a circular sequence.
In this, channel being serviced gets the lowest priority and the channel next to it gets the
highest priority.

Thus, with rotating priority in a single chip DMA system, any device requesting service is
guaranteed to be recognized after not more than three higher priority services have
occurred.
This prevents any one channel from monopolizing the system.
The rotating priority mode can be set by writing logic ‘1’ in the bit 4 of the mode set
register
Control Logic
In the master mode, Control logic controls the sequence of operation during DMA
cycles (DMA read, DMA write & DMA verify).
It also generates required control signals and memory address to be accessed.
It increments 16-bit address register and decrement count register of corresponding
channel during DMA action.
It is disabled in slave mode.
Mode Set Register
Extended Write Mode :
Microcomputer systems allow use of various types of memory and I/O devices with
different access time.
• If a device can not be accessed within a specific amount of time it
returns a “not ready” indication to the 8257 that causes the 8257 to
insert one or more wait states in its internal sequencing.

• The extended write option provides alternative timing for the I/O
and memory write signals which allows the devices to return an
early READY and prevents the unnecessary occurrence of wait states
in the Operating Modes of 8257.

• It does this by activating MEMW and IOW signals earlier in the DMA
cycle, giving more setup time.
TC STOP Mode :
If the TC stop bit is set, a channel is disabled (i.e. its enable bit is reset) after the terminal
count (TC) output goes high, thus automatically preventing further DMA operation on
that channel.

To enable DMA operation on the channel it is necessary to set enable bit of the
corresponding channel in the mode set register.

If the TC STOP bit is not set, the occurrence of the TC output has no effect on the
channel enable bits.
Auto Load Mode :
Auto load Mode when enabled, permits block chaining operations, without immediate
software intervention between blocks.
In this mode, channel 2 parameters (DMA starting address, terminal count and DMA transfer mode)
are initialized as usual for the first data block.

These parameters are automatically duplicated in the channel 3 registers when channel 2 is initialized.

After the first block of DMA cycles is executed by channel 2 (i.e., after the TC output goes high), the
parameters stored in the channel 3 registers are transferred to channel 2 during an ‘update’ cycle and
next block of DMA cycle is executed.

This repeat block operations can be used in applications such as CRT refreshing.
1.It is a 4-channel Direct Memory Access (DMAC) interface IC which allows data transfer between memory and
up to 4 I/O devices, bypassing CPU.
2.A maximum of 16 KB of data (= 214) can be transferred by this IC sequentially at a time. When a DMA request
comes from a peripheral, the DMAC 8257, via its HRQ (Hold Request) pin, requests the CPU on its HOLD pin.
CPU then acknowledges this request via its HLDA pin which goes to HLDA pin of 8257. After this, DMAC
generates the required MEMR, MEMW, I/OR, I/OW signals.
3.Initialization of the DMAC is done under program control for each channel. The parameters which need to be
initialized for each channel are starting address, number of bytes of data to be transferred, mode of operation, etc.
4. DMAC can be operated in three modes: (a) DMA Read (reading from memory, writing into peripheral), (b)
DMA Write (writing into memory, reading from peripheral), (c) DMA verify.
5. Priority for each of the 4 channels can be set in (a) fixed priority, (b) rotating priority.
6.A Terminal Count Register exists for each of 4 channels. The number of bytes of data to be transferred is
stored in the D13–D0 positions of the 16-bit Terminal Count Register. On completion of data transfer, the
Terminal Count (TC) pin goes high.
7.When the CPU is in control of its buses (address bus, data bus and control bus), it acts as master and DMA
controller acts as the slave. When DMA controller takes control of the buses, it becomes the master and CPU
becomes the slave.
The 8259 can be programmed
through a sequence of simple I/O
operations It accepts two types of
command words.

They are :
(a)Initialization Command Word
(ICW)
(b)Operational Command Word
(OCW)