Benazir Bhutto Shaheed University Lyari (BBSUL)

Digital Logic Devices

Lecture Notes-2

By: Prof. Dr Taj Mohammad Baloch

1
Boolean Addition and Multiplication
 The rules for Boolean Addition are:
0+0=0
0+1=1
1+0=1
1+1=1

 The rules for Boolean Multiplication are:

00=0
01=0
10=0
11=1

NB/EAB1054 Jul 2004 Boolean Algebra 2

 Associative Law
 The order the variables are grouped when ANDing
or ORing more than 2 variables does not matter.
 Associative law for addition(OR):
A + (B +C) = (A + B) + C
A


A A + (B + C)
B (A + B) + C
B
C C
 Associative law for multiplication(AND):
A(BC) = (AB)C
A


A A (BC)
B (A B)C
B
C C

NB/EAB1054 Jul 2004 Boolean Algebra 3

Summary of Boolean Algebra
Commutative laws : A+B = A
AB = BA
Associative laws: A+(B+C) = (A+B)+C
A(BC) = (AB)C
Distributive laws: A(B+C) = AB + AC
A +0=A AA=A
A +1=1 A  A’ = 0
A 0=0 A’’ = A
A 1=1 A + AB = A
A +A=A A + A’B = A + B
A + A’ = 1 (A+B)(A+C) = A + BC

NB/EAB1054 Jul 2004 Boolean Algebra 4

Boolean Expression for a Logic
Circuit
 Steps to determine Boolean expression of a
logic circuit:
 Step 1:
 Starting from the left-most inputs, determine output of
each logic gate.
 OR gate  Boolean addition, AND gate  Boolean
multiplication.
 Step 2:
 If output of a logic gate is the input of another logic gate,
use the expression for the output which you had found
earlier to determine the output of the next logic gate.

NB/EAB1054 Aug 2004 Boolean Analysis of Logic Circuits 5

Boolean Expression for a Logic
Circuit
 Step 3:
 Continue finding the expression of all outputs until you
have reached the final output or the right-most output.

NB/EAB1054 Aug 2004 Boolean Analysis of Logic Circuits 6

Example 1

 Determine the Boolean expression for the

following logic circuit:

AB

X=AB+AC
AC

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Example 2

 Determine the Boolean expression for the

following logic circuit:

A+B

B’C Y=(A+B)+B’C
B’

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Constructing a Truth Table

 Step 1: List down all possible input

combinations.
 Step 2: Put a 1 for each combination of
output variables determined in the evaluation.
 Step 3: Place a 0 for all other input
combinations.

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Constructing a Truth Table
 e.g. Truth table for X = AB+CD
A B C D X  Step 1: List down all
0 0 0 0 0 possible input
0 0 0 1 0
0 0 1 0 0 combinations.
0 0 1 1 1
0 1 0 0 0
 Step 2: Put a 1 for
0 1 0 1 0 each combination of
0 1 1 0 0
0 1 1 1 1
output variables
1 0 0 0 0 determined in the
1 0 0 1 0
1 0 1 0 0
evaluation.
1 0 1 1 1  Step 3: Place a 0 for
1 1 0 0 1
1 1 0 1 1 all other input
1 1 1 0 1 combinations.
1 1 1 1 1

NB/EAB1054 Aug 2004 Boolean Analysis of Logic Circuits 10

Exercise 1

 a) Find the Boolean expression for the

following logic circuit.

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NB/EAB1054 Jul 2004 Boolean Algebra 12
 Constrct Logic circuit from given Boolean
expression
 EX
 1

 2

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Write down the Boolean Expression of
Following Logic circuits

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 Example 1

 How many logic gates are used? 6

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NB/EAB1054 Aug 2004
Jul 2004 Simplification usingAlgebra
Boolean Boolean Algebra 15
15
 From Truth Table to Logic Circuit
■ Example 1: Implement the logic circuit whose logic
function is specified by the truth table below:

Inputs Output
A B C Z
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 0
1 1 1 0
NB/EAB1054 Jul 2004 Boolean Algebra 16
 From Truth Table to Logic Circuit

■ The SOP expression for the logic function in the

previous slide is thus:
Z = A’BC’ + A’BC + AB’C
■ The logic circuit implementation is:
A AB’C

B
A’BC
Z

A’BC’
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 Karnaugh Map Format

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NB/EAB1054 Jul 2004 Boolean Algebra 19
NB/EAB1054 Jul 2004 Boolean Algebra 20
 Combinational Logic Circuits

AND-OR-Invert Logic Circuit

■ Complement of the AND-OR circuit.

■ Implements a POS expression. (Proof: Use
Demorgan’s Theorem)
AB  CD  ( AB)(CD)  ( A  B)(C  D)
■ E.g.
AB
AB + CD

(AB + CD)’ = (A’ + B’)(C’ + D’)

C
D

NB/EAB1054 Jul 2004 Boolean Algebra 21

 Exclusive-OR Logic

■ Combination of 2 AND gates, 1 OR gate, and

2 inverters.
■ Output high only when two inputs are at
opposite levels.
A


A
X = AB’ + A’B X=A B
B

NB/EAB1054 Jul 2004 Boolean Algebra 22

The Half
Adder
■From the rules of ■ From the truth table
binary addition, the we can derive the
truth table for a half expressions for Cout
adder is therefore: and ∑:
Inputs Outputs
Cout = AB
A B Cout ∑ Σ =
0 0 0 0 ■ The A⊕B
half adder logic
0 1 0 1 diagram is:
1 0 0 1 A
Sum
1 1 1 0 B

Cout

NB/EAB1054 Aug 23
2004 Applications of Combinational
Logic
 The Full Adder
■ E.g, addition of two 5-bit binary numbers: 10101
and 00111: 1 1 1
1 0 1 0 1 (augend)

+ 0 0 1 1 1 (addend)

Sum → 1 1 1 0 0
Carry → 0 0 1 1 1
■ Starting from LSB, the corresponding bits of the
augend and the addend are added together to get
the sum bit and the carry bit.
■ Resulting carry bit added to the next significant
bits
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of the augend and addend.
Boolean Algebra 24
 The Full Adder
■ The full adder: ■ The full adder truth
❑ accepts two input bits and table
an input carry Inputs Outputs
A B Cin Cout ∑
❑ generates the sum and
carry output. 0 0 0 0 0
0 0 1 0 1
■ Difference between a full 0 1 0 0 1
adder and a half adder is 0 1 1 1 0
1 0 0 0 1
that it accepts an input 1 0 1 1 0
carry. 1 1 0 1 0
1 1 1 1 1

NB/EAB1054 Jul 2004 Boolean Algebra 25

 The Full Adder
■ The logic diagram for a full adder is:

U1A
A 1
3 1
U2A
2 3

∑
2
74U84
6A
N
B 1
3
7486N
U3A
2 1
3
2
7408N U5A
Cin 7408N 1
3
2 Cout
7432N

■ To implement a full adder using half adders:

NB/EAB1054 Jul 2004 Boolean Algebra 26
 The Full Adder
∑
■ The logic symbol for a full adder is A ∑ Su
B
Ci Cout Ca
n
■ The full adder outputs can be
described by the following expressions:

∑ =A⊕B⊕
C
Cout = ( A ⊕ B)Cin +
AB
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 Comparators
■ Compares the magnitude of two binary quantities to
determine whether they are equal.
■ Some can indicate which of 2 binary no’s is larger.
■ A comparator which indicates whether two numbers
are equal will give an output HIGH if the two
numbers are equal. The truth table is:

Inputs Output

A B
0 0 1
0 1 0
1 0 0
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Decoders
■ A decoder detects the presence of a specific
combination of bits on its inputs and to
indicate the presence of the combination at
the output.
■ some special decoder ICs available (e.g.
74HC154 – 1 of 16 decoder, and 74HC42 –
BCD to decimal decoder) , there is really no
specific decoder design.

29
 Decoders
■ For example, let’s design a simple decoder, which
gives a HIGH output when the input combination is
1011. For other input combinations, the output is
LOW.
■ If we designate A0 to A3 as the input bits with A0
being the LSB and A3 being the MSB, the SOP
expression for this decoder is: A3 A2 A1 A0
■ Therefore, the logic circuit for the decoder is:
U1A
U2A 1
2
U2B
1 2
6 3 4

7404N
4
5
A3 A2 A1A0
7404N

7440N 30
Multiplexers (Data Selectors)

■ A multiplexer is a logic circuit that accepts

several digital inputs and selects one of them
at any given time to pass on to the output.
■ There are two types of inputs in a multiplexer:
select (or address) inputs and data inputs.
■ The select inputs control which data inputs
will be selected to the output.

31
 Multiplexers (Data Selectors)
■ E.g. consider a 4-input ■ The data output is equal to :
multiplexer (MUX) with the ❑ D0 only if S1=0 and S0=0:
logic symbol: Y = D0 S1’ S0’.
MUX ❑ D1 only if S1=0 and S0=1:
Select S0 0
inputs S1 1 Y = D 1 S1’ S 0.
D0 Y Data
0 ❑ D2 only if S1=1 and S0=0:
D1 output
Data 1 Y = D2 S1S0’
inputs D2 2
D3 3 ❑ D3 only if S 1=1 and S 0=1:

■ The MUX operation is: Y = D3 S1 S0.

Data Select Inputs Input ■Thus, Y = D0 S1’

S1 S0
Selected S0’+ D1 S1’ S0+ D2
0 0 D0 S1S0’+ D3 S1 S0
0 1 D1
1 0 D2
1 1 D3
32
■ The logic diagram for a 4-input multiplexer is
therefore:

U1B
3 4
S0 U1A
S1 1 2
7404N
U2
7404N
D0
U3
D1
Y
OR4
D2

D3
AND3
33

3
What are Latches?
Latches are digital circuits that store a single bit of information and hold its value
until it is updated by new input signals. They are used in digital systems as
temporary storage elements to store binary information. Latches can be
implemented using various digital logic gates, such as AND, OR, NOT, NAND, and
NOR gates.
Latches are widely used in digital systems for various applications, including data storage
control circuits, and flip-flop circuits. They are often used in combination with other digital
circuits to implement sequential circuits, such as state machines and memory elements.
Latches are basic storage elements that operate with signal levels (rather than signal
transitions). Latches controlled by a clock transition are flip-flops

Types of Latches in Digital Electronics

In digital electronics different types of latches are:
• i. . SR Latches ii. Gated SR Latches
• iii. D Latches iv. Gated D Latches
• v. JK Latches vi. T Laches
i. SR Latch
S-R latches i.e., Set-Reset latches are the simplest form of latches and are implemented
using two inputs: S (Set) and R (Reset). The S input sets the output to 1, while the R inpu
resets the output to 0. When both S and R inputs are at 1, the latch is said to be in an
“undefined” state. They are also known as preset and clear states. The SR latch forms the
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basic buildingJulblocks
2004 Boolean
of all other types of Algebra
flip-flops. 34
 Logic Diagram of SR Latch

SR Latch is a logic circuit with:

•2 cross-coupled NOR gate or 2 cross-coupled NAND gate.
•2 input S for SET and R for RESET
•2 output Q, Q’.

a. logic diagram represents the SR latch using NAND gate.

The below logic diagram represents SR latch using NOR Gate.

Boolean Algeba 35
Different Cases of SR Latch
The different cases of SR latch are discussed below.
Case 1: S’ = R’ = 1 (S = R = 0)
If Q = 1, Q and R’ inputs for 2nd NAND gate are both 1.
If Q = 0, Q and R’ inputs for 2nd NAND gate are 0 and 1
respectively.

Case 2: S’ = 0, R’ = 1 (S = 1, R = 0)
•As S’ = 0, the output of 1st NAND gate, Q = 1 (SET
state).
•In second NAND gate, as Q and R’ inputs are 1,
Q’=0.

Case 3: S’ = 1, R’ = 0 (S = 0, R = 1)

Case 4: S’ = R’ = 0 (S = R = 1) 36
Truth Table of SR Latch

The below table represents the truth table of SR latch.

S R Q Q’

0 0 Latch Latch

0 1 0 1

1 0 1 0

1 1 0 0

37
 Logic Diagram of Gated SR Latch

The below logic diagram represents the gated SR llatch.

Boolean Algebra 38
The below table represents the truth table of Gated SR latch.

Enable S R Qn+1

0 X X Qn

1 0 0 Qn

1 0 1 0

1 1 0 1

1 1 1 X

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Flip Flop Logics

A flip-flop is a sequential digital electronic circuit having two stable states that
can be used to store one bit of binary data. Flip-flops are the fundamental
building blocks of all memory devices.

The flip-flops are basically the circuits that maintain a certain state unless and
until directed by the input for changing that state. We can construct a basic
flip-flop using four-NOR and four-NAND gates.

Types of Flip-Flops
The flip-flops are of the following types:
1. S-R Flip Flop
2. J-K Flip Flop
3. T Flip Flop
4. D Flip Flop

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 1. S-R Flip Flop
This is the simplest flip-flop circuit. It has a set input (S) and a reset input (R).
When in this circuit when S is set as active, the output Q would be high and
the Q' will be low. If R is set to active then the output Q is low and the Q' is
high. Once the outputs are established, the results of the circuit are maintained
until S or R get changed, or the power is turned off.

NB/EAB1054 Jul 2004 Boolean Algebra 41