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    Vlsi File Final 2

    Uploaded by

    Nishita Karda

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd

    Vlsi File Final 2

    Uploaded by

    Nishita Karda
    4 views36 pages

    Original Title

    vlsi file final 2 (1)

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    © © All Rights Reserved

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    PDF, TXT or read online from Scribd

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    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    4 views36 pages

    Vlsi File Final 2

    Uploaded by

    Nishita Karda

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 36

    Shri G.S.

    Institute of Technology & Science, Indore

    Department of Electronics & Telecommunication Engineering

    VLSI Design LAB project

    (Code-EC35010)

    Session: July-Dec2024

    A Laboratory Work Report

    Submitted By: Submitted To:

    NISHITA KARDA(0801EC221064) PROF. ASHWIN SHRIVASTAVA

    PARTH SHARMA (0801EC221067) PROF. NEERAJ MALVIYA


    PRANAV SHRIVASTAVA (0801EC221074)

    RAMESH DAWAR (0801EC221078)


    AndGate using Gate level style

    Code:

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    Technology Schematic:

    Simulation:
    FullAdderusing2halfadders
    Code:

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    Technology Schematic:

    Simulation:
    AllLogicGates Using Dataflow Style

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    Simulation:
    HalfAdderUsingGates(Dataflow Style)

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    Technology Schematic:

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    2:4-Decoder

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    Technology Schematic:

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    MUXUsingBehavioralStyle

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    Technology Schematic:

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    BCDtoExcess-3 using Behavioural Style
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    Technology Schematic:

    Simulation:
    D-Flip Flop using Behavioural Style
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    Simulation:
    JKFlipFlop Using Behavioural Style

    Code:

    module sp_JKff_BEHAVIORAL(
    input j,k,clk,
    output reg q,qbar
    );
    always @(posedge clk) begin
    if(j==0 && k==0)
    begin q<=q;
    qbar<=qbar; end
    else if(j==0 && k==1)
    begin q<=1'b0;
    qbar<=1'b1; end
    else if(j==1 && k==0)
    begin q<=1'b1;
    qbar<=1'b0; end
    else if(j==1 && k==1)
    begin q<=(~q);
    qbar<=(~qbar);
    end end
    endmodule
    RTL:
    Schematic:
    PriorityEncoder using Behavioural Style
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    Technology Schematic:

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    JohnsonCounter Using Behavioural Style

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    RingCounter

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    RippleCarryAdder
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    SevenSegment

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    UpCounter

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    Technology Schematic:

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    4–bitComparator

    Code:
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    Technology Schematic:
    Simulation:

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