JSPM’s

JAYWANTRAO SAWANAT COLLEGE OF ENGINEERING

Sr. No. 58, Handewadi Road, Hadapsar, Pune, Maharashtra 411028
Department of Electronics and Telecommunication Engineering

Experiment No: 10
Study of Shift Register 74HC194
Title: Evaluate the various functions of shift register 74HC194
Aim: Design and implement of 4-bit Ring Counter, Twisted ring Counter and pulse train generator
using IC74HC194.
CO:
Objective:
1) Perform the Functional verification of the universal shift register.
2) Design and implement 4-bit Ring counter using IC74HC194/IC74LS95.
3) Design and implement 4-bit Twisted ring-counter using IC74HC194/ IC74LS95
4) Design and implement pulse train generator using IC74HC194 for pulse 111001 (Use
right shift)
Pre-requisites: Basic knowledge of shift register and counter.
Hardware: Digital IC trainer kit, patch cords, power supply, IC’s- 74LS194/74HC95

Theory:
Shift Register:
A register is capable of shifting its binary information in one or both directions is known as
shift register. The logical configuration of shift register consist of a D-Flip flop cascaded with
output of one flip flop connected to input of next flip flop. All flip flops receive common clock
pulses which causes the shift in the output of the flip flop. The simplest possible shift register is
one that uses only flip flop. The output of a given flip flop is connected to the input of next flip
flop of the register. Each clock pulse shifts the content of register one bit position to right.
Types of Shift Registers
• Serial In Serial Out shift register
• Serial In parallel Out shift register
• Parallel In Serial Out shift register
• Parallel In parallel Out shift register
• Bidirectional Shift Register
• Universal Shift Register

Fig 10.1A Serial In Serial Out shift register Fig 10.1B Serial In Parallel Out shift

SE [Electronics and Telecommunication] Subject: Digital Circuit

 JSPM’s
JAYWANTRAO SAWANAT COLLEGE OF ENGINEERING
Sr. No. 58, Handewadi Road, Hadapsar, Pune, Maharashtra 411028
Department of Electronics and Telecommunication Engineering

register

Fig 10.1C Parallel In Serial Out shift register Fig 10.1D Parallel In Parallel Out shift
register
Universal Shift Register:
A Universal shift register is a register which has both the right shift and left shift with
parallel load capabilities. Universal shift registers are used as memory elements in computers. A
Unidirectional shift register is capable of shifting in only one direction. A bidirectional shift
register is capable of shifting in both the directions. The Universal shift register is a combination
design of bidirectional shift register and a unidirectional shift register with parallel load provision.

IC 74LS194:
• The 74LS194 are high-speed devices Shift-left and shift-right capability, synchronous
parallel and serial data transfer.
• It has serial/parallel data input and output capability which means that it can function as
SISO, SIPO, PISO and PIPO shift register.
Pin diagram of Universal Shift Register IC74194

74194

Fig 10.2 Pin diagram of universal shift register IC 74LS194

SE [Electronics and Telecommunication] Subject: Digital Circuit

 JSPM’s
JAYWANTRAO SAWANAT COLLEGE OF ENGINEERING
Sr. No. 58, Handewadi Road, Hadapsar, Pune, Maharashtra 411028
Department of Electronics and Telecommunication Engineering

Part A: Functional table verification of shift-register IC74LS194:

• A register may operate in any of the modes, like SISO, SIPO, PISO or bidirectional.
• IC74194 is a 4-bit universal shift register.
• IC74194 has a four parallel data inputs (D0-D3) and S0 & S1 are control inputs.

Function Table for IC74194

Operation Inputs Outputs
Mode ̅̅̅̅̅
CP 𝐌𝐑 S1 S0 DSR DSL Dn QA QB QC QD
Reset(clear) X 0 X X X X X 0 0 0 0
Shift Left 1 1 0 X 0 X Q1 Q2 Q3 0
1 1 0 X 1 X Q1 Q2 Q3 1
Shift Right 1 0 1 0 X X 0 Q0 Q1 Q2
1 0 1 1 X X 1 Q0 Q1 Q2
Parallel load 1 1 1 X X Dn D0 D1 D2 D3
Hold X 1 0 0 X X X Q0 Q1 Q2 Q3

Operation-
Parallel Loading [S1=S0 =1]:- Parallel loading is also accomplished synchronously with Low-to
High clock transitions by applying four bits of data and then driving the mode control input S1&S0
to logic High state.
Data are loaded into corresponding flip-flops and appear at the outputs with Low-High clock
transition. Serial data flow is inhibited (disabled) during parallel loading.
Serial Shift Right Operation[S1=0, S0=1]- Shift right operation is accomplished by setting S1,S0=
01 and serial data is entered at the shift right serial input DSR, parallel data flow is
inhibited(disabled) during serial shift operation.
Hence D0, D1, D2, D3 inputs become ‘don’t care’, Master Reset [MR ̅̅̅̅̅] = 1, FF-A is now serial input,
clock is applied to input, QA is connected to B, QB to C and QC to D and serial data is applied at
input A. Data is serially transferred from QA to QB ,QB to QC and QC to QD.
Serial Shift Left Operation- Shift left operation is accomplished by setting S1 SO=10 and serial
data is entered at the shift left serial input DSL, parallel data flow is inhibited(disabled) during
serial shift operation. Hence A, B, C, D inputs become ‘don’t care’. Mode control is applied to 1.
FF-D is now serial input. Clock is applied to clock input. QD is connected to C, QC to B and QB to A
and serial data is applied to input D.

SE [Electronics and Telecommunication] Subject: Digital Circuit

 JSPM’s
JAYWANTRAO SAWANAT COLLEGE OF ENGINEERING
Sr. No. 58, Handewadi Road, Hadapsar, Pune, Maharashtra 411028
Department of Electronics and Telecommunication Engineering

Part B: Design and implement 4-bit Ring Counter using IC74HC194.

Ring counter:
Ring counter is a basic register with direct feedback such that the contents of the register simply
circulate around the register when the clock is running. Here, the last output that is Q3 in a shift
register is connected back to the serial input (DSR).

QA QB QC QD
(2)
(16) (15) (14) (13) (12) (1)

(11)

(9)
(7)
A B C D
(8) (3) (4) (5) (6) (8)

1 0 0 0

Fig 10.3 Ring counter using universal shift register IC 74LS194

• Truth Table for the Ring Counter:

Clock Pulses QA QB QC QD

1 1 0 0 0
2 0 1 0 0
3 0 0 1 0
4 0 0 0 1
5 1 0 0 0
6 0 1 0 0
7 0 0 1 0
8 0 0 0 1

SE [Electronics and Telecommunication] Subject: Digital Circuit

 JSPM’s
JAYWANTRAO SAWANAT COLLEGE OF ENGINEERING
Sr. No. 58, Handewadi Road, Hadapsar, Pune, Maharashtra 411028
Department of Electronics and Telecommunication Engineering

• Procedure
1. Connect Vcc and ground to the necessary pins.
2. Connect combinational circuit as shown in circuit diagram.
̅̅̅̅̅ = 1, S1=1 and S0=. It will perform parallel load operation.
3. Connect MR
4. Apply A B C D =1000 as it is first count in the sequence
5. Apply clock pulse, we get QA QB QC QD =1000.
6. The output of combinational circuit is connected to DSR pin as shown in fig. (right shift
operation)
̅̅̅̅̅ = 1, S1=0, S0=1, DSL=0. It will make Shift Register in Right Shift Mode.
7. Connect MR
8. Apply the clock pulse and observe the sequence as per truth table.

Part C: Design and implement 4-bit Twisted Ring Counter using IC74HC194.
Twisted Ring counter:
A basic ring counter can be slightly modified to produce another type of shift register counter called
Johnson counter. Here complement of last output is connected back to the not gate input and not
gate output is connected back to serial input (Q3 to DSR). A four-bit Johnson counter gives 8 state
output.

(12) (13) (14) (15)

QQD
A QQC
B QC QD
(16) QB QA
(1)
(2) (15) (14) (13) (12)

(11)

(7) (9)
A B C D
(8) (3) (4) (5) (6)
(8)

Fig 10.4 Circuit diagram of Twisted Ring counter using universal shift register IC 74LS194

Truth Table of twisted ring counter

Clock Pulses QA QB QC QD
1 1 0 0 0
2 1 1 0 0
3 1 1 1 0
4 1 1 1 1

SE [Electronics and Telecommunication] Subject: Digital Circuit

 JSPM’s
JAYWANTRAO SAWANAT COLLEGE OF ENGINEERING
Sr. No. 58, Handewadi Road, Hadapsar, Pune, Maharashtra 411028
Department of Electronics and Telecommunication Engineering

5 0 1 1 1
6 0 0 1 1
7 0 0 0 1
8 0 0 0 0

• Procedure
1. Connect Vcc supply and ground to respective pins.
2. Connect combinational circuit as shown in circuit diagram.
3. Connect MR=1, S1 = 0, S0 = 1, DSL=0. It will make Shift Register in Right Shift Mode.
Connect A, B, C and D pins to ground.
4. Apply the clock pulse and observe the sequence as per truth table.

Part D: Design and implement pulse train generator using IC74HC194 (Use right shift)
Design a pulse train generator using universal shift register for following pulse train 111001
use right shift operation.
From the length of sequence determine the number of flip flops as-
L≤2𝑁 − 1, where L=Length of the sequence
N=Number of flip-flops
The length of sequence L=6
L≤2𝑁 = 2𝑁 ≤ 7
N=3
Thus 3 flip flops are required for following sequence.
State Table-
Here shift right operation is used. So, write sequence under Q0 (MSB) column, and perform shift
operation
Outputs Y=DSR Decimal Equivalent
Clock pulse
QA QB QC
1 1 1 0 1 6
2 1 1 1 1 7
3 1 1 1 0 7
4 0 1 1 0 3
5 0 0 1 1 1
6 1 0 0 1 4

As in the above state table 7 repeats at 2nd and 3rd clock pulse, so 3 flip-flops are not sufficient.
Hence, 4 flip flops are required.

SE [Electronics and Telecommunication] Subject: Digital Circuit

 JSPM’s
JAYWANTRAO SAWANAT COLLEGE OF ENGINEERING
Sr. No. 58, Handewadi Road, Hadapsar, Pune, Maharashtra 411028
Department of Electronics and Telecommunication Engineering

Clock Outputs Decimal

Y=DSR
pulse QA QB QC QD Equivalent
1 1 1 1 0 0 12
2 1 1 1 1 0 14
3 0 1 1 1 1 15
4 0 0 1 1 1 07
5 1 0 0 1 1 03
6 1 1 0 0 1 09
• Design a combinational circuit from given state by K-map.
QC QD
QA QB
00 01 11 10
00

01

11

10

𝐘 = ̅̅̅̅
𝐐𝐁 + ̅̅̅̅
𝐐𝐂 + ̅̅̅̅
𝐐𝐃

• Connection diagram for given sequence using IC74194

•

(2) (16) QA QB QC QD
(15) (14) (13) (12) (1)

(11)

(9)
(7)
(8) A B C D (10)
(3) (4) (5) (6)

1 1 0 0

Fig 10.5 Circuit diagram of Pulse Train Generator using universal shift register IC 74LS194

SE [Electronics and Telecommunication] Subject: Digital Circuit

 JSPM’s
JAYWANTRAO SAWANAT COLLEGE OF ENGINEERING
Sr. No. 58, Handewadi Road, Hadapsar, Pune, Maharashtra 411028
Department of Electronics and Telecommunication Engineering

• Procedure:
1. Connect Vcc and ground pins.
2. Connect MR=1, S1 = 1 and S0 = 1
DSL=0, DSR=0. It will perform parallel load operation.
3. Apply A B C D =1100 as it is first count in the sequence
4. Apply clock pulse we get QA QB QC QD ➔1 1 0 0.
5. Connect combinational circuit as shown in circuit diagram. The output of combinational
circuit is connected to DSR pin as shown in Fig 10.5 (right shift operation)
6. Connect MR=1, S1=0, S0=1, DSL=0. It will make shift Register in Right Shift mode.
7. Apply the clock pulse and observe the sequence as per truth table.

Conclusion:

Relevance to the Industry:

1. The main benefit of this counter is, it requires n-number of FFs evaluated to the ring counter
to move a given data for producing a series of 2n states.
2. A PISO shift register is used for converting parallel to serial data.
3. These registers are used for data transfer, manipulation and data storage.
4. The SIPO register is used for converting serial to parallel data therefore in communication
lines
A register that can store the data and /shifts the data towards the right and
left along with the parallel load capability is known as a universal shift
register. It can be used to perform input/output operations in both serial and
parallel modes. Unidirectional shift registers and bidirectional shift registers
are combined together to get the design of the universal shift register.
https://www.youtube.com/watch?v=UMQP_Hh5vKA

Questions:
Q.1: What is the difference between Ring shift counter & Johnson Counter?
Q.2: What is the use of Master Reset pin [ MR] of universal shift register?
Q.3: What are the output frequencies of 74194?
Q.4: Define universal shift register.
Q.5: What are the types of shift register?

SE [Electronics and Telecommunication] Subject: Digital Circuit