JSPM’s

JAYWANTRAO SAWANAT COLLEGE OF ENGINEERING

Sr. No. 58, Handewadi Road, Hadapsar, Pune, Maharashtra 411028
Department of Electronics and Telecommunication Engineering

Experiment No: 05
Study of Counters

Title: Design and Implement 4-bit counter using JK- Flip flop.

Aim:

A. Design and Implement 4-bit UP counter using JK- Flip flop.

B. Design and Implement 4-bit Down counter using JK- Flip flop.

ELO: Students will be able to ___________________________________________________.

Objective:

1) To study of basics of counter

2) Design and Implement 4-bit UP counter using JK- Flip flop.
3) Design and Implement 4-bit Down counter using JK- Flip flop.

Pre-requisites: Basic knowledge of counters.

Hardware: Digital IC trainer kit, patch cords, power supply, IC 74LS76.

Theory:

A counter is a register capable of counting number of clock pulse arriving at its clock input. Counter
represents the number of clock pulses arrived. A specified sequence of states appears as counter
output. This is the main difference between a register and a counter. The digital circuit used for
counting pulses is known as counter. It is sequential circuit. Counter is widest application of flip-
flops. It is a group of flip-flop with clock signal applied. Counters count number of clock pulses.
Hence with some modifications it can be used for measuring frequency or time period.
Types of Counter:- Counters are basically of 2 types
1) Asynchronous or Ripple Counter
2) Synchronous Counter
1] Asynchronous or Ripple Counter: For these counter the external clock signal is applied to the
one flip-flop and then output of preceding flip-flop is connected to the clock of next flip-flop.
2] Synchronous Counter: In synchronous counter all the flip-flop receives the external clock pulse
simultaneously. e.g.- Ring counter & Johnson counter.
• Classification of Counter:-
Depending on the way in which the counting progresses, the synchronous or asynchronous
counters are classified as follows:

SE [Electronics and Telecommunication] Subject: Digital Circuit Lab

 JSPM’s
JAYWANTRAO SAWANAT COLLEGE OF ENGINEERING
Sr. No. 58, Handewadi Road, Hadapsar, Pune, Maharashtra 411028
Department of Electronics and Telecommunication Engineering

Counters

Up Counters Down Counters Up/Down Counters

1) Up Counters:-up counters are the counters that count from small to big count. Their output
goes on increasing as they receive clock pulses.

e.g.-the output of up counter will be 0→1→2→3→4→

2) Down Counter:-down counter are the counter that counts large to small count. Their output
goes on decreasing as they clock pulse.
e.g.-the output of down counter will be 7→6→5→4→
3) Up-Down Counter:-up-down counter is a combination of up counter& down counter.

Part A: Design and Implement 4-bit UP counter using JK- Flip flop.

The 4 bit up counter shown in below diagram is designed by using JK flip flop. External clock pulse
is connected to all the flip flops in parallel. For designing the counters JK flip flop is preferred. The
significance of using JK flip flop is that it can toggle its state if both the inputs are high, depending
on the clock pulse. The inputs of first flip flop are connected to HIGH (logic 1), which makes the
flip flop to toggle, for every clock pulse entered into it. So the synchronous counter will work with
single clock signal and changes its state with each pulse

4 Bit synchronous Up counter

SE [Electronics and Telecommunication] Subject: Digital Circuit Lab

 JSPM’s
JAYWANTRAO SAWANAT COLLEGE OF ENGINEERING
Sr. No. 58, Handewadi Road, Hadapsar, Pune, Maharashtra 411028
Department of Electronics and Telecommunication Engineering

The output of first JK flip flop (Q) is connected to the input of second flip flop. The AND gates
(which are connected externally) drives the inputs of other two flip flops. The inputs of these AND
gates, are supplied from previous stage lip flop outputs.

Working can be explained in the below table. The above-mentioned working of synchronous counter
can be clearly given in the below table.

In the up counter the 4 bit binary sequence starts from 0000 and increments up to 1111.Before
understanding the working of the above up counter circuit know about JK Flip flop.

In the above circuit as the two inputs of the flip flop are wired together. So , there are only two
possible conditions that can occur, that is, either the two inputs are high or low.

If the two inputs are high then JK flip-flop toggles and if both are low JK flip flop remembers i.e. it
stays in the previous state.

Let us see the operation. Here clock pulse indicates edge triggered clock pulse.

Operation:

1) In the first clock pulse, the outputs of all the flip flops will be at 0000.

2)In the second clock pulse, as inputs of J and k are connected to the logic high, output of JK flip
flop(FF0) change its state .Thus the output of the first flip-flop(FF0) changes its state for every
clock pulse .This can be observed in the above shown sequence .The LSB changes its state
alternatively. Thus producing -0001

3) In the third clock pulse next flip flop (FF1) will receive its J K inputs i.e (logic high) and it
changes its state. At this state FF0 will change its state to 0. And thus input on the FF1 is 0.Hence
output is -0010

4) Similarly, in the fourth clock pulse FF1 will not change its state as its inputs are in low state, it
remains in its previous state. Though it produces the output to FF2, it will not change its state due
to the presence of AND gate. FF0 will again toggle its output to logic high state. Thus Output is
0011.

5) In the fifth clock pulse, FF2 receives the inputs and changes its state. While, FF0 will have low
logic on its output and FF1 will also be low state producing 0100.

This process continuous up to 1111.Working can be explained in the below table. The above
mentioned working of synchronous counter can be clearly given in the below table.

SE [Electronics and Telecommunication] Subject: Digital Circuit Lab

 JSPM’s
JAYWANTRAO SAWANAT COLLEGE OF ENGINEERING
Sr. No. 58, Handewadi Road, Hadapsar, Pune, Maharashtra 411028
Department of Electronics and Telecommunication Engineering

The below table shows the outputs of 4 flip flops Q1, Q2, Q3, Q4.The first flip-flop toggles on
every edge triggered pulse .While the second one triggers only if its inputs are high at a given
clock pulse. The third flip-flop toggles if the two ouputs Q1 and Q2 are high. Similarly, Q4 will
toggle if all the three Q1,Q2,Q3 are high.

Operation Table:

After reaching zero again the three flip flops toggles to logic low i.e 0000 and again count starts.
Timing diagram for up counter is shown below.

Part B: Design and Implement 4-bit DOWN counter using JK- Flip flop.

SE [Electronics and Telecommunication] Subject: Digital Circuit Lab

 JSPM’s
JAYWANTRAO SAWANAT COLLEGE OF ENGINEERING
Sr. No. 58, Handewadi Road, Hadapsar, Pune, Maharashtra 411028
Department of Electronics and Telecommunication Engineering

Down counter counts the numbers in decreasing order. This is similar to an up counter but is
should decrease its count. So inputs of JK flip- flop are connected to the inverted Q (Q’) .The 4 bit
down counter shown in below diagram is designed by using JK flip flop. The same external clock
pulse is connected to all the flip flops.

As the counter has to count down the sequence, initially all the inputs will be in high state as they
have to count down the sequence. It will start with 1111 and ends with 0000, similar to the up
counter.

In the down counter it should be remembered that, preceding flip flop will toggles only if front flip
flop produces low logic at its output.

Conclusion:

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SE [Electronics and Telecommunication] Subject: Digital Circuit Lab

 JSPM’s
JAYWANTRAO SAWANAT COLLEGE OF ENGINEERING
Sr. No. 58, Handewadi Road, Hadapsar, Pune, Maharashtra 411028
Department of Electronics and Telecommunication Engineering

Relevance to the Industry:

1. The main application of counter is to count events, and each event is converted in to one clock
cycle. That means counter is used to count number of clocks
2. Counters can have many different functions for count, control, and time monitoring. These
include arithmetic functions, controller, batch counter, count totalizer, event counter, preset,
pulse counter, delay cycle, position indicator, rate meters or tachometers, and time meters.
Reset capability can be none, manual, remote or auto reset (model dependent).
3. It used in in time measurement. That means calculating time in timers such as electronic
devices like ovens and washing machines.
4. We can design digital triangular wave generator by using counters.

Its pleasure to bring to your attention the following design

of 4 bit up counter using JK flip-flop
https://www.youtube.com/watch?v=EY66uqAn6Ns

Questions:
1. What is the function of a JK flip-flop in a 4-bit counter design?
2. How many JK flip-flops are required to design a 4-bit binary counter?
3. Explain the role of the clock signal in the operation of a JK flip-flop-based counter.
4. What is the significance of the "J" and "K" inputs in a JK flip-flop?
5. How does a JK flip-flop differ from a D flip-flop in counter design?

SE [Electronics and Telecommunication] Subject: Digital Circuit Lab