03 Circuit-Basic
03 Circuit-Basic
+
−
− + +
− −
The Circuit Abstraction
i
+
+
v
−
−
ri (t) ri ro
+
P = ρgh
h(t) −
ro (t)
# of transistors
Dual-Core Itanium 2
1,000,000,000
Itanium 2
Itanium
100,000,000
Pentium 4
Pentium III
Pentium II 10,000,000
Pentium
80486 1,000,000
80386
80286 100,000
8086
10,000
8080
8008
4004
1,000
1970 1980 1990 2000 2010
year
+
P = ρgh
h(t) −
ro (t)
i i i
+ + +
+
R v V0 v I0 v
−
− − −
v = iR v = V0 i = −I0
Analyzing Simple Circuits
Analyzing simple circuits is straightforward.
Example 1:
i
+1V 1Ω v
Example 2:
i
+1A 1Ω v
+1V 1Ω v +1A
1. 1A
2. 2A
3. 0A
4. cannot determine
5. none of the above
Check Yourself
+1V 1Ω v +1A
The voltage source forces the voltage across the resistor to be 1V.
Therefore, the current through the resistor is 1V/1Ω = 1A.
+1V 1Ω v +1A
If all of the current from current source flowed through the resistor,
then it would generate 1V across the resistor.
The current source supplies all of the current through the resistor!
Check Yourself
+1V 1Ω v +1A
1. 1A
2. 2A
3. 0A
4. cannot determine
5. none of the above
Analyzing More Complex Circuits
KVL: The sum of the voltages around any closed path is zero.
+ +
+ v2 v3
+ − −
v1 = V 0
− + v6 −
− + +
v4 v5
− −
Analyzing Circuits: KVL
KVL: The sum of the voltages around any closed path is zero.
+ +
+ v2 v3
+ − −
v1 = V 0
− + v6 −
− + +
v4 v5
− −
+ +
+ v2 v3
+ − −
v1 = V 0
− + v6 −
− + +
v4 v5
− −
1. 3 2. 4 3. 5 4. 6 5. 7
Check Yourself
+ +
+ v2 v3
B
+ − −
v1 = V 0
− + v6 −
− + +
v4 v5
A C
− −
A : −v1 + v2 + v4 = 0
B : −v2 + v3 − v6 = 0
C : −v4 + v6 + v5 = 0
Check Yourself
+ +
+ v2 v3
+ − −
v1 = V 0
− + v6 −
− + +
v4 v5
D
− −
D : −v1 + v3 − v6 + v4 = 0
Check Yourself
+ +
+ v2 v3
+ − −
v1 = V 0
− + v6 −
− + +
v4 v5
E
− −
E : −v1 + v2 + v6 + v5 = 0
Check Yourself
+ +
+ v2 v3
+ − −
v1 = V 0
− + v6 −
− + +
v4 v5
F
− −
F : −v4 − v2 + v3 + v5 = 0
Check Yourself
+ +
+ v2 v3
+ − −
v1 = V 0
− + v6 −
− + +
v4 v5
G
− −
G : −v1 + v3 + v5 = 0
Check Yourself
A : − v 1 + v2 + v4 = 0
B : − v2 + v3 − v6 = 0
C : − v4 + v6 + v5 = 0
D : − v1 + v3 − v6 + v4 = 0
E : − v1 + v2 + v6 + v5 = 0
F : − v4 − v 2 + v 3 + v 5 = 0
G : − v1 + v 3 + v 5 = 0
+ +
+ v2 v3
+ − −
v1 = V 0
− + v6 −
− + +
v4 v5
− −
1. 3 2. 4 3. 5 4. 6 5. 7
+ +
+ v2 v3
B
+ − −
v1 = V 0
− + v6 −
− + +
v4 v5
A C
− −
A : −v1 + v2 + v4 = 0
B : −v2 + v3 − v6 = 0
C : −v4 + v6 + v5 = 0
Analyzing Circuits: KVL
+ +
+ v2 v3
+ − −
v1 = V 0
− A+B
+ v6 −
− + +
v4 v5
− −
A : −v1 + v2 + v4 = 0
B : −v2 + v3 − v6 = 0
A+B : −v1 + v2 + v4 − v2 + v3 − v6 = −v1 + v3 − v6 + v4 = 0
KVL: Summary
One KVL equation can be written for every closed path in a circuit.
KCL equations for the “inner” loops of planar circuits are linearly
independent.
Kirchhoff’s Current Law
→ i2
i1 →
→i
3
Current i1 flows into a node and two currents i2 and i3 flow out:
i1 = i2 + i3
Kirchhoff’s Current Law
The net flow of electrical current into (or out of) a node is zero.
i1 i2 i3
i1 i2 i3
i4 i5 i6
i1 = i4
i2 = i5
i3 = i6
1. 1 2. 2 3. 3 4. 4 5. 5
Check Yourself
How many linearly independent KCL equations can be written for
the following circuit?
i2 i2
i1 i3 i4
i1 i3 i4
1. 1 2. 2 3. 3 4. 4 5. 5
Check Yourself
i2 i3
i1
+ i6
− i4 i5
1. 3 2. 4 3. 5 4. 6 5. 7
Check Yourself
A
i2 i3
i1
+ B i6 C
− i4 i5
D
A: i1 + i2 + i3 = 0
B: −i2 + i4 + i6 = 0
C: −i6 − i3 + i5 = 0
D: i1 + i4 + i5 = 0
Check Yourself
1: i 1 + i2 + i3 = 0
2: −i2 + i4 + i6 = 0
3: −i6 − i3 + i5 = 0
4: i 1 + i4 + i5 = 0
i1 + (i4 + i6 ) + (i5 − i6 ) = i1 + i4 + i5
This is equation 4!
i2 i3
i1
+ i6
− i4 i5
1. 3 2. 4 3. 5 4. 6 5. 7
Analyzing Circuits: KCL
i2 i3
i1
+ i6
− i4 i5
The net current out of any closed surface (which can contain mul
tiple nodes) is zero.
i2 i3
i1
+ i6
− i4 i5
node 1: i 1 + i2 + i3 = 0
Analyzing Circuits: KCL
The net current out of any closed surface (which can contain mul
tiple nodes) is zero.
i2 i3
i1
+ i6
− i4 i5
node 1: i 1 + i2 + i3 = 0
node 2: − i 2 + i4 + i6 = 0
Analyzing Circuits: KCL
The net current out of any closed surface (which can contain mul
tiple nodes) is zero.
i2 i3
i1
+ i6
− i4 i5
node 1: i 1 + i2 + i3 = 0
node 2: − i 2 + i4 + i6 = 0
nodes 1+2: i1 + i2 + i3 − i2 + i4 + i6 = i1 + i3 + i4 + i6 = 0
Analyzing Circuits: KCL
The net current out of any closed surface (which can contain mul
tiple nodes) is zero.
i2 i3
i1
+ i6
− i4 i5
nodes 1+2: i1 + i2 + i3 − i2 + i4 + i6 = i1 + i3 + i4 + i6 = 0
node 3: − i 3 − i6 + i 5 = 0
Analyzing Circuits: KCL
The net current out of any closed surface (which can contain mul
tiple nodes) is zero.
i2 i3
i1
+ i6
− i4 i5
nodes 1+2: i1 + i3 + i4 + i6 = 0
node 3: − i 3 − i6 + i 5 = 0
nodes 1+2+3: i1 + i3 + i4 + i6 − i3 − i6 + i5 = i1 + i4 + i5 = 0
Analyzing Circuits: KCL
The net current out of any closed surface (which can contain mul
tiple nodes) is zero.
i2 i3
i1
+ i6
− i4 i5
nodes 1+2: i1 + i3 + i4 + i6 = 0
node 3: − i 3 − i6 + i 5 = 0
nodes 1+2+3: i1 + i3 + i4 + i6 − i3 − i6 + i5 = i1 + i4 + i5 = 0
Net current out of nodes 1+2+3 = net current into bottom node!
KCL: Summary
One KCL equation can be written for every closed surface (which
contain one or more nodes) in a circuit.
KCL equations for every primitive node except one (ground) are
linearly independent.
KVL, KCL, and Constitutive Equations
i2 i3
i1 + +
+ v2 v3
+ − i6 −
v1 = V 0
− i4 + v6 − i 5
− + +
v4 v5
− −
KVL, KCL, and Constitutive Equations
i2 i3
i1 + +
+ v2 v3
+ − i6 −
v1 = V 0
− i4 + v6 − i 5
− + +
v4 v5
− −
12 unknowns: v1 , v2 , v3 , v4 , v5 , v6 , i1 , i2 , i3 , i4 , i5 and i6 .
V0
KCL at e1 :
R2 R3 e1 − V0 e1 − e2 e1
R6 + + =0
+ R2 R6 R4
V0 e1 e2
−
KCL at e2 :
R4 R5 e2 − V0 e2 − e1 e2
+ + =0
R3 R6 R5
gnd
loop a:
R2 R3 −V0 + R2 (ia − ib ) + R4 (ia − ic ) = 0
ib R6
+ loop b:
V0
− R2 (ib − ia ) + R3 (ib ) + R6 (ib − ic ) = 0
R4 R5
ia ic loop c:
R4 (ic − ia ) + +R6 (ic − ib ) + R5 (ic ) = 0
3Ω
+15 V 2Ω +10 A
1. 1 A 2. 53 A 3. −1 A 4. −5 A
5. none of the above
Check Yourself
Node method:
I e
3Ω
+15 V 2Ω +10 A
KCL at node e:
e − 15 e 5
+ = 10 → e = 15 → e = 18
3 2 6
15 − 18
I= = −1 A
3
Check Yourself
Loop method:
3Ω
I
I 10
+15 V 2Ω +10 A
3Ω
+15 V 2Ω +10 A
1. 1 A 2. 53 A 3. −1 A 4. −5 A
5. none of the above
Common Patterns
i +
v
−
A one-port has two terminals. Current enters one terminal (+) and
exits the other (−), producing a voltage (v) across the terminals.
Series Combinations
i i
+ +
R1
v R2 v Rs
− −
v = R1 i + R2 i v = Rs i
Rs = R1 + R2
i i
+ +
v R1 R2 v Rp
− −
v v v
i= + i=
R1 R2 Rp
1 1 1 R1 + R2 1 R1 R2
= + = → Rp = 1 1 = ≡ R1 ||R2
Rp R1 R2 R1 R2 R1 + R2
R1 + R2
1 1
2 1
1. 0.5 2. 1 3. 2 4. 3 5. 5
Check Yourself
1 1 1
2 1 2 2
2 2 1 2
Check Yourself
1 1
2 1
1. 0.5 2. 1 3. 2 4. 3 5. 5
Voltage Divider
R1 V1
R2 V2
V
I=
R1 + R2
R1
V1 = R1 I = V
R 1 + R2
R2
V2 = R2 I = V
R 1 + R2
Current Divider
I
I1 I2
V
R1 R2
V = (R1 ||R2 ) I
V R1 ||R2 1 R1 R2 R2
I1 = = I= I= I
R1 R1 R1 R1 + R2 R1 + R2
V R1 ||R2 1 R1 R2 R1
I2 = = I= I= I
R2 R2 R2 R1 + R2 R1 + R2
Check Yourself
1Ω 3Ω
15V 12Ω 6Ω Vo
1. Vo ≤ 3V
2. 3V< Vo ≤ 6V
3. 6V< Vo ≤ 9V
4. 9V< Vo ≤ 12V
5. Vo > 12V
Check Yourself
1Ω 3Ω
15V 12Ω 6Ω Vo
Add the top two resistances to get the series equivalent: 4Ω.
12Ω × 6Ω
Then find the parallel equivalent: = 4Ω.
12Ω + 6Ω
4Ω
15V 4Ω Vo
4Ω
Now apply the voltage divider relation: Vo = × 15V = 7.5V.
4Ω + 4Ω
Check Yourself
1Ω 3Ω
15V 12Ω 6Ω Vo
1. Vo ≤ 3V
2. 3V< Vo ≤ 6V
3. 6V< Vo ≤ 9V
4. 9V< Vo ≤ 12V
5. Vo > 12V
Summary