Pca 9548 A

PCA9548A
ZHCSJK4G – JUNE 2009 – REVISED MARCH 2021
支持复位的 PCA9548A 低电压 8 通道 I2C 开关

通道。根据可编程控制寄存器的内容，可选择任一单独
1 特性
的 SCx/SDx 通道或者通道组合。这些下游通道可用于
• 8 选 1 双向转换开关解决 I2C 从器件地址冲突。例如，如果应用中需要八个
• 与 I2C 总线和系统管理总线 (SMBus) 兼容完全相同的数字温度传感器，则每个通道 (0-7) 可以连
• 低电平有效复位输入接一个传感器。
• 三个硬件地址引脚允许在 I2C 总线上使用多达八个
发生超时或其他不当操作时，系统主控器可通过将
PCA9548A 器件
RESET 输入置为低电平来复位 PCA9548A。同样，上
• 通过 I2C 总线实现通道选择
电复位即可取消选中所有通道并初始化 I2C/SMBus 状
• 加电时所有开关通道取消选定
态机。将 RESET 置为有效也可实现复位和初始化，并
• 低 RON 开关
且无需将部件断电。这样可以在下游 I2C 总线卡在低电
• 支持 1.8V、2.5V、3.3V 和 5V 总线间的电压电平转
平状态时进行恢复。
换
• 加电时无干扰由于开关上有导通栅极，因此 VCC 引脚可用于限制将
• 支持热插入由 PCA9548A 传递的最大电压。这样就可以在每个对
• 低待机电流上使用不同的总线电压，从而让 1.8V、2.5V 或 3.3V
• 工作电源电压范围为 2.3V 至 5.5V 部件能够在没有任何额外保护的情况下与 5V 部件通
• 5V 耐压输入信。对于每个通道，外部上拉电阻器将总线电压上拉至
• 0kHz 至 400kHz 时钟频率所需的电压水平。所有 I/O 引脚均可承受 5V 电压。
• 闩锁性能超过 100mA，符合 JESD 78 II 类规范的
要求器件信息
• ESD 保护性能超过 JESD 22 规范要求器件名称封装(1) 封装尺寸（标称值）
– 2000V 人体放电模型 (A114-A) SSOP (24) 8.20mm × 5.30mm
– 200V 机器放电模型 (A115-A) TVSOP (24) 5.00mm × 4.40mm

– 1000V 带电器件模型 (C101) PCA9548A SOIC (24) 15.40mm × 7.50mm
TSSOP (24) 7.80mm × 4.40mm
2 应用
VQFN (24) 4.00mm × 4.00mm
• 服务器
• 路由器（电信交换设备） (1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
• 工厂自动化
• 具有 I2C 从地址冲突的产品（例如，多个完全一样
的温度传感器）
3 说明
PCA9548A 器件配有八个可通过 I2C 总线控制的双向
转换开关。SCL/SDA 上行对扩展到八个下行对，或者
VCC Channel 0
SDA SD0 Slaves A0, A1...AN
SCL SC0
I2C or SMBus
Master
(processor) Channel 1
SD1 Slaves B0, B1...BN
RESET SC1
PCA9548A
Channel 2
SD2 Slaves C0, C1...CN
SC2
A0
A1
A2 Channel 7
GND SD7 Slaves H0, H1...HN
SC7
简化版原理图
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SCPS143
PCA9548A
ZHCSJK4G – JUNE 2009 – REVISED MARCH 2021 www.ti.com.cn
Table of Contents
1 特性................................................................................... 1 8.4 Device Functional Modes..........................................15
2 应用................................................................................... 1 8.5 Programming............................................................ 15
3 说明................................................................................... 1 8.6 Register Maps...........................................................16
4 Revision History.............................................................. 2 9 Application Information Disclaimer............................. 20
5 Pin Configuration and Functions...................................3 9.1 Application Information............................................. 20
6 Specifications.................................................................. 5 9.2 Typical Application.................................................... 20
6.1 Absolute Maximum Ratings........................................ 5 10 Power Supply Recommendations..............................24
6.2 ESD Ratings............................................................... 5 10.1 Power-On Reset Requirements.............................. 24
6.3 Recommended Operating Conditions.........................5 11 Layout........................................................................... 26
6.4 Thermal Information....................................................5 11.1 Layout Guidelines................................................... 26
6.5 Electrical Characteristics.............................................6 11.2 Layout Example...................................................... 27
6.6 I2C Interface Timing Requirements.............................8 12 Device and Documentation Support..........................28
6.7 Reset Timing Requirements........................................9 12.1 Related Documentation.......................................... 28
6.8 Switching Characteristics............................................9 12.2 Receiving Notification of Documentation Updates..28
6.9 Typical Characteristics.............................................. 10 12.3 Support Resources................................................. 28
7 Parameter Measurement Information.......................... 11 12.4 Trademarks............................................................. 28
8 Detailed Description......................................................13 12.5 Electrostatic Discharge Caution..............................28
8.1 Overview................................................................... 13 12.6 Glossary..................................................................28
8.2 Functional Block Diagram......................................... 14 13 Mechanical, Packaging, and Orderable
8.3 Feature Description...................................................14 Information.................................................................... 28
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision F (April 2019) to Revision G (March 2021) Page
• Changed the PW and RGE package values in the Thermal Information. ..........................................................5
• Changed the VPORR row in the Electrical Characteristics .................................................................................. 6
• Added VPORF row to the Electrical Characteristics ............................................................................................ 6
• Changed the ICC Low inputs and High inputs values in the Electrical Characteristics .......................................6
• Changed the Power Supply Recommendations .............................................................................................. 24
Changes from Revision E (February 2015) to Revision F (April 2019) Page

• 更新了节 3 部分.................................................................................................................................................. 1
• Changed the Pin Configuration images.............................................................................................................. 3
• Updated Pin Name for Pin 8 From: SC2 To: SD2 in the Pin Functions table..................................................... 3
• Added the Typical Characteristics section........................................................................................................ 10
Changes from Revision D (June 2014) to Revision E (February 2015) Page

• 更改了首页图...................................................................................................................................................... 1
• Added Thermal Information. .............................................................................................................................. 5
• Changed Note (2) in the Electrical Characteristics ............................................................................................. 6
• Added Layout Example.....................................................................................................................................27
Changes from Revision C (June 2007) to Revision D (June 2014) Page

• Added RESET Errata section........................................................................................................................... 15
• Updated Typical Application schematic. .......................................................................................................... 20
2 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: PCA9548A

PCA9548A
www.ti.com.cn ZHCSJK4G – JUNE 2009 – REVISED MARCH 2021
5 Pin Configuration and Functions
A0 1 24 VCC
A1 2 23 SDA
RE SET 3 22 SCL
SD0 4 21 A2
SC0 5 20 SC7
SD1 6 19 SD7
SC1 7 18 SC6
SD2 8 17 SD6
SC2 9 16 SC5
SD3 10 15 SD5
SC3 11 14 SC4
GND 12 13 SD4
No t to scale
图 5-1. DB, DGV, DW or PW Package, 24-Pin SSOP, TVSOP, SOIC or TSSOP , Top View
表 5-1. Pin Functions

PIN
NO.
I/O DESCRIPTION
NAME DB, DW, DGV ,
PW
A0 1 I Address input 0. Connect directly to VCC or ground
RESET 3 I Active-low reset input. Connect to VCC through a pull-up resistor, if not used
SD0 4 I/O Serial data 0. Connect to VCC through a pull-up resistor
SC0 5 I/O Serial clock 0. Connect to VCC through a pull-up resistor
GND 12 — Ground
SCL 22 I/O Serial clock bus. Connect to VCC through a pull-up resistor
SDA 23 I/O Serial data bus. Connect to VCC through a pull-up resistor
VCC 24 — Supply voltage
Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 3

PCA9548A
RE SET
SDA
SCL
VCC
A1
A0
24
23
21
20
19
22
SD0 1 18 A2
SC0 2 17 SC7
SD1 3 16 SD7
Th ermal
SC1 4 Pad 15 SC6
SD2 5 14 SD6
SC2 6 13 SC5
10
11
12
7
9
GND
SD3
SC3
SD4
SC4
SD5
No t to scale
图 5-2. RGE Package, 24-Pin VQFN , Top View
表 5-2. Pin Functions, RGE

PIN
I/O DESCRIPTION
NAME NO.
GND 9 — Ground
SCL 19 I/O Serial clock bus. Connect to VCC through a pull-up resistor
SDA 20 I/O Serial data bus. Connect to VCC through a pull-up resistor
VCC 21 — Supply voltage
RESET 24 I Active-low reset input. Connect to VCC through a pull-up resistor, if not used

PCA9548A
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
VCC Supply voltage –0.5 7 V
VI Input voltage(2) –0.5 7 V
II Input current –20 20 mA
IO Output current –25 25 mA
ICC Supply current –100 100 mA
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
6.2 ESD Ratings

VALUE UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000
Electrostatic
V(ESD) Charged-device model (CDM), per JEDEC specification JESD22-C101 or ±1000 V
discharge
ANSI/ESDA/JEDEC JS-002(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions

See (1)
MIN MAX UNIT
VCC Supply voltage 2.3 5.5 V
SCL, SDA 0.7 × VCC 6
VIH High-level input voltage V
A2–A0, RESET 0.7 × VCC VCC + 0.5
SCL, SDA –0.5 0.3 × VCC
VIL Low-level input voltage V
A2–A0, RESET –0.5 0.3 × VCC
TA Operating free-air temperature –40 85 °C
(1) All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. See the Implications of Slow or
Floating CMOS Inputs application report.
6.4 Thermal Information

PCA9548A
THERMAL METRIC(1) DB (SSOP) DGV (TVSOP) DW (SOIC) PW (TSSOP) RGE (VQFN) UNIT
24 PINS
RθJA Junction-to-ambient thermal resistance 89.1 99.6 73.2 108.8 57.2 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 51.1 31.1 41.3 54.1 62.5 °C/W
RθJB Junction-to-board thermal resistance 46.6 53.1 42.9 62.7 34.4 °C/W
ψJT Junction-to-top characterization parameter 18.5 0.9 15.3 10.9 3.8 °C/W
ψJB Junction-to-board characterization parameter 46.3 52.6 42.6 62.3 34.4 °C/W

PCA9548A
6.4 Thermal Information (continued)

PCA9548A
THERMAL METRIC(1) DB (SSOP) DGV (TVSOP) DW (SOIC) PW (TSSOP) RGE (VQFN) UNIT
24 PINS
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A N/A N/A 15.5 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics

VCC = 2.3 V to 3.6 V, over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP(1) MAX UNIT
VPORR Power-on reset voltage, VCC rising No load, VI = VCC or GND 1.2 1.5 V
VPORF Power-on reset voltage, VCC falling(2) No load, VI = VCC or GND 0.8 1 V
5V 3.6
4.5 V to 5.5 V 2.6 4.5
3.3 V 1.9
Vo(sw) Switch output voltage Vi(sw) = VCC, ISWout = –100 μA V
3 V to 3.6 V 1.6 2.8
2.5 V 1.5
2.3 V to 2.7 V 1.1 2
VOL = 0.4 V 3 6
IOL SDA 2.3 V to 5.5 V mA
VOL = 0.6 V 6 9
SCL, SDA –1 1
SC7–SC0, SD7–SD0 –1 1
II VI = VCC or GND 2.3 V to 5.5 V μA
A2–A0 –1 1
RESET –1 1
5.5 V 50 80
fSCL = 400 kHz VI = VCC or GND, IO = 0 3.6 V 20 35
2.7 V 11 20
Operating mode
5.5 V 9 30
fSCL = 100 kHz VI = VCC or GND, IO = 0 3.6 V 6 15
2.7 V 4 8
ICC μA
5.5 V 0.2 2
Low inputs VI = GND, IO = 0 3.6 V 0.1 2
2.7 V 0.1 1
Standby mode
5.5 V 0.2 2
High inputs VI = VCC, IO = 0 3.6 V 0.1 2
2.7 V 0.1 1
SCL or SDA input at 0.6 V,
3 20
Supply-current Other inputs at VCC or GND
ΔICC SCL, SDA 2.3 V to 5.5 V μA
change SCL or SDA input at VCC – 0.6 V,
3 20
Other inputs at VCC or GND
A2–A0 4 5
VI = VCC or GND
Ci RESET 2.3 V to 5.5 V 4 5 pF
SCL VI = VCC or GND, Switch OFF 20 28
SDA 20 28
Cio(off) (3) VI = VCC or GND, Switch OFF 2.3 V to 5.5 V pF
SC7–SC0, SD7–SD0 5.5 7.5

PCA9548A
6.5 Electrical Characteristics (continued)

VCC = 2.3 V to 3.6 V, over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP(1) MAX UNIT
4.5 V to 5.5 V 4 10 20
VO = 0.4 V, IO = 15 mA
RON Switch-on resistance 3 V to 3.6 V 5 12 30 Ω
VO = 0.4 V, IO = 10 mA 2.3 V to 2.7 V 7 15 45
(1) All typical values are at nominal supply voltage (2.5-, 3.3-, or 5-V VCC), TA = 25°C.
(2) The power-on reset circuit resets the I2C bus logic with VCC < VPORF.
(3) Cio(ON) depends on internal capacitance and external capacitance added to the SCn lines when channels(s) are ON.

PCA9548A
6.6 I2C Interface Timing Requirements

over recommended operating free-air temperature range (unless otherwise noted) (see 图 7-1)
MIN MAX UNIT
STANDARD MODE
fscl I2C clock frequency 0 100 kHz
tsch I2C clock high time 4 μs
tscl I2C clock low time 4.7 μs
tsp I2C spike time 50 ns
tsds I2C serial-data setup time 250 ns
tsdh I2C serial-data hold time 0(1) μs
ticr I2C input rise time 1000 ns
ticf I2C input fall time 300 ns
tocf I2C output (SDn) fall time (10-pF to 400-pF bus) 300 ns
tbuf I2C bus free time between stop and start 4.7 μs
tsts I2C start or repeated start condition setup 4.7 μs
tsth I2C start or repeated start condition hold 4 μs
tsps I2C stop condition setup 4 μs
tvdL(Data) Valid-data time (high to low)(3) SCL low to SDA output low valid 1 μs
tvdH(Data) Valid-data time (low to high)(3) SCL low to SDA output high valid 0.6 μs
ACK signal from SCL low
tvd(ack) Valid-data time of ACK condition 1 μs
to SDA output low
Cb I2C bus capacitive load 400 pF
FAST MODE
fscl I2C clock frequency 0 400 kHz
tsch I2C clock high time 0.6 μs
tscl I2C clock low time 1.3 μs
tsp I2C spike time 50 ns
tsds I2C serial-data setup time 100 ns
tsdh I2C serial-data hold time 0(1) μs
20 + 0.1Cb
ticr I2C input rise time (2) 300 ns
20 + 0.1Cb
ticf I2C input fall time (2) 300 ns
20 + 0.1Cb
tocf I2C output (SDn) fall time (10-pF to 400-pF bus) (2) 300 ns
tbuf I2C bus free time between stop and start 1.3 μs
tsts I2C start or repeated start condition setup 0.6 μs
tsth I2C start or repeated start condition hold 0.6 μs
tsps I2C stop condition setup 0.6 μs
tvdL(Data) Valid-data time (high to low)(3) SCL low to SDA output low valid 1 μs
tvdH(Data) Valid-data time (low to high)(3) SCL low to SDA output high valid 0.6 μs
ACK signal from SCL low
tvd(ack) Valid-data time of ACK condition 1 μs
to SDA output low
Cb I2C bus capacitive load 400 pF
(1) A device internally must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH min of the SCL signal), to bridge
the undefined region of the falling edge of SCL.
(2) Cb = total bus capacitance of one bus line in pF.
(3) Data taken using a 1-kΩ pull-up resistor and 50-pF load (see 图 7-2).

PCA9548A
6.7 Reset Timing Requirements

over recommended operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
tW(L) Pulse duration, RESET low 6 ns
tREC(STA) Recovery time from RESET to start 0 ns
6.8 Switching Characteristics

over recommended operating free-air temperature range, CL ≤ 100 pF (unless otherwise noted) (see 图 7-1)
FROM TO
PARAMETER MIN MAX UNIT
(INPUT) (OUTPUT)
RON = 20 Ω, CL = 15 pF SDA or SCL SDn or SCn 0.3
tpd (1) Propagation delay time ns
RON = 20 Ω, CL = 50 pF SDA or SCL SDn or SCn 1
trst (2) RESET time (SDA clear) RESET SDA 500 ns
(1) The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load
capacitance, when driven by an ideal voltage source (zero output impedance).
(2) trst is the propagation delay measured from the time the RESET pin is first asserted low to the time the SDA pin is asserted high,
signaling a stop condition. It must be a minimum of tWL.

PCA9548A
6.9 Typical Characteristics

25 1.8
Standard-mode
Fast-mode 1.6
20 1.4
1.2
Rp(max) (kOhm)
Rp(min) (kOhm)
15
1
0.8
10
0.6
0.4
5
0.2 VDPUX > 2V
VDPUX <= 2
0 0
0 50 100 150 200 250 300 350 400 450 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5
Cb (pF) VDPUX (V) D009
D008
Standard-mode (fSCL = 100 Fast-mode (fSCL= 400 kHz, tr VOL = 0.2*VDPUX, IOL = 2 mA when VDPUX ≤ 2 V
kHz, tr = 1 µs) = 300 ns) VOL = 0.4 V, IOL = 3 mA when VDPUX > 2 V
图 6-1. Maximum Pull-Up Resistance (Rp(max)) vs Bus 图 6-2. Minimum Pull-Up Resistance (Rp(min)) vs Pull-Up
Capacitance (Cb) Reference Voltage (VDPUX)

PCA9548A
7 Parameter Measurement Information

VCC
R L = 1 kW
SDA
DUT
CL = 50 pF
(see Note A)
SDA LOAD CONFIGURATION
Three Bytes for Complete

Device Programming
Stop Start Address R/W Data Data Stop

ACK
Condition Condition Bit 7 Address Address
Bit 0 Bit 7 Bit 0 Condition
Bit 6 Bit 1 (A)
(P) (S) (MSB) (LSB) (MSB) (LSB) (P)
tscl tsch
0.7 ´ VCC
SCL
0.3 ´ VCC
ticr tvd(ack) tsts
tbuf ticf tsp
tvdH(Data)
0.7 ´ VCC
SDA
0.3 ´ VCC
ticr tvdL(Data)
ticf tsdh tsps
tsth tsds Repeat Start
Condition Stop
Start or Condition
Repeat Start
Condition
VOLTAGE WAVEFORMS
BYTE DESCRIPTION
2
1 I C address
2, 3 P-port data
A. CL includes probe and jig capacitance.

B. All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
C. Not all parameters and waveforms are applicable to all devices.
图 7-1. I2C Load Circuit and Voltage Waveforms

PCA9548A
VCC
RL = 1 kW
SDA
DUT
CL = 50 pF
(see Note A)
SDA LOAD CONFIGURATION
Start
SCL ACK or Read Cycle
SDA
0.3 VCC
tRESET
RESET VCC/2
tREC
tw
SDn, SCn
0.3 VCC
tRESET
A. CL includes probe and jig capacitance.
B. All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
C. I/Os are configured as inputs.
D. Not all parameters and waveforms are applicable to all devices.
图 7-2. Reset Load Circuit and Voltage Waveforms

PCA9548A
8 Detailed Description
8.1 Overview
The PCA9548A is a 8-channel, bidirectional translating I2C switch. The master SCL/SDA signal pair is directed
to eight channels of slave devices, SC0/SD0-SC3/SD3. Any individual downstream channel can be selected as
well as any combination of the eight channels.
The device offers an active-low RESET input which resets the state machine and allows the PCA9548A to
recover if one of the downstream I2C buses get stuck in a low state. The state machine of the device can also be
reset by cycling the power supply, VCC, also known as a power-on reset (POR). Both the RESET function and a
POR cause all channels to be deselected.
The connections of the I2C data path are controlled by the same I2C master device that is switched to
communicate with multiple I2C slaves. After the successful acknowledgment of the slave address (hardware
selectable by A0 and A1 pins), a single 8-bit control register is written to or read from to determine the selected
channels.
The PCA9548A may also be used for voltage translation, allowing the use of different bus voltages on each
SCn/SDn pair such that 1.8-V, 2.5-V, or 3.3-V parts can communicate with 5-V parts. This is achieved by using
external pull-up resistors to pull the bus up to the desired voltage for the master and each slave channel.

PCA9548A
8.2 Functional Block Diagram
PCA9548A
SC0
SC1
SC2
SC3
SC4
SC5
SC6
SC7
SD0
SD1
SD2
SD3
SD4
SD5
SD6
SD7
GND Switch Control Logic
VCC
Reset Circuit
RESET
SCL A0
Input Filter
2
SDA I C Bus Control A1
A2
8.3 Feature Description

The PCA9548A is an 8-channel, bidirectional translating switch for I2C buses that supports Standard-Mode (100
kHz) and Fast-Mode (400 kHz) operation. The PCA9548A features I2C control using a single 8-bit control
register in which each bit controls the enabling and disabling for one of the 8 switch channels of I2C data flow.
Depending on the application, voltage translation of the I2C bus can also be achieved using the PCA9548A to
allow 1.8-V, 2.5-V, or 3.3-V parts to communicate with 5-V parts. Additionally, in the event that communication on
the I2C bus enters a fault state, the PCA9548A can be reset to resume normal operation using the RESET pin
feature or by a power-on reset which results from cycling power to the device.

PCA9548A
8.4 Device Functional Modes

8.4.1 RESET Input
The RESET input is an active-low signal that may be used to recover from a bus-fault condition. When this signal
is asserted low for a minimum of tWL, the PCA9548A resets its registers and I2C state machine and deselects all
channels. The RESET input must be connected to VCC through a pull-up resistor.
8.4.1.1 RESET Errata
If RESET voltage set higher than VCC, current flows from RESET pin to VCC pin.
8.4.1.1.1 System Impact
VCC is pulled above its regular voltage level.
8.4.1.1.2 System Workaround
Design such that RESET voltage is same or lower than VCC.
8.4.2 Power-On Reset
When power (from 0 V) is applied to VCC, an internal power-on reset holds the PCA9548A in a reset condition
until VCC has reached VPOR. At that point, the reset condition is released and the PCA9548A registers and I2C
state machine initialize to their default states. After that, V CC must be lowered to below VPOR and then back up to
the operating voltage for a power-reset cycle.
8.5 Programming
8.5.1 I2C Interface
The bidirectional I2C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must be
connected to a positive supply through a pull-up resistor when connected to the output stages of a device. Data
transfer may be initiated only when the bus is not busy.
I2C communication with this device is initiated by a master sending a start condition, a high-to-low transition on
the SDA input/output while the SCL input is high (see 图 8-1). After the start condition, the device address byte is
sent, most significant bit (MSB) first, including the data direction bit (R/ W).
After receiving the valid address byte, this device responds with an acknowledge (ACK), a low on the SDA input/
output during the high of the ACK-related clock pulse. The address inputs (A0–A2) of the slave device must not
be changed between the start and the stop conditions.
On the I2C bus, only one data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as control
commands (start or stop) (see 图 8-2).
A stop condition, a low-to-high transition on the SDA input/output while the SCL input is high, is sent by the
master (see 图 8-1).
Any number of data bytes can be transferred from the transmitter to receiver between the start and the stop
conditions. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before
the receiver can send an ACK bit. The device that acknowledges must pull down the SDA line during the ACK
clock pulse so that the SDA line is stable low during the high pulse of the ACK-related clock period (see 图 8-3).
When a slave receiver is addressed, it must generate an ACK after each byte is received. Similarly, the master
must generate an ACK after each byte that it receives from the slave transmitter. Setup and hold times must be
met to ensure proper operation.
A master receiver signals an end of data to the slave transmitter by not generating an acknowledge (NACK) after
the last byte has been clocked out of the slave. This is done by the master receiver by holding the SDA line high.
In this event, the transmitter must release the data line to enable the master to generate a stop condition.

PCA9548A
SDA
SCL
S P
Start Condition Stop Condition
图 8-1. Definition of Start and Stop Conditions
SDA
SCL
Data Line Change

Stable; of Data
Data Valid Allowed
图 8-2. Bit Transfer
Data Output
by Transmitter
NACK
Data Output
by Receiver
ACK
SCL From
Master 1 2 8 9
Start Clock Pulse for

Condition Acknowledgment
图 8-3. Acknowledgment on I2C Bus
8.6 Register Maps

8.6.1 Device Address
图 8-4 shows the address byte of the PCA9548A.

PCA9548A
Slave Address
1 1 1 0 A2 A1 A0 R/W
Fixed Hardware
Selectable
图 8-4. PCA9548A Address
The last bit of the slave address defines the operation (read or write) to be performed. When it is high (1), a read
is selected, while a low (0) selects a write operation.
表 8-1 shows the PCA9548A address reference.
表 8-1. Address Reference
INPUTS
I2C BUS SLAVE ADDRESS
A2 A1 A0
L L L 112 (decimal), 70 (hexadecimal)
L L H 113 (decimal), 71 (hexadecimal)
L H L 114 (decimal), 72 (hexadecimal)
L H H 115 (decimal), 73 (hexadecimal)
H L L 116 (decimal), 74 (hexadecimal)
H L H 117 (decimal), 75 (hexadecimal)
H H L 118 (decimal), 76 (hexadecimal)
H H H 119 (decimal), 77 (hexadecimal)
8.6.2 Control Register

Following the successful acknowledgment of the address byte, the bus master sends a command byte that is
stored in the control register in the PCA9548A (see 图 8-5). This register can be written and read via the I2C bus.
Each bit in the command byte corresponds to a SCn/SDn channel and a high (or 1) selects this channel. Multiple
SCn/SDn channels may be selected at the same time. When a channel is selected, the channel becomes active
after a stop condition has been placed on the I2C bus. This ensures that all SCn/SDn lines are in a high state
when the channel is made active, so that no false conditions are generated at the time of connection. A stop
condition always must occur immediately after the acknowledge cycle. If multiple bytes are received by the
PCA9548A, it saves the last byte received.
Channel Selection Bits (Read/Write)
B7 B6 B5 B4 B3 B2 B1 B0
Channel 0
Channel 1
Channel 2
Channel 3
Channel 4
Channel 5
Channel 6
Channel 7
图 8-5. Control Register

PCA9548A
表 8-2 shows the PCA9548A Command byte definition.

表 8-2. Command Byte Definition
CONTROL REGISTER BITS
COMMAND
B7 B6 B5 B4 B3 B2 B1 B0
0 Channel 0 disabled
X X X X X X X
1 Channel 0 enabled
X X X X X X X
1 Channel 1 enabled
X X X X X X X
1 Channel 2 enabled
X X X X X X X
1 Channel 3 enabled
X X X X X X X
1 Channel 4 enabled
X X X X X X X
1 Channel 5 enabled
X X X X X X X
1 Channel 6 enabled
X X X X X X X
1 Channel 7 enabled
No channel selected, power-up/reset
0 0 0 0 0 0 0 0
default state

PCA9548A
8.6.3 Bus Transactions

Data is exchanged between the master and PCA9548A through write and read commands.
8.6.3.1 Writes
Data is transmitted to the PCA9548A by sending the device address and setting the least-significant bit (LSB) to
a logic 0 (see 图 8-4 for device address). The command byte is sent after the address and determines which
SCn/SDn channel receives the data that follows the command byte (see 图 8-6). There is no limitation on the
number of data bytes sent in one write transmission.
Slave Address Control Register
SDA S 1 1 1 0 A2 A1 A0 0 A B7 B6 B5 B4 B3 B2 B1 B0 A P
Start Condition R/W ACK From Slave ACK From Slave Stop Condition
图 8-6. Write to Control Register
8.6.3.2 Reads
The bus master first must send the PCA9548A address with the LSB set to a logic 1 (see 图 8-4 for device
address). The command byte is sent after the address and determines which SCn/SDn channel is accessed.
After a restart, the device address is sent again, but this time, the LSB is set to a logic 1. Data from the SCn/SDn
channel defined by the command byte then is sent by the PCA9548A (see 图 8-7). After a restart, the value of
the SCn/SDn channel defined by the command byte matches the SCn/SDn channel being accessed when the
restart occurred. Data is clocked into the SCn/SDn channel on the rising edge of the ACK clock pulse. There is
no limitation on the number of data bytes received in one read transmission, but when the final byte is received,
the bus master must not acknowledge the data.
Slave Address Control Register
SDA S 1 1 1 0 A2 A1 A0 1 A B7 B6 B5 B4 B3 B2 B1 B0 NA P
Start Condition R/W ACK From Slave NACK From Master Stop Condition
图 8-7. Read From Control Register

PCA9548A
9 Application Information Disclaimer

Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information

Applications of the PCA9548A contain an I2C (or SMBus) master device and up to eight I2C slave devices. The
downstream channels are ideally used to resolve I2C slave address conflicts. For example, if eight identical
digital temperature sensors are needed in the application, one sensor can be connected at each channel: 0, 1, 2,
and 3. When the temperature at a specific location needs to be read, the appropriate channel can be enabled
and all other channels switched off, the data can be retrieved, and the I2C master can move on and read the
next channel.
In an application where the I2C bus contains many additional slave devices that do not result in I2C slave
address conflicts, these slave devices can be connected to any desired channel to distribute the total bus
capacitance across multiple channels. If multiple switches are enabled simultaneously, additional design
requirements must be considered (See the Design Requirements and Detailed Design Procedure sections).
9.2 Typical Application
A typical application of the PCA9548A contains 1 or many separate data pull-up voltages, VCC , one for the
master device and one for each of the selectable slave channels, 0 through 7. In the event where the master
device and all slave devices operate at the same voltage, then the VCC pin can be connected to this supply
voltage. In an application where voltage translation is necessary, additional design requirements must be
considered (See the Design Requirements section).
图 9-1 shows an application in which the PCA9548A can be used.

PCA9548A
VCC = 2.7 V to 5.5 V

VCC = 3.3 V
VCC = 2.7 V to 5.5 V
24
See Note A
23 4
SDA SDA SD0
I2C/SMBus 22 5 Channel 0
SCL SCL SC0
Master
3 VCC = 2.7 V to 5.5 V
RESET RESET
See Note A
SD1 6
7 Channel 1
SC1
VCC = 2.7 V to 5.5 V
See Note A
8
SD2
9 Channel 2
SC2
VCC = 2.7 V to 5.5 V
See Note A
10
SD3
11 Channel 3
SC3
VCC = 2.7 V to 5.5 V

PCA9548A
See Note A
13
SD4
14 Channel 4
SC4
VCC = 2.7 V to 5.5 V
See Note A
SD5 15
16 Channel 5
SC5
VCC = 2.7 V to 5.5 V
See Note A
17
SD6
18 Channel 6
SC6
VCC = 2.7 V to 5.5 V

21
A2
2 See Note A
A1
1 19
A0 SD7
12 20 Channel 7
GND SC7
A. Pin numbers shown are for the PW and RTW packages.
图 9-1. PCA9548A Typical Application Schematic

PCA9548A
9.2.1 Design Requirements

The A0, A1, and A2 pins are hardware selectable to control the slave address of the PCA9548A. These pins
may be tied directly to GND or VCC in the application.
If multiple slave channels are activated simultaneously in the application, then the total IOL from SCL/SDA to
GND on the master side is the sum of the currents through all pull-up resistors, Rp.
The pass-gate transistors of the PCA9548A are constructed such that the VCC voltage can be used to limit the
maximum voltage that is passed from one I2C bus to another.
Pass-Gate Voltage (Vpass) vs Supply Voltage (VCC) at Three Temperature Points shows the voltage
characteristics of the pass-gate transistors (note that the graph was generated using data specified in the
Electrical Characteristics section of this data sheet). In order for the PCA9548A to act as a voltage translator, the
Vpass voltage must be equal to or lower than the lowest bus voltage. For example, if the main bus is running at 5
V and the downstream buses are 3.3 V and 2.7 V, Vpass must be equal to or below 2.7 V to effectively clamp the
downstream bus voltages. As shown in Pass-Gate Voltage (Vpass) vs Supply Voltage (VCC) at Three
Temperature Points, Vpass(max) is 2.7 V when the PCA9548A supply voltage is 4 V or lower, so the PCA9548A
supply voltage could be set to 3.3 V. Pull-up resistors then can be used to bring the bus voltages to their
appropriate levels (see 图 9-1).
9.2.2 Detailed Design Procedure
Once all the slaves are assigned to the appropriate slave channels and bus voltages are identified, the pull-up
resistors, Rp, for each of the buses need to be selected appropriately. The minimum pull-up resistance is a
function of the reference voltage of the specific I2C channel (VDPUX), VOL,(max), and IOL as shown in 方程式 1.
VDPUX VOL(max)
Rp(min)
IOL
(1)
The maximum pull-up resistance is a function of the maximum rise time, tr (300 ns for fast-mode operation, fSCL
= 400 kHz) and bus capacitance, Cbis given by 方程式 2.
tr
Rp(max)
0.8473 u Cb
(2)
The maximum bus capacitance for an I2C bus must not exceed 400 pF for fast-mode operation. The bus
capacitance can be approximated by adding the capacitance of the PCA9548A, Cio(OFF), the capacitance of
wires, connections, traces, and the capacitance of each individual slave on a given channel. If multiple channels
are activated simultaneously, each of the slaves on all channels contribute to total bus capacitance.

PCA9548A
9.2.3 Application Curves
5 25
25ºC (Room Temperature) Standard-mode
85ºC Fast-mode
4 -40ºC 20
Rp(max) (kOhm)
3 15
Vpass (V)
2 10
1 5
0 0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 0 50 100 150 200 250 300 350 400 450
VCC (V) Cb (pF) D008
D007
Standard-mode (fSCL kHz, tr SPACE (fSCL kHz, tr) Standard-mode (fSCL = 100 Fast-mode (fSCL = 400 kHz, tr
kHz, tr = 1 µs) = 300 ns)
图 9-2. Pass-Gate Voltage (Vpass) vs Supply Voltage
(VCC) at Three Temperature Points 图 9-3. Maximum Pull-Up Resistance (Rp(max)) vs
Bus Capacitance (Cb)
1.8
1.6
1.4
1.2
Rp(min) (kOhm)
0.8
0.6
0.4
0.2 VDPUX > 2V

VDPUX <= 2
0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5
VDPUX (V) D009
VOL = 0.2*VDPUX, IOL = 2 mA when VDPUX ≤ 2 V

VOL = 0.4 V, IOL = 3 mA when VDPUX > 2 V
图 9-4. Minimum Pullup Resistance (Rp(min)) vs Pullup Reference Voltage (VDPUX)

PCA9548A
10 Power Supply Recommendations

10.1 Power-On Reset Requirements
In the event of a glitch or data corruption, PCA9548A can be reset to its default conditions by using the power-on
reset feature. Power-on reset requires that the device go through a power cycle to be completely reset. This
reset also happens when the device is powered on for the first time in an application.
The two types of power-on reset are shown in 图 10-1 and 图 10-2.
VCC
Ramp-Up Ramp-Down Re-Ramp-Up
VCC_TRR_GND
Time
Time to Re-Ramp
VCC_RT VCC_FT VCC_RT
图 10-1. VCC Is Lowered Below 0.2 V Or 0 V And Then Ramped Up To VCC
VCC
Ramp-Down Ramp-Up
VCC_TRR_VPOR50
VIN drops below POR levels
Time
Time to Re-Ramp
VCC_FT VCC_RT
图 10-2. VCC Is Lowered Below The Por Threshold, Then Ramped Back Up To VCC
表 10-1 specifies the performance of the power-on reset feature for PCA9548A for both types of power-on reset.
表 10-1. Recommended Supply Sequencing And Ramp Rates(1)
PARAMETER MIN TYP MAX UNIT
VCC_FT Fall rate See 图 10-1 1 100 ms
VCC_RT Rise rate See 图 10-1 0.01 100 ms
VCC_TRR_GND Time to re-ramp (when VCC drops to GND) See 图 10-1 0.001 ms
VCC_TRR_POR50 Time to re-ramp (when VCC drops to VPOR_MIN – 50 mV) See 图 10-2 0.001 ms
Level that VCCP can glitch down to, but not cause a functional
VCC_GH See 图 10-3 1.2 V
disruption when VCCX_GW = 1 μs
Glitch width that will not cause a functional disruption when
VCC_GW See 图 10-3 μs
VCCX_GH = 0.5 × VCCx
VPORF Voltage trip point of POR on falling VCC 0.767 1.144 V
VPORR Voltage trip point of POR on rising VCC 1.033 1.428 V
(1) TA = –40°C to 85°C (unless otherwise noted)
Glitches in the power supply can also affect the power-on reset performance of this device. The glitch width
(VCC_GW) and height (VCC_GH) are dependent on each other. The bypass capacitance, source impedance, and
the device impedance are factors that affect power-on reset performance. 图 10-3 and 表 10-1 provide more
information on how to measure these specifications.

PCA9548A
VCC
VCC_GH
Time
VCC_GW
图 10-3. Glitch Width And Glitch Height
VPOR is critical to the power-on reset. VPOR is the voltage level at which the reset condition is released and all
the registers and the I2C/SMBus state machine are initialized to their default states. The value of VPOR differs
based on the VCC being lowered to or from 0. 图 10-4 and 表 10-1 provide more details on this specification.
VCC
VPOR
VPORF
Time
POR
Time
图 10-4. VPOR

PCA9548A
11 Layout
11.1 Layout Guidelines
For PCB layout of the PCA9548A, common PCB layout practices must be followed but additional concerns
related to high-speed data transfer such as matched impedances and differential pairs are not a concern for I2C
signal speeds. It is common to have a dedicated ground plane on an inner layer of the board and pins that are
connected to ground must have a low-impedance path to the ground plane in the form of wide polygon pours
and multiple vias. By-pass and de-coupling capacitors are commonly used to control the voltage on the VCC pin,
using a larger capacitor to provide additional power in the event of a short power supply glitch and a smaller
capacitor to filter out high-frequency ripple.
In an application where voltage translation is not required, all VDPUX voltages and VCC could be at the same
potential and a single copper plane could connect all of pull-up resistors to the appropriate reference voltage. In
an application where voltage translation is required, VDPUM and V DPU0 – VDPU7 may all be on the same layer of
the board with split planes to isolate different voltage potentials.
To reduce the total I2C bus capacitance added by PCB parasitics, data lines (SCn and SDn) must be a short as
possible and the widths of the traces must also be minimized (For example, 5-10 mils depending on copper
weight).

PCA9548A
11.2 Layout Example
LEGEND
Partial Power Plane
(inner layer)
To I2C Master
Copper Pour
(outer layer)
Via to Power Plane
Via to GND Plane
By-pass/de-coupling
capacitors
VDPUM
GND VCC
To Slave Channel 0
To Slave Channel 7
A0 1 PW package 24 VCC
A1 2 23 SDA
VDPU0
RESET 3 22 SCL VDPU7
SD0 4 21 A2
To Slave Channel 1
PCA9548A
SC0 5 20 SC7
To Slave Channel 6
SD1 6 19 SD7
VDPU1
SC1 7 18 SC6
VDPU6
SD2 8 17 SD6
To Slave Channel 2
VDPU2 SC2 9 16 SC5
To Slave Channel 5
VDPU5
SD3 10 15 SD5
SC3 11 14 SC4
GND 12 13 SD4
To Slave Channel 3
VDPU3
To Slave Channel 4
GND
VDPU4
图 11-1. Layout Example

PCA9548A
12 Device and Documentation Support

12.1 Related Documentation
For related documentation see the following:
• I2C Bus Pull-Up Resistor Calculation
• Maximum Clock Frequency of I2C Bus Using Repeaters
• Introduction to Logic
• Understanding the I2C Bus
• Choosing the Correct I2C Device for New Designs
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates—including silicon errata—go to the product folder for your
device on ti.com. In the upper right-hand corner, click the Alert me button. This registers you to receive a weekly
digest of product information that has changed (if any). For change details, check the revision history of any
revised document.
12.3 Support Resources
TI E2E ™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

PACKAGE OPTION ADDENDUM
www.ti.com 4-Nov-2023
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
PCA9548ADB ACTIVE SSOP DB 24 60 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 PD548A Samples
PCA9548ADBR ACTIVE SSOP DB 24 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 PD548A Samples
PCA9548ADGV NRND TVSOP DGV 24 TBD Call TI Call TI -40 to 85

PCA9548ADGVR LIFEBUY TVSOP DGV 24 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 PD548A
PCA9548ADW LIFEBUY SOIC DW 24 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 PCA9548A
PCA9548APWR ACTIVE TSSOP PW 24 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 PD548A Samples
PCA9548APWRG4 ACTIVE TSSOP PW 24 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 PD548A Samples
PCA9548ARGER NRND VQFN RGE 24 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 PD548A
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
TAPE AND REEL INFORMATION
REEL DIMENSIONS TAPE DIMENSIONS

K0 P1
B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers
Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2 Q1 Q2
Q3 Q4 Q3 Q4 User Direction of Feed
Pocket Quadrants
*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
PCA9548ADBR SSOP DB 24 2000 330.0 16.4 8.2 8.8 2.5 12.0 16.0 Q1
PCA9548ADGVR TVSOP DGV 24 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
PCA9548APWR TSSOP PW 24 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1
PCA9548ARGER VQFN RGE 24 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
PCA9548ARGER VQFN RGE 24 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
Pack Materials-Page 1
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
PCA9548ADBR SSOP DB 24 2000 356.0 356.0 35.0
PCA9548ADGVR TVSOP DGV 24 2000 356.0 356.0 35.0
PCA9548APWR TSSOP PW 24 2000 356.0 356.0 35.0
PCA9548ARGER VQFN RGE 24 3000 356.0 356.0 35.0
PCA9548ARGER VQFN RGE 24 3000 356.0 356.0 35.0
TUBE
T - Tube
height L - Tube length
W - Tube
width
B - Alignment groove width

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
PCA9548ADB DB SSOP 24 60 530 10.5 4000 4.1
PCA9548ADW DW SOIC 24 25 506.98 12.7 4826 6.6
GENERIC PACKAGE VIEW
RGE 24 VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4204104/H
PACKAGE OUTLINE
RGE0024C VQFN - 1 mm max height
PLASTIC QUAD FLATPACK- NO LEAD
B 4.1 A
3.9
PIN 1 INDEX AREA 4.1

3.9
1 MAX C
SEATING PLANE
0.05
0.00 2X 2.5 0.08 C
2.1±0.1
(0.2) TYP
7 12
20X 0.5
6
13
25 SYMM
2X
2.5
1 18
PIN 1 ID 24X 0.30
0.18
(OPTIONAL) 24 19 0.1 C A B
SYMM
24X 0.50
0.30
0.05 C
4224376 / C 07/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
(3.8)
( 2.1)
24 19
24X (0.6)
24X (0.24)
1
18
20X (0.5)
SYMM 25
(3.8)
2X
(0.8)
(Ø0.2) VIA
TYP
6 13
(R0.05)
7 12
2X(0.8)
SYMM
LAND PATTERN EXAMPLE

SCALE: 20X
0.07 MAX 0.07 MIN

ALL AROUND METAL ALL AROUND
SOLDER MASK
OPENING
SOLDER MASK METAL UNDER
OPENING SOLDER MASK
NON SOLDER MASK

DEFINED SOLDER MASK
(PREFERRED) DEFINED
SOLDER MASK DETAILS

4224376 / C 06/2021
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments
literature number SLUA271 (www.ti.com/lit/slua271).
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
(3.8)
4X ( 0.94)
24 19
24X (0.6)
24X (0.24)
1
18
20X (0.5)
SYMM (3.8)
(0.57)
TYP
6 13
(R0.05) TYP 25
METAL
TYP 7 12
(0.57)
TYP
SYMM
SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
80% PRINTED COVERAGE BY AREA
SCALE: 20X
4224376 / C 06/2021
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations..
www.ti.com
PACKAGE OUTLINE
PW0024A SCALE 2.000
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SEATING
PLANE
6.6 C
TYP
A 6.2
0.1 C
PIN 1 INDEX AREA
22X 0.65
24
1
2X
7.9 7.15
7.7
NOTE 3
12
13
0.30
24X
4.5 0.19 1.2 MAX
B
4.3 0.1 C A B
NOTE 4
0.25
GAGE PLANE
0.15
0.05
(0.15) TYP
SEE DETAIL A 0.75
0 -8 0.50
DETAIL A
A 20
TYPICAL
4220208/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0024A TSSOP - 1.2 mm max height
24X (1.5) SYMM
1 (R0.05) TYP
24X (0.45) 24
22X (0.65)
SYMM
12 13
(5.8)
LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK METAL UNDER SOLDER MASK

METAL
OPENING SOLDER MASK OPENING
EXPOSED METAL EXPOSED METAL
0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND
NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)
SOLDER MASK DETAILS
15.000
4220208/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0024A TSSOP - 1.2 mm max height
24X (1.5) SYMM

(R0.05) TYP
1
24X (0.45) 24
22X (0.65)
SYMM
12 13
(5.8)
SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220208/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE

28 PINS SHOWN
0,38
0,65 0,15 M
0,22
28 15
0,25
0,09
5,60 8,20
5,00 7,40
Gage Plane
1 14 0,25
A 0°–ā8° 0,95
0,55
Seating Plane
2,00 MAX 0,05 MIN 0,10
PINS **
14 16 20 24 28 30 38
DIM
A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90
A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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PCA9548A

ZHCSJK4G – JUNE 2009 – REVISED MARCH 2021

支持复位的 PCA9548A 低电压 8 通道 I2C 开关

– 2000V 人体放电模型 (A114-A) SSOP (24) 8.20mm × 5.30mm

– 200V 机器放电模型 (A115-A) TVSOP (24) 5.00mm × 4.40mm

Changes from Revision E (February 2015) to Revision F (April 2019) Page

Changes from Revision D (June 2014) to Revision E (February 2015) Page

Changes from Revision C (June 2007) to Revision D (June 2014) Page

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5 Pin Configuration and Functions

表 5-1. Pin Functions

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图 5-2. RGE Package, 24-Pin VQFN , Top View

表 5-2. Pin Functions, RGE

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6.2 ESD Ratings

6.3 Recommended Operating Conditions

6.4 Thermal Information

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6.4 Thermal Information (continued)

6.5 Electrical Characteristics

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6.5 Electrical Characteristics (continued)

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6.6 I2C Interface Timing Requirements

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6.7 Reset Timing Requirements

6.8 Switching Characteristics

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6.9 Typical Characteristics

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7 Parameter Measurement Information

SDA LOAD CONFIGURATION

Three Bytes for Complete

Stop Start Address R/W Data Data Stop

A. CL includes probe and jig capacitance.

图 7-1. I2C Load Circuit and Voltage Waveforms

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SDA LOAD CONFIGURATION

SCL ACK or Read Cycle

图 7-2. Reset Load Circuit and Voltage Waveforms

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Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 13

8.2 Functional Block Diagram

GND Switch Control Logic

8.3 Feature Description

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8.4 Device Functional Modes

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Start Condition Stop Condition

图 8-1. Definition of Start and Stop Conditions

Data Line Change