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Assignment-1 Module-2

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28 views

Assignment-1 Module-2

Uploaded by

p09931312
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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K.L.E.

Society’s
FORM
KLE College of Engg. & Technology, Chikodi ISO 21001: 2018 -
KLECET
Since 1916 DEPT. OF COMPUTER SCIENCE

Title: Assignment1
1- Questions
Subject: Digital Design and Computer Organization Sub.code:BCS302
Semester: III (A&B) Marks 10 marks
Max. Marks:
ASSIGNMENT-1 QUESTIONS
Module-2

Q. Questions CO’s Marks


No.
1 Design a combinational circuit with three inputs and one output. C302.2 6
a) The output is 1 when the binary value of input is less than or equal
to 2. The output is 0 otherwise.
b) The output is 1 when the binary value of the input is an even
number
2 Explain binary adder and subtractor with neat diagram. C302.2 6
3 Explain the carry lookahead generator with neat di
diagram. C302.2 10

4 Explain with a neat diagram 3:8 decoder. C302.2 6

5 Implement a given functions using 3:8 line decoder C302.2 10


a) F1 (a,b,c)= ∑(0,4,6)
∑(0,4,6 b)F1 (a,b,c)= ∑(1,2,3,4)
∑(1,2,3,4
F2 (a,b,c)= ∑(0,5) F2 (a,b,c)= ∑(3,5,7
∑(3,5,7)
F3 (a,b,c)= ∑(1,2,3,7)
∑(1,2,3,7

6 Implement a full adder using 3:8 decoder. C302.2 6


7 Implement a full-subtractor
subtractor using 3:8 decoder with NAND gates. C302.2 6
8 What is multiplexer? Explain 8:1 multiplexer with the help of logic C302.2 7
diagram and corresponding expression.
9 Implement following Boolean functions
function with 8:1
1 mux and 4:1 mux and C302.2 10
external gates. a) F1(A,B,C,D)=
F1(A,B,C,D)=∑(0,1,5,7,8,13,14)
b) F2(A,B,C,D)=∑(1,3,4,11,12,13,14,15
∑(1,3,4,11,12,13,14,15)

10 What is priority encoder? Design 4:2 priority encoder with necessary diagram. C302.2 10

11 Write a Verilog code for 4-bit


4 adder. C302.2 6
12 Write a Verilog code for 8:3 encoder. C302.2 6
13 List the difference between combinational logic and sequential logic. C302.2 6

14 Explain the working derive the


ing of SR latch using NOR gates and derive C302.2 8
characteristic equation.
15 Explain the edge triggered D flip flop. C302.2 6

16 Explain the working of JK flip flop with timing diagram. C302.2 8

17 Derive the characteristic equation for SR,D,JK and T flip flop. C302.2 10

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