Scribd
Upload
17 views5 pages

FPGA Guide

Uploaded by

aya
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
17 views5 pages

FPGA Guide

Uploaded by

aya
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 5

TP guide for FPGA

Launch Vivado.

Quick start : click Create project

New project window: click Next -> Enter project name and location (tick Create project subdirectory)
then click Next

-> tick RTL project then click Next

-> Add sources page : in target language select VHDL, and click Create file (VHDL as type and
enter a filename), then click Next

-> Add constraints page click Create file (XDC as type and enter a filename), then click Next

-> Default part page: select xc7z020clg484-1, then Next -> click Finish

Something like this should appear :

Otherwise :

1
Orange : Navigator
Green : Sources
Red : Properties
Blue : Design
Black : Console

Double click on your design source file (filename.vhd) i twill open the corresponding source code in
VHDL : you can here develop your code (respect the syntax and comment with --). You can add other
sources to your design by : left click on Design sources in the Sources tab -> Add sources -> Add or
create design sources -> Create file : select VHDL as type and enter a filename, then click OK and
Finish .

When employing components pay attention to the hierarchy (To move the element on the top :
Right click on the source element and Set as top ).

You can check your design for errors with report DRC from the Navigator -> RTL analysis -> Report
DRC. You can also visualize the schematic corresponding to your design.

2
SIMULATION
In order to run a simulation : select your design and click on Run Simulation in the Navigator tab
under SIMULATION -> Run bahavioural simulation . Something similar to the image here below
should appear.

In the object tab you can right click on the signal and force a constant value (Force constant) or a
clock signal (Force clock). You can run the simulation for a time lag of your choice with the Run for
button. And see the result on the right tab. Zoom_in and Zoom_out if the time scale is insufficient.

Now you can feel halfway to be like :

(Micheal Scofield from Prison Break)

3
MAPPING INPUTs and OUTPUTs
You need now to map the pins of your design with those on the ZedBoard (see in the image below :
buttons encircled in yellow, leds in red, …). For this operation you should locate your I/Os and the
port name associated to them (e.g. the first led on the left is LD7 and its port name is U14 ; the left
button is BTNL and the port name is N15).

Go to Window -> I/O Ports : you should see the list of your ports appear in the Console. In the column
Package Pin you can select the Port name corresponding to the design pins.

4
You can click on Run synthesis and Run implementation, and then check the layout of the circuit you
have realized.

You can turn ON/OFF the board with the button on the upper-left corner.

In PROGRAM AND DEBUG, you can generate the bitstream (Generate Bitstream) to be sent to the
FPGA. In order to connect to your board, you can click on Open Target and select Auto-connect. Then
just Program Device and select your device (it should be the only one that appears).

If you see something like :

OR

There might be a problem.

Otherwise just check the validity by pressing on the buttons and looking at the leds.

You might also like