Verilog for

Digital Design
Chapter 2:
Combinational Logic Design

Verilog for Digital Design

Copyright © 2007 1
Frank Vahid and Roman Lysecky
 AND/OR/NOT Gates (Fundamental Gates used in
combinational circuits)
There are two types of circuits: Combinational (2) Sequential
Combinational Circuits: In which the output depends on the input only. (like in truth table)
Sequential Circuits: In which the output depends on the input as well as the previous
output. In other words, sequential circuits are those circuits in which the output depends
on the input as well as the state of the system.

In combinational circuits, there is no concept of state and hence no memory is involved.

In sequential circuits, the system goes through different states and therefore a memory is
required to remember different states of the system

We start with the Verilog designing of combinational circuits which contains logic gates.
The three fundamental logic gates are AND gate, OR gate and NOT gate.

Verilog for Digital Design

Copyright © 2007 2
Frank Vahid and Roman Lysecky
 AND/OR/NOT Gates
Verilog Modules and Ports (Declaration of components in Verilog)
X X
F F X F
Y Y

module And2(X, Y, F); module Or2(X, Y, F); module Inv(X, F);

input X, Y; input X, Y; input X;

output F; output F; output F;
... ... ...

• module – Declares a new type of component. This is a keyword in Verilog.

• A module may have different names. For example:
– Named “And2" in first example, “Or2" in the second example and “Inv" in the third example
– Remember that u can choose any name.
– Includes list of ports (module's inputs and outputs). A port is actually a French language word which means the
GATE. (BAAB in Arabic language). There are two types of ports: Input port and output port.

• input – it shows which ports are inputs

• output – it shows which ports are outputs
• Each port is a bit – can have value of 0, 1, or x (unknown value)
• Note: Verilog already has built-in primitives (keywords) for logic gates, but instructive to build them

Verilog for Digital Design

Copyright © 2007 3
vldd_ch2_And2.v vldd_ch2_Or2.v
Frank Vahid and Roman Lysecky vldd_ch2_Inv.v
 AND/OR/NOT Gates
(Rules for keywords and Identifiers)
X X
F F X F
Y Y

module And2(X, Y, F); module Or2(X, Y, F); module Inv(X, F);

input X, Y; input X, Y; input X;

output F; output F; output F;
... ... ...
• Verilog has several dozen keywords
– User cannot use keywords when naming items like modules or ports
– module, input, and output are keywords
– Keywords must be lowercase, You can not use any CAPITAL letter in keywords.
– However, the words you have chosen (identifier) may contain upper case letters.
• User-defined names (the words you have chosen) – Identifiers
– Begin with letter or underscore (_). It is followed by any sequence of letters, digits,
underscores, and dollar signs ($)
– Valid identifiers: A, X, Hello, JXYZ, B14, Sig432, Wire_23, _F1, F$2, _Go_$_$, _, Input, Output,
• Note: "_" and "Input" are valid, but unwise
– Invalid identifiers: input (keyword), $ab (doesn't start with letter or underscore), 2A (doesn't start with
letter or underscore)
• Note: Verilog is case sensitive. Sig432 differs from SIG432 and sig432
Verilog for Digital Design
Copyright © 2007 4
vldd_ch2_And2.v vldd_ch2_Or2.v
Frank Vahid and Roman Lysecky vldd_ch2_Inv.v
 How to Declare a 4x1 Multiplexor in Verilog

• Q: Begin a module definition for a 4x1 multiplexor

Mux4
– Inputs: I3, I2, I1, I0, S1, S0. Outputs: D
I0
I1
D
I2
I3
module Mux4(I3, I2, I1, I0, S1, S0, D); S1 S0

input I3, I2, I1, I0;

input S1, S0; 4x1 mux
output D;
...

• Note that input ports above are separated into two declarations for clarity
• In one line u have data inputs (I3, I2, I1, I0)
• In the next line, u have control inputs (S1, S0)
• However, u can write data inputs and control inputs in a single
line.

Verilog for Digital Design

Copyright © 2007 5
Frank Vahid and Roman Lysecky vldd_ch2_Mux4Beh.v
 What we have did so far
• Until now, we have learned that how to declare a module (component)
in Verilog.
• Declaration means, the name of a module and the name of ports.

• Next, we will focus on how to describe the functionality of a module

(component) in Verilog…….

Verilog for Digital Design

Copyright © 2007 6
Frank Vahid and Roman Lysecky
 Behavior/Functionality of AND/OR/NOT Gates
Module Procedures—always
• One way to describe a module's behavior
uses an "always" procedure
x
F – always – Procedure that executes repetitively (infinite loop)
y from simulation start (it never ends). ‫بشكل متكرر‬
– @ – event control showing that statements should only
execute when values change

module And2(X, Y, F);

• "(X,Y)" – execute if X changes or Y changes
(change known as an event)
input X, Y; • Sometimes called “sensitivity list” ‫قائمة الحساسية‬
output F; • We’ll say that procedure is “sensitive to X and Y”
reg F; wait until X or
– "F <= X & Y;" – Procedural statement that sets F to
Y changes AND of X, Y
always @(X, Y) begin
F <= X & Y; • & is built-in bit AND operator
end • <= assigns value to variable
F <= x AND y – reg – Declares a variable data type, which
endmodule
holds its value between assignments
vldd_ch2_And2.v
• Needed for F to hold value between
assignments
• Note: "reg", short for "register", is an unfortunate
name. A reg variable may or may not
correspond to an actual physical register. There
obviously is no register inside an AND gate.
Verilog for Digital Design
Copyright © 2007 7
Frank Vahid and Roman Lysecky
 AND/OR/NOT Gates
Module Procedures—always
• Q: Given that "|" and "~" are built-in operators for OR and NOT, complete
the modules for a 2-input OR gate and a NOT gate
x
F x F
y

module Or2(X, Y, F); module Inv(X, F);

input X, Y; input X;
output F; output F;
reg F; reg F;

always @(X, Y) begin always @(X) begin

F <= X | Y; F <= ~X;
end end

endmodule endmodule

Verilog for Digital Design

Copyright © 2007 vldd_ch2_Or2.v 8
Frank Vahid and Roman Lysecky vldd_ch2_Inv.v
 Recap
• So far:
– Definition of module (Declaration of a module)
– Functionality/behavior of a module using “always”
procedure
• Next:
– Testing of a module using a test bench

Verilog for Digital Design

Copyright © 2007 9
Frank Vahid and Roman Lysecky
 AND/OR/NOT Gates
Simulation and Testbenches — A First Look

• How does our new module behave?

• Simulation: User provides input values and
simulator generates output values Timescale directive is for simulation.
– Test vectors – sequence of input values More details later.
– Waveform – graphical representation of
`timescale 1 ns/1 ns
sequence of input values
1 module And2(X, Y, F);
X
User provides test 0 input X, Y;
vectors output F;
1 reg F;
Y
0
Simulator generates always @(X, Y) begin
1 F <= X & Y;
output values based F end
on HDL description 0
endmodule
time

Simulator
Verilog for Digital Design
Copyright © 2007 10
Frank Vahid and Roman Lysecky vldd_ch2_And2.v
 AND/OR/NOT Gates
Simulation and Testbenches — A First Look
• Instead of drawing test vectors, user can describe them with HDL
• Different values of inputs can be written in the program

1 ... `timescale 1 ns/1 ns

X Y_s <= 0; X_s <= 0;
0 #10 Y_s <= 0; X_s <= 1; module And2(X, Y, F);
1 #10 Y_s <= 1; X_s <= 0;
Y #10 Y_s <= 1; X_s <= 1; input X, Y;
0 ... output F;
time reg F;
10 20 30 (ns)
1 always @(X, Y) begin
F F <= X & Y;
0 end

endmodule
"#10" –
Tells simulator to keep present values
for 10 ns, before executing the next
statement

Verilog for Digital Design

Simulator
Copyright © 2007 11
Frank Vahid and Roman Lysecky vldd_ch2_And2.v
 AND/OR/NOT Gates
Simulation and Testbenches

Idea: Create new "Testbench" module that provides test vectors to component's inputs

`timescale 1 ns/1 ns
Testbench module Testbench();
procedure

X_s reg X_s, Y_s;

X CompToTest
Y_s F_s wire F_s;
Y (And2) F
And2 CompToTest(X_s, Y_s, F_s);

initial begin
// Test all possible input combinations
• HDL testbench Y_s <= 0; X_s <= 0;
#10 Y_s <= 0; X_s <= 1;
• Module with no ports #10 Y_s <= 1; X_s <= 0;
• Declare reg variable for each input #10 Y_s <= 1; X_s <= 1;
end
port, wire for each output port
endmodule
• Instantiate module, map variables to More information
on next slides
ports (more in next section)
• Set variable values at desired times
Note: CompToTest short for Component To Test
Verilog for Digital Design
Copyright © 2007 12
Frank Vahid and Roman Lysecky vldd_ch2_And2TB.v
 AND/OR/NOT Gates
Simulation and Testbenches

• wire – Declares a net data type, which

does not store its value
– Vs. reg data type that stores value `timescale 1 ns/1 ns
– Nets used for connections
– Net's value determined by what it is module Testbench();
connected to
• initial –procedure that executes at reg X_s, Y_s;
simulation start, but executes only once wire F_s;
– Vs. "always" procedure that also
And2 CompToTest(X_s, Y_s, F_s);
executes at simulation start, but that
repeats
initial begin
• # – Delay control – number of time units // Test all possible input combinations
to delay this statement's execution Y_s <= 0; X_s <= 0;
relative to previous statement #10 Y_s <= 0; X_s <= 1;
– `timescale – compiler directive telling #10 Y_s <= 1; X_s <= 0;
compiler that from this point forward, 1 #10 Y_s <= 1; X_s <= 1;
time unit means 1 ns end
• Valid time units – s (seconds), ms
(milliseconds), us (microseconds), ns endmodule
(nanoseconds), ps (picoseconds), and fs
(femtoseconds)
• 1 ns/1 ns – time unit / time precision.
Precision is for internal rounding. For our
purposes, precision will be set same as
time unit.
Verilog for Digital Design Note: We appended "_s" to reg/wire identifiers to
Copyright © 2007 distinguish them from ports, though not strictly necessary 13
Frank Vahid and Roman Lysecky vldd_ch2_And2TB.v
 AND/OR/NOT Gates
Simulation and Testbenches

• Provide testbench file to simulator `timescale 1 ns/1 ns

– Simulator generates waveforms
module Testbench();
– We can then check if behavior
looks correct reg X_s, Y_s;
wire F_s;

And2 CompToTest(X_s, Y_s, F_s);

1 initial begin
X_s // Test all possible input combinations
0 Y_s <= 0; X_s <= 0;
1 #10 Y_s <= 0; X_s <= 1;
Y_s #10 Y_s <= 1; X_s <= 0;
0 #10 Y_s <= 1; X_s <= 1;
end
1
F_s
endmodule
0
time
10 20 30 (ns)
Simulator
Verilog for Digital Design
Copyright © 2007 14
Frank Vahid and Roman Lysecky vldd_ch2_And2TB.v
 Recap
• So far:
– Definition of a module (declaration in Verilog)
– Working/functionality of a module (behavior of the module in Verilog)
– Testing of a module by using testbench
– You have used three very simple examples of AND, OR and NOT gates.

• Next:
– Now you will use the aforementioned concepts
for combinational circuit (structure)

Verilog for Digital Design

Copyright © 2007 15
Frank Vahid and Roman Lysecky
 Combinational Circuits
Component Instantiations
• Circuit – A connection of modules. It means u can
design more than one modules and then simply X
connect them according to the requirements. F X F
Y
– Also known as structure
– A circuit is a second way to describe a module.
– In the previous slides, you have written the Modules to be used
functionality of a module using “always” loop.
Module instances ‫قطعة‬
– Now, you will see another of writing the behaviour
using circuits in Verilog.
• Instance – An occurrence of a module in a circuit K
P And2_1 N1
• May be multiple instances of a module. e.g., Car's modules: W
N2 And2_2
tires, engine, windows, etc., with 4 tire instances, 1 engine
instance, 6 window instances, etc. S
Inv_1
BeltWarn

Verilog for Digital Design

Copyright © 2007 16
Frank Vahid and Roman Lysecky
 Combinational Circuits
Module Instantiations
• Creating a circuit `timescale 1 ns/1 ns
1. Start definition of a new module module BeltWarn(K, P, S, W);
2. Declare nets for connecting module
instances input K, P, S;
output W;
• N1, N2
wire N1, N2;

And2 And2_1(K, P, N1);

Inv Inv_1(S, N2);
And2 And2_2(N1, N2, W);
3. Create module instances, create
connections endmodule

X
F X F
Y K
P And2_1 N1
“BeltWarn” example: Turn on
W
N2 And2_2
warning light (w=1) if car key is
S
in ignition (k=1), person is
Inv_1
seated (p=1), and seatbelt is not
fastened (s=0) BeltWarn
vldd_ch2_BeltWarnStruct.v
Verilog for Digital Design
Copyright © 2007 17
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 Combinational Circuits
Module Instantiations

• Module instantiation `timescale 1 ns/1 ns

statement module BeltWarn(K, P, S, W);

input K, P, S;
output W;
And2 And2_1(K, P, N1);
wire N1, N2;
Note: Ports ordered
as in original And2 And2 And2_1(K, P, N1);
module definition Inv Inv_1(S, N2);
And2 And2_2(N1, N2, W);
Connects instantiated module's
endmodule
ports to nets and variables

Name of new module instance And2_1

K And2_2
Must be distinct; hence And2_1 and And2_2 N1
P W
Name of module to instantiate N2
S

Inv_1 BeltWarn

Verilog for Digital Design vldd_ch2_BeltWarnStruct.v

Copyright © 2007 18
Frank Vahid and Roman Lysecky
 Combinational Circuits (Structural Code)
Module Instantiations
Q: Complete the 2x1 mux circuit's module instantiations

`timescale 1 ns/1 ns

Mux2 module Mux2(I1, I0, S0, D);

I0
D input I1, I0;
I1 input S0;
1. Start definition of a new
S0 output D;
module (done)
wire N1, N2, N3;
(Draw desired circuit,
And2_1
if not already done) N2 Or2_1 Inv Inv_1 (S0, N1);
I0
And2 And2_1 (I0, N1, N2);
2. Declare nets N1 D And2 And2_2 (I1, S0, N3);
N3
for internal wires I1 Or2 Or2_1 (N2, N3, D);

And2_2 endmodule
3. Create module instances
Inv_1
and connect ports S0

Is it a behavioral Verilog Code or Structural Verilog Code??

Verilog for Digital Design
Copyright © 2007 19
Frank Vahid and Roman Lysecky
vldd_ch2_Mux2Struct.v
 Combinational Circuit Structure
Simulating the Circuit
• Same testbench format for BeltWarn
module as for earlier And2 module
`timescale
`timescale 11 ns/1
ns/1 ns
ns
Testbench
module
module Testbench();
Testbench();
procedure

X_s
X CompToTest reg
reg K_s,
X_s, P_s,
Y_s; S_s;
Y_s F_s
Y (And2) F wire
wire W_s;
F_s;

BeltWarn CompToTest(K_s,
And2 CompToTest(X_s, Y_s,P_s, S_s, W_s);
F_s);

initial
initial begin
begin
Testbench K_s <= 0;all
// Test P_spossible
<= 0; S_s <= 0;
input combinations
#10
Y_s K_s <= X_s
<= 0; 0; P_s <= 1; S_s <= 0;
<= 0;
K_s #10
#10 K_s
Y_s <=
<= 1;
0; P_s
X_s <=
<= 1;
1; S_s <= 0;
procedure

K #10
#10 K_s
Y_s <=
<= 1;
1; P_s
X_s <=
<= 1;
0; S_s <= 1;
P_s CompToTest W_s end #10 Y_s <= 1; X_s <= 1;
P (BeltWarn) W end
S_s S
endmodule
endmodule

K BeltWarn
P W
Verilog for Digital Design
Copyright © 2007 S 20
Frank Vahid and Roman Lysecky
vldd_ch2_BeltWarnTB.v
 Combinational Circuit Structure
Simulating the Circuit

• Simulate testbench file to obtain `timescale 1 ns/1 ns

waveforms module Testbench();

reg K_s, P_s, S_s;

wire W_s;

BeltWarn CompToTest(K_s, P_s, S_s, W_s);

1
K_s initial begin
0 K_s <= 0; P_s <= 0; S_s <= 0;
1 #10 K_s <= 0; P_s <= 1; S_s <= 0;
P_s #10 K_s <= 1; P_s <= 1; S_s <= 0;
0 #10 K_s <= 1; P_s <= 1; S_s <= 1;
1 end
S_s
0
endmodule
1
W_s
0
10 20 30 time (ns)
Simulator
Verilog for Digital Design
Copyright © 2007 21
Frank Vahid and Roman Lysecky
vldd_ch2_BeltWarnTB.v
 Combinational Circuit Structure
Simulating the Circuit

• More on testbenches `timescale 1 ns/1 ns

– Note that a single module instantiation module Testbench();

statement used reg K_s, P_s, S_s;

wire W_s;
– reg and wire declarations (K_s, P_s,
S_s, W_s) used because procedure BeltWarn CompToTest(K_s, P_s, S_s, W_s);
cannot access instantiated module's initial begin
ports directly K_s <= 0; P_s <= 0; S_s <= 0;
#10 K_s <= 0; P_s <= 1; S_s <= 0;
• Inputs declared as regs so can assign #10 K_s <= 1; P_s <= 1; S_s <= 0;
values (which are held between #10 K_s <= 1; P_s <= 1; S_s <= 1;
assignments) end

– Note module instantiation statement endmodule

and procedure can both appear in one
module

Verilog for Digital Design

Copyright © 2007 22
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vldd_ch2_BeltWarnTB.v
 Recap
• So far:
– Definition, working and testing of module
– Combinational circuit (structure)
• Structure
• Testbench
– You can write two types of modules codes in Verilog
• Structural Verilog Code (when the circuit or structure is given)
• Behavioral Verilog Code (When the circuit or structure is NOT given)
• Remember that testbench for structural as well as behavioral Verilog
Codes remains the same.

• Next:
– Top-Down Design
• Combinational Behavior to Structure
Verilog for Digital Design
Copyright © 2007 23
Frank Vahid and Roman Lysecky
 Top-Down Design – Combinational Behavior to Structure

• In the previous slides, u have seen that how to write the Verilog code if the structure (circuit) is given.
However, in some cases the structure is not known and only the behavior/functionality is given. In other
words, designer may initially know system behavior, but not the structure. For example, consider the
following behavior which has three inputs (K, P and S) and only a single output (W).
– BeltWarn: W = KPS'
• Top-down design
– Capture the behavior, and simulate
– Capture structure (circuit), simulate again
– Gets behavior right first, unfettered by complexity of creating structure

K_s
Capture P_s
Simulate S_s
behavior
W_s
Should be
K_s the same
Capture P_s
Simulate S_s
structure
W_s

Verilog for Digital Design

Copyright © 2007 24
Frank Vahid and Roman Lysecky
Top-Down Design – Combinational Behavior to Structure
Always Procedures with Assignment Statements
`timescale 1 ns/1 ns
• How describe behavior? One way:
module BeltWarn(K, P, S, W);
Use an always procedure
– Sensitive to K, P, and S input K, P, S;
output W;
• Procedure executes only if change reg W;
occurs on any of those inputs
always @(K, P, S) begin
– Simplest procedure uses one W <= K & P & ~S;
end
assignment statement endmodule
• Simulate using testbench (same as
shown earlier) to get waveforms K_s
1
0
• Top-down design 1
P_s
– Proceed to capture structure, 0
1
simulate again using same S_s
0
testbench – result should be the 1
same waveforms W_s
0
time
10 20 30 40 (ns)
Verilog for Digital Design
Copyright © 2007 25
Frank Vahid and Roman Lysecky vldd_ch2_BeltWarnBeh.v
Top-Down Design – Combinational Behavior to Structure
Procedures with Assignment Statements

• Procedural assignment statement `timescale 1 ns/1 ns

– Assigns value to variable module BeltWarn(K, P, S, W);

– Right side may be expression of input K, P, S;

output W;
operators reg W;
• Built-in bit operators include
always @(K, P, S) begin
& → AND | → OR ~ → NOT W <= K & P & ~S;
^ → XOR ~^ → XNOR end
endmodule

– Q: Create an always procedure to

compute:
• F = C'H + CH' vldd_ch2_BeltWarnBeh.v
Answer 1: Answer 2:
always @(C,H) begin always @(C,H)
F <= (~C&H) | (C&~H); begin
end F <= C ^ H;
end

Verilog for Digital Design

Copyright © 2007 26
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Top-Down Design – Combinational Behavior to Structure
Procedures with Assignment Statements

• Procedure may have multiple `timescale 1 ns/1 ns

assignment statements module TwoOutputEx(A, B, C, F, G);

input A, B, C;
output F, G;
reg F, G;

always @(A, B, C) begin

F <= (B & B) | ~C;
G <= (A & B) | (B & C);
end
endmodule

vldd_ch2_TwoOutputBeh.v

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 Top-Down Design – Combinational Behavior to Structure
Procedures with If-Else Statements

• Process may use if-else statements

(a.k.a. conditional statements)
`timescale 1 ns/1 ns
– if (expression)
module BeltWarn(K, P, S, W);
• If expression is true (evaluates to
nonzero value), execute input K, P, S;
corresponding statement(s) output W;
reg W;
• If false (evaluates to 0), execute
else’s statement (else part is always @(K, P, S) begin
if ((K & P & ~S) == 1)
optional)
W <= 1;
• Example shows use of operator == else
→ logical equality, returns true/false W <= 0;
end
(actually, returns 1 or 0) endmodule
• True is nonzero value, false is zero

vldd_ch2_BeltWarnBehIf.v

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 Top-Down Design – Combinational Behavior to Structure
Procedures with If-Else Statements
• More than two possibilities
`timescale 1 ns/1 ns
– Handled by stringing if-else
module Mux4(I3, I2, I1, I0, S1, S0, D);
statements together
• Known as if-else-if construct input I3, I2, I1, I0;
input S1, S0;
• Example: 4x1 mux behavior output D;
reg D;
– Suppose S1S0 change to 01
Suppose always @(I3, I2, I1, I0, S1, S0)
• if’s expression is false begin
S1S0
• else's statement executes, change to if (S1==0 && S0==0)
D <= I0;
which is an if statement 01 else if (S1==0 && S0==1)
whose expression is true D <= I1;
else if (S1==1 && S0==0)
Note: The following indentation shows if D <= I2;
statement nesting, but is unconventional: else
if (S1==0 && S0==0) D <= I3;
end
D <= I0; && → logical AND
else endmodule
if (S1==0 && S0==1)
D <= I1; & : bit AND (operands are bits, returns bit)
else && : logical AND (operands are true/false
if (S1==1 && S0==0) values, returns true/false)
Verilog for Digital Design D <= I2;
Copyright © 2007 else 29
vldd_ch2_Mux4Beh.v
Frank Vahid and Roman Lysecky D <= I3;
Top-Down Design – Combinational Behavior to Structure
Procedures with If-Else Statements
`timescale 1 ns/1 ns

module Dcd2x4(I1, I0, D3, D2, D1, D0);

• Q: Create procedure describing input I1, I0;
behavior of a 2x4 decoder using if- output D3, D2, D1, D0;
else-if construct reg D3, D2, D1, D0;

D0 always @(I1, I0)

I0 D1 begin
if (I1==0 && I0==0)
I1 D2 begin
D3 D3 <= 0; D2 <= 0;
D1 <= 0; D0 <= 1;
2x4 decoder end
else if (I1==0 && I0==1)
Order of assignment statements does begin
D3 <= 0; D2 <= 0;
not matter. D1 <= 1; D0 <= 0;
end
Placing two statements on one line else if (I1==1 && I0==0)
does not matter. begin
D3 <= 0; D2 <= 1;
D1 <= 0; D0 <= 0;
To execute multiple statements if end
expression is true, enclose them else
begin
between "begin" and "end" D3 <= 1; D2 <= 0;
Verilog for Digital Design D1 <= 0; D0 <= 0;
Copyright © 2007 end vldd_ch2_Dcd2x4Beh.v 30
Frank Vahid and Roman Lysecky end
endmodule
 Top-Down Design – Combinational Behavior to Structure
`timescale 1 ns/1 ns

module BeltWarn(K, P, S, W);

• Top-down design input K, P, S;

output W;
– Capture behavior, and simulate reg W;

– Capture structure using a second always @(K, P, S) begin

W <= K & P & ~S;
module, and simulate end
– The test bench will be the same endmodule
K_s vldd_ch2_BeltWarnBeh.v
Capture P_s
Simulate S_s `timescale 1 ns/1 ns
behavior
W_s
Should be module BeltWarn(K, P, S, W);
K_s the same input K, P, S;
Capture P_s
Simulate S_s output W;
structure
W_s
wire N1, N2;

And2 And2_1(K, P, N1);

Inv Inv_1(S, N2);
And2 And2_2(N1, N2, W);

Verilog for Digital Design endmodule

vldd_ch2_BeltWarnStruct.v
Copyright © 2007 31
Frank Vahid and Roman Lysecky
 Top-Down Design – Combinational Behavior to Structure
Common Pitfall – Missing Inputs from Event Control Expression
• Pitfall – Missing inputs from event
control’s sensitivity list when describing
combinational behavior
`timescale 1 ns/1 ns
– Results in sequential behavior
module Mux4(I3, I2, I1, I0, S1, S0, D);
– Wrong 4x1 mux example Missing I3-I0 from
sensitivity list input I3, I2, I1, I0;
• Has memory
input S1, S0;
• No compiler error Recomputes D if S1 output D;
or S0 changes reg D;
– Just not a mux
Fails to recompute D if I3 always @(S1, S0)
(or I2, I1, I0) changes begin
Reminder if (S1==0 && S0==0)
• Combinational behavior: Output I1 D <= I0;
value is purely a function of the else if (S1==0 && S0==1)
I3 D <= I1;
present input values
else if (S1==1 && S0==0)
• Sequential behavior: Output D <= I2;
S1
value is a function of present and else
past input values, i.e., the system S0 D <= I3;
has memory end
D endmodule
Verilog for Digital Design
Copyright © 2007 32
Frank Vahid and Roman Lysecky vldd_ch2_Mux4Wrong.v
 Top-Down Design – Combinational Behavior to Structure
Common Pitfall – Missing Inputs from Event Control Expression
• Verilog provides mechanism to help avoid
this pitfall
– @* – implicit event control expression
`timescale 1 ns/1 ns
• Automatically adds all nets and variables
that are read by the controlled statement or module Mux4(I3, I2, I1, I0, S1, S0, D);
statement group input I3, I2, I1, I0;
• Thus, @* in example is equivalent to input S1, S0;
output D;
@(S1,S0,I0,I1,I2,I3) reg D;
• @(*) also equivalent
always @*
begin
if (S1==0 && S0==0)
D <= I0;
else if (S1==0 && S0==1)
D <= I1;
else if (S1==1 && S0==0)
D <= I2;
else
D <= I3;
end
endmodule
Verilog for Digital Design
Copyright © 2007 33
Frank Vahid and Roman Lysecky
Top-Down Design – Combinational Behavior`timescale 1 ns/1 ns
to Structure module Dcd2x4(I1, I0, D3, D2, D1, D0);
Common Pitfall – Output not Assigned on Every Pass input I1, I0;
output D3, D2, D1, D0;
• Pitfall – Failing to assign every output reg D3, D2, D1, D0;

on every pass through the procedure always @(I1, I0)

begin
for combinational behavior if (I1==0 && I0==0)
– Results in sequential behavior begin
D3 <= 0; D2 <= 0;
• Referred to as inferred latch (more later) D1 <= 0; D0 <= 1;
– Wrong 2x4 decoder example end
else if (I1==0 && I0==1)
• Has memory begin
Missing assignments to
• No compiler error outputs D2, D1, D0 D3 <= 0; D2 <= 0;
D1 <= 1; D0 <= 0;
– Just not a decoder
end
I1I0=10 → D2=1, else if (I1==1 && I0==0)
others=0 begin
I1I0=11 → D3=1, D3 <= 0; D2 <= 1;
D1 <= 0; D0 <= 0;
but D2 stays same
end
else if (I1==1 && I0==1)
I1 begin
D3 <= 1;
I0
end
// Note: missing assignments
D3
// to every output in last "else if"
end
D2
Verilog for Digital Design endmodule
Copyright © 2007 vldd_ch2_Dcd2x4Wrong.v 34
Frank Vahid and Roman Lysecky
Top-Down Design – Combinational Behavior to Structure
Common Pitfall – Output not Assigned on Every Pass
• Same pitfall often occurs due to not considering all
possible input combinations

if (I1==0 && I0==0)

begin
D3 <= 0; D2 <= 0;
D1 <= 0; D0 <= 1;
end
else if (I1==0 && I0==1)
begin
D3 <= 0; D2 <= 0;
D1 <= 1; D0 <= 0;
end
else if (I1==1 && I0==0)
begin
D3 <= 0; D2 <= 1; Last "else" missing, so not all
D1 <= 0; D0 <= 0; input combinations are covered
end
(i.e., I1I0=11 not covered)

Verilog for Digital Design

Copyright © 2007 35
Frank Vahid and Roman Lysecky
 Hierarchical Circuits

Verilog for Digital Design

Copyright © 2007 36
Frank Vahid and Roman Lysecky
 Hierarchical Circuits
Using Modules Instances in Another Module
• Module can be used as instance in a new module
– As seen earlier: And2 module used as instance in BeltWarn module
– Can continue: BeltWarn module can be used as instance in another
module
• And so on
• Hierarchy powerful mechanism for managing complexity

BeltWarn

Display
WindowLock

X BeltWarn
F
Y

Verilog for Digital Design

Copyright © 2007 37
Frank Vahid and Roman Lysecky
 Hierarchical Circuits
Using Module Instances in Another Module
• 4-bit 2x1 mux example `timescale 1 ns/1 ns

module Mux2(I1, I0, S0, D);

2x1 mux circuit from earlier Mux2 input I1, I0;
I0 input S0;
D
N2 I1 output D;
I0 S0
N1 D
N3 wire N1, N2, N3;
I1
Inv Inv_1 (S0, N1);
And2 And2_1 (I0, N1, N2);
Mux2 And2 And2_2 (I1, S0, N3);
Or2 Or2_1 (N2, N3, D);
S0
endmodule

Verilog for Digital Design

Copyright © 2007 vldd_ch2_Mux2Struct.v
38
Frank Vahid and Roman Lysecky
 Hierarchical Circuits
Using Module Instances in Another Module
• 4-bit 2x1 mux example
`timescale 1 ns/1 ns
Create four Mux2 A3 Mux2_4b
A2 module Mux2_4b(A3, A2, A1, A0,
instances C3
B3, B2, B1, B0,
A1 C2
Mux2_4b S0,
A0 C1 C3, C2, C1, C0);
Mux2 C0
A3 I0 B3
D C3 input A3, A2, A1, A0;
B3 I1 B2
S0 input B3, B2, B1, B0;
B1
input S0;
B0
A2 I0 Mux2 output C3, C2, C1, C0;
D C2
B2 I1 S0
S0 Mux2 Mux2_3 (B3, A3, S0, C3);
Can then use Mux2 Mux2_2 (B2, A2, S0, C2);
A1 I0 Mux2 C1 Mux2_4b in Mux2 Mux2_1 (B1, A1, S0, C1);
D Mux2 Mux2_0 (B0, A0, S0, C0);
B1 I1 another module’s
S0
circuit, and so on ... endmodule
A0 I0 Mux2
D C0
B0 I1
S0
s0

Verilog for Digital Design

Copyright © 2007 39
vldd_ch2_Mux2_4bStruct.v
Frank Vahid and Roman Lysecky
 Built-In Gates

Verilog for Digital Design

Copyright © 2007 40
Frank Vahid and Roman Lysecky
 Built-In Gates
• We previously defined AND, OR, and
NOT gates
• Verilog has several built-in gates that
can be instantiated
– and, or, nand, nor, xor, xor
• One output, one or more inputs `timescale 1 ns/1 ns
• The output is always the first in the list module BeltWarn(K, P, S, W);
of port connections
input K, P, S;
– Example of 4-input AND: output W;
and a1 (out, in1, in2, in3, in4); wire N1, N2;
– not is another built-in gate
and And_1(N1, K, P);
• Earlier BeltWarn example using built- not Inv_1(N2, S);
and And_2(W, N1, N2);
in gates
endmodule
– Note that gate size is automatically
determined by the port connection list
vldd_ch2_BeltWarnGates.v
Verilog for Digital Design
Copyright © 2007 41
Frank Vahid and Roman Lysecky