Lab 2
Lab 2
1. Start Logisim
6. Set the pins in the following order and record the states for Q and Q’
Set Reset Q Q’
1 0
1 1
0 1
1 1
7. Describe in a sentence, the behaviour of the circuit when one of the inputs is 1 (but not
both) and why this is useful for digital circuit design.
8. What do you notice about the two times you set both inputs to 1. Briefly explain what is
happening here and why this is an issue for digital circuit design ?
Discuss 7 and 8 with your lab demonstrator and provide your answer in your submis-
sion document, along with the truth table in Step 6.
9. So the unclocked R-S flip flop has issues. Lets talk about the D Flip-Flop then. Review
the lectures on the D Flip-Flop, and when you feel comfortable, wire up a D Flip Flip using
AND gates and NOR gates, with output LEDS labeled Q and Q’.
■
For this you will have only 1 input pin, as well as a clock input. The clock can be pulsed
on and off by clicking it with the operation pointer (the finger in the top left of screen), or
you can simple enable clock ticking from the menu (under “Simulate”).
Export your circuit as an image and include it in your submission document.
10. Explore the behaviour of the D Flip Flop by filling out the following truth table
Clock Pin Q Q’
0 0
0 1
1 1
1 0
11. Briefly explain the behaviour of a D Flip Flop and how it is useful for digital circuit design.
12. What is the role of the clock ? How does it impact the changing of state of Q and Q’ ?
13. Why is it generally preferred over the R-S Flip Flop ?
Discuss 11 -13 with your lab demonstrator and provide your answer in your submission
document, along with the truth table above.
14. J-K Flip Flops are like your general purpose Flip Flop because they are programmable.
Review the video on JK Flip Flops, and when you’re feeling comfortable, wire up a J-K FF
using NAND gates. Two of your NAND gates will need to deal with three inputs.
Logisim will not be able to simulate this circuit, but export your completed circuit as an
image and include it in your submission document.
15. Complete and include this truth table for JK Flip Flops in your submission docu-
ment.
J K Q (when clocked) Q’ (when clocked)
0 0
1 0
0 1
1 1
16. How can a J-K Flip Flop be made to behave like a D Flip Flop ?
17. How can a J-K Flop Flop be made to behave like a toggle (T Flip Flop) ?
Discuss these questions with your lab demonstrator and provide your answer in your
submission document, along with the truth table in Step 15.
22. Use your register to fill out the following test schedule:
0 0000 0000
1 0001
2 0010