Binding of Instructions and Data to

Memory
Address binding of instructions and data to memory addresses can
happen at three different stages.

Compile time: If memory location known a

Memory Management priori, absolute code can be generated; must
recompile code if starting location changes.
Lectures notes from the text Load time: Must generate relocatable code if
supplement by Siberschatz and Galvin memory location is not known at compile time.
Modified by B.Ramamurthy Execution time: Binding delayed until run
Chapter 9 time if the process can be moved during its
execution from one memory segment to
another. Need hardware support for address
maps (e.g., base and limit registers).

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Dynamic relocation using a relocation register

Dynamic Loading
Routine is not loaded until it is called
Better memory-space utilization;
unused routine is never loaded.
Useful when large amounts of code are
needed to handle infrequently occurring
cases.
No special support from the operating
system is required implemented
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Dynamic Linking Overlays

Linking postponed until execution time. Keep in memory only those instructions and
Small piece of code, stub, used to locate the data that are needed at any given time.
appropriate memory- resident library routine.
Stub replaces itself with the address of the Needed when process is larger than amount
routine, and executes the routine. of memory allocated to it.
Operating system needed to check if routine
is in processes’ memory address. Implemented by user, no special support
Dynamic linking is particularly useful for needed from operating system, programming
libraries. design of overlay structure is complex

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1
 Schematic View of Swapping
Swapping
A process can be swapped temporarily out of
memory to a backing store, and then brought back
into memory for continued execution.
Backing store – fast disk large enough to
accommodate copies of all memory images for all
users; must provide direct access to these memory
images.
Roll out, roll in – swapping variant used for priority-
based scheduling algorithms; lower-priority process is
swapped out so higher-priority process can be loaded
and executed.

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Hardware Support for Relocation and

Contiguous Allocation Limit Registers
Main memory usually into two partitions:
„ Resident operating system, usually held in low

memory with interrupt vector.

„ User processes then held in high memory.

Single-partition allocation
„ Relocation-register scheme used to protect user

processes from each other, and from changing

operating-system code and data.
„ Relocation register contains value of smallest

physical address; limit register contains range of

logical addresses – each logical address must be
less than the limit register.
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Dynamic Storage-Allocation
Contiguous Allocation (Cont.) Problem
Multiple-partition allocation How to satisfy a request of size n from a list of free holes.
„ Hole – block of available memory; holes of various size are
scattered throughout memory.
First-fit: Allocate the first hole that is big
„ When a process arrives, it is allocated memory from a hole
enough.
large enough to accommodate it.
„ Operating system maintains information about:
Best-fit: Allocate the smallest hole that is big
a) allocated partitions b) free partitions (hole) enough; must search entire list, unless ordered
OS OS OS OS
by size. Produces the smallest leftover hole.
process 5 process 5 process 5 process 5
Worst-fit: Allocate the largest hole; must also
process 9 process 9 search entire list. Produces the largest leftover
process 8 process 10
hole.
First-fit and best-fit better than worst-fit in
process 2 process 2 process 2 process 2
terms of speed and storage utilization.
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2
Fragmentation Paging
External Fragmentation – total memory space exists to Logical address space of a process can be noncontiguous;
satisfy a request, but it is not contiguous. process is allocated physical memory whenever the latter is
Internal Fragmentation – allocated memory may be slightly available.
larger than requested memory; this size difference is memory Divide physical memory into fixed-sized blocks called frames
internal to a partition, but not being used.
(size is power of 2, between 512 bytes and 8192 bytes).
Reduce external fragmentation by compaction
Divide logical memory into blocks of same size called pages.
„ Shuffle memory contents to place all free memory together
in one large block. Keep track of all free frames.
„ Compaction is possible only if relocation is dynamic, and is To run a program of size n pages, need to find n free frames
done at execution time. and load program.
„ I/O problem Set up a page table to translate logical to physical addresses.
Š Latch job in memory while it is involved in I/O. Internal fragmentation.
Š Do I/O only into OS buffers.

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Address Translation
Address Translation Scheme Architecture
Address generated by CPU is divided
into:
„ Page number (p) – used as an index into a
page table which contains base address of
each page in physical memory.

„ Page offset (d) – combined with base

address to define the physical memory
address that is sent to the memory unit.
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Paging Example Paging Example

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Free Frames Implementation of Page Table
Page table is kept in main memory.
Page-table base register (PTBR) points to the page
table.
Page-table length register (PRLR) indicates size of
the page table.
In this scheme every data/instruction access requires
two memory accesses. One for the page table and
one for the data/instruction.
The two memory access problem can be solved by
the use of a special fast-lookup hardware cache
Before allocation After allocation called associative memory or translation look-aside
buffers (TLBs)
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Paging Hardware With TLB Effective Access Time

Associative Lookup = ε time unit
Assume memory cycle time is 1 microsecond
Hit ratio – percentage of times that a page
number is found in the associative registers;
ration related to number of associative
registers.
Hit ratio = α
Effective Access Time (EAT)
EAT = (1 + ε) α + (2 + ε)(1 – α)
=2+ε–α
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Inverted Page Table

Inverted Page Table Architecture
One entry for each real page of memory.
Entry consists of the virtual address of the page
stored in that real memory location, with information
about the process that owns that page.
Decreases memory needed to store each page table,
but increases time needed to search the table when a
page reference occurs.
Use hash table to limit the search to one — or at
most a few — page-table entries.

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