1

8051 TIMERS/COUNTERS

P. Pavan Kumar, Assistant Professor, MVGRCE(A)

 Inside Architecture of 8051
2

External interrupts
On-chip Timer/Counter

Interrupt ROM for

On-chip Timer 1 Counter
Control program
RAM Timer 0 Inputs
code

CPU

Bus Serial
4 I/O Ports
OSC Control Port

P0 P1 P2 P3 TxD RxD
Address/Data
Figure 1-2. Inside the 8051 Microcontroller Block Diagram
 Timers /Counters
3

 The 8051 has 2 timers/counters: timer/counter 0 and

timer/counter 1. They can be used as
1. The timer is used as a time delay generator.
 The clock source is the internal crystal frequency of the
8051.
2. An event counter.
 External input from input pin to count the number of
events on registers.
 These clock pulses cold represent the number of people
passing through an entrance, or the number of wheel
rotations, or any other event that can be converted to
pulses.
 Timer
4

 8051 timers use 1/12 of XTAL frequency as the

input of timers, regardless of machine cycle.
 Because the input of timer is a regular, fixed-
periodic square wave, we can count the number
of pulses and calculate the time delay.
8051
XTAL
÷ 12 Timer
oscillator
P1 to
LCD
TH0
Set
TL0
Timer 0
 Counter
5

 Count the number of events

 External input from Tx input pin (Timer pin x=0 or 1).
 We use Tx to denote T0 or T1.
 External input from T0 input pin (P3.4) for Counter 0
 External input from T1 input pin (P3.5) for Counter 1
8051
TH0
P1 to
TL0
LCD
Vcc P3.4
a switch T0
 Timer/Counter 0
6

timer input

XTAL
÷ 12
oscillator
C/T = 0

TH0 TL0
C/T = 1
counter input
T0 Pin
1:start
Pin 3.4
TR0 TF0
0:stop

Gate
1. monitor by JNB
INT0 Pin
Pin 3.2 2. interrupt
hardware control
 Timer/Counter 1
7

timer input

XTAL
÷ 12
oscillator
C/T = 0

TH1 TL1
counter input
C/T = 1
T1 Pin
1:start
Pin 3.5
TR1 TF1
0:stop

Gate
1. monitor by JNB
INT1 Pin 2. interrupt
Pin 3.3
hardware control
 Registers Used in Timer/Counter
8

 TH0, TL0 (Timer 0 registers)

 TH1, TL1 (Timer 1 registers)
 TMOD (Timer mode register)
 TCON (Timer control register)
 Since 8052 has 3 timers/counters, the formats of
these control registers are different.
 T2CON (Timer 2 control register), TH2 and TL2 used for
8052 only.
 Basic Registers of the Timer
9

 Both Timer 0 and Timer 1 are 16 bits wide.

 Each 16-bit timer can be accessed as two separate
registers of low byte and high byte.
 Timer 0: TH0 & TL0
 Timer 0 high byte, timer 0 low byte
 Timer 1: TH1 & TL1
 Timer 1 high byte, timer 1 low byte
 These registers stores
 the time delay as a timer
 the number of events as a counter
 Timer Registers
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TH0 TL0

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Timer 0

TH1 TL1

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Timer 1
 TCON Register (1/2)
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 Timer control register: TCON

 Upper nibble for control and status indication of
timer/counter, lower nibble for control and status indication
of interrupts
 TR (Timer Run control bit)
 TR0 for Timer/counter 0; TR1 for Timer/counter 1.
 TRx is set by programmer to turn timer/counter ON/OFF.
 TRx=0: OFF (stop)
 TRx=1: ON (start)
(MSB) (LSB)
TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
Timer 1 Timer 0 For Interrupts
 TCON Register (2/2)
12

 TF (Timer Flag, control flag)

 TF0 for timer/counter 0; TF1 for timer/counter 1.
 TFx is like a carry. Originally, TFx=0. When TH-TL roll
over to 0000 from FFFFH, the TFx is set to 1.
 TFx=0 : no overflow
 TFx=1: overflow
 If we enable interrupt, TFx=1 will trigger ISR.

(MSB) (LSB)
TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
Timer 1 Timer 0 For Interrupts
 Equivalent Instructions for the Timer
Control Register
13

For timer 0
SETB TR0 = SETB TCON.4
CLR TR0 = CLR TCON.4

SETB TF0 = SETB TCON.5

CLR TF0 = CLR TCON.5
For timer 1
SETB TR1 = SETB TCON.6
CLR TR1 = CLR TCON.6

SETB TF1 = SETB TCON.7

CLR TF1 = CLR TCON.7
TCON: Timer/Counter Control Register
TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
 TMOD Register
14

 Timer mode register: TMOD

MOV TMOD,#21H
 An 8-bit register

 Set the usage mode for two timers

 Set lower 4 bits for Timer 0 (Set to 0000 if not used)
 Set upper 4 bits for Timer 1 (Set to 0000 if not used)
 Not bit-addressable
(MSB) (LSB)
GATE C/T M1 M0 GATE C/T M1 M0
Timer 1 Timer 0
 TMOD Register
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GATE Gating control when set (Gate=1). Timer/counter is

enabled only while the INTx pin is high and the TRx
control pin is set. When cleared (Gate=0), the timer is
enabled whenever the TRx control bit is set.
C/T Timer or counter selected cleared for timer operation
(input from internal system clock). Set for counter
operation (input from Tx input pin).
M1 Mode selection bit 1
M0 Mode selection bit 0
(MSB) (LSB)
GATE C/T M1 M0 GATE C/T M1 M0
Timer 1 Timer 0
 C/T (Clock/Timer)
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 This bit is used to decide whether the timer is used as a

interval timer/delay generator (Timer) or an external
event counter (Counter).
 C/T = 0 : Timer
 C/T = 1 : Counter
 The interval timer means calculating the time elapsed
between events or generating a delay.
 Event counter means to count the pulses that are
generated by external events.
 The only difference between timing and counting
operation is the clock source used by the timer circuit.
 Gate
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 Every timer has a mean of starting and stopping.

 GATE=0
 Internal control
 The start and stop of the timer are controlled by software.
 Set/clear the TR0 (or TR1) for start/stop timer.
 GATE=1
 External control
 The hardware way of starting and stopping the timer by software
and an external source.
 Timer/counter is enabled only while the INT0 (or INT1) pin has an
1 to 0 transition and the TR0 (or TR1) control pin is set.
 INT0: P3.2, pin 12; INT1: P3.3, pin 13.
 M1, M0
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 M0 and M1 can be configured to select the timer mode

for timers 0 & 1.

M1 M0 Mode Operating Mode

0 0 0 13-bit timer mode
8-bit THx + 5-bit TLx (x= 0 or 1)
0 1 1 16-bit timer mode
8-bit THx + 8-bit TLx (x= 0 or 1)
1 0 2 8-bit auto reload
8-bit auto reload timer/counter;
THx holds a value which is to be reloaded into
TLx each time it overflows.
1 1 3 Split timer mode
 Mode 0
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 Mode 0: In this timer mode, the timer behaves as a

13 bit timer, where THx will be operated as 8-bit
timer and TLx will be operated as 5-bit timer.
 Mode 0 is kept in 8051 only to maintain
compatibility with the previous version of
microcontroller, the 8048.
 This mode is rarely used in 8051 based systems.
 Mode 1
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 In this timer mode, the timer behaves as a 16-bit

timer.
 Timer registers TLx and THx behaves as eight bit up
counters and collectively they form 16-bit up
counter, allowing any value between 0000H to
FFFFH to be loaded in these registers.
 Mode 2
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 In this timer mode, the timer behaves like an 8-bit

timer. The timer value is updated in the lower byte of
the timer register.
 The higher byte of timer register is responsible for
loading the value into the lower byte.
 Once the value is loaded, from that value the lower
byte of timer register gets updated (up-counted) till
the maximum value (FFH) is reached.
 When maximum value is reached, the timer overflows
and again the lower byte of timer register is loaded
with a value to start count by higher byte.
 Mode 3
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 In this timer mode, the timer behave as two

completely separate 8-bit timers, TL0 as an 8-bit
interval timer/event counter controlled by the Timer
0 control bits of TMOD register and TH0 acts only
as an 8-bit interval timer controlled by Timer 1 bits
of TMOD register.
 Timer mode 3 is also called as Split timer mode.
 Timer 1 cannot be used in applications where
interrupt is needed as its control bits of TMOD
register are assigned for TH0 of Timer 0.