Computer Organization and Architecture

Designing for Performance

11th Edition

Chapter 13:
Instruction Sets:
Characteristics and Functions.

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Machine Instruction Characteristics
• Operation code: Specifies the operation to be performed
(ADD, I/O), it is referred to as machine instructions or
computer instructions
• Source operand reference: The operation may involve one
or more source operands, that is, operands that are inputs
for the operation.
• The collection of different instructions that the processor
can execute is referred to as the processor’s instruction set
• Each instruction must contain the information required by
the processor for execution
• Result operand reference: The operation may produce a
result.

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Figure 13.2: A Simple Instruction Format

• Within the computer each instruction is represented by a

sequence of bits
• The instruction is divided into fields, corresponding to the
constituent elements of the instruction

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Source and result operands can be in one of
four areas:
1)Main or virtual memory 3) Processor register
– A processor contains one or more
– As with next instruction references,
registers that may be referenced
the main or virtual memory address
by machine instructions.
must be supplied
– If more than one register exists
each register is assigned a unique
name or number and the
instruction must contain the
number of the desired register

2) I/O device
– The instruction must specify the I/O 4) Immediate
module and device for the operation. – The value of the operand is
If memory-mapped I/O is used, this is contained in a field in the
just another main or virtual memory instruction being executed
address
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Designation of Registers
• Registers are designated
– By capital letters (e.g., A, IR)
– Sometimes followed by numbers (e.g., R13)
• Often the names indicate function:
– MAR - memory address register
– PC - program counter
– IR - instruction register
• Designation of a register
– a register: R1
– portion of a register : PC(H), IR(0-11)
– a bit of a register : IR(15)
• Common ways of drawing the block diagram of a register
Register R Showing individual bits
R1 7 6 5 4 3 2 1 0

15 0 15 8 7 0
R2 PC(H) PC(L)
Numbering of bits Divided into two parts

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 Register Transfer
• Register transfer: Copying the contents of one register to
another
• Notation of a register transfer: R2 ← R1
– The contents of register R1 are copied (loaded) into register R2
– A simultaneous transfer of all bits from R1 to R2, during one clock
pulse
– non-destructive: the contents of R1 are not altered

• Note: A register transfer such as: R3 ← R5

Implies that the digital system has :
– Data lines from the src register (R5) to the dst register (R3)
– Parallel load in the destination register (R3)
– Control lines to perform the action

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Instruction Representation
• Opcodes are represented by abbreviations called mnemonics
• Examples include:
– ADD Add
– SUB Subtract
– MUL Multiply
– DIV Divide
– LOAD Load data from memory
– STOR Store data to memory
• Operands are also represented symbolically
• Each symbolic opcode has a fixed binary representation
– The programmer specifies the location of each symbolic operand

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 Reverse Polish Notation
• Common Arithmetic Expression: A + B
A+B Infix notation
+AB Prefix notation or Polish notation
AB+ Postfix notation or reverse Polish notation
- reverse Polish notation: very suitable for stack
manipulation
• Evaluation of Arithmetic Expressions
– Any arithmetic expression can be expressed in
parenthesis-free (reverse) Polish notation
– A * B + C * D => AB*CD*+
– (A + B) * [C * (D + E) + F] => AB + DE + C * F + *

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 Reverse Polish Notation (cont.)
• Arithmetic Expressions are evaluated as follows:
– Scan expression from left to right
– When an operator is reached, perform the operation with
two operands found on the left side of the operator.
– Remove the two operands and the operator and replace
them by the number obtained from the result of the
operation.
– Repeat the procedure for every operator until there are
no more operators

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In Class Activity
Convert the following arithmetic expressions
from reverse Polish notation to infix notation.
•A B C * / D – E F / +

•Solution:
𝐴𝐴 𝐸𝐸
− 𝐷𝐷 +
B∗C 𝐹𝐹

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 In Class Activity-Solution
Convert the following numerical arithmetic expression
into reverse Polish notation and show the stack
operations for evaluating the numerical result.
(3 + 4)[ 10 (2 + 6) + 8]
Solution:
(3 + 4) [10 (2 + 6) + 8] = 616
RPN: 3 4 + 2 6 + 10 * 8 + *

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Table 13.1: Utilization of Instruction
Addresses (Nonbranching Instructions)
Number of Symbolic Interpretation
Addresses Representation
3 OP A, B, C A ← B OP C
2 OP A, B A ← A OP B
1 OP A AC ← AC OP A
3 OP T ← (T – 1) OP T

AC = accumulator
T = top of stack
(T – 1) = second element of stack
A, B, C = memory or register locations

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 𝐀𝐀 – 𝐁𝐁
Figure 13.3: Programs to Execute Y =
𝐂𝐂 + (𝐃𝐃×𝐄𝐄)

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Three-, Two-address Instructions
• Three-address Instructions (specify operand either a
processor register or a memory).
– Program to evaluate X = (A + B) * (C + D) :
ADD R1, A, B /* R1 ← M[A] + M[B] */
ADD R2, C, D /* R2 ← M[C] + M[D] */
MUL X, R1, R2 /* M[X] ← R1 * R2 */
– Results in short program
– Instruction becomes long (many bits)
• Two-address Instructions (it is the most common in
commercial computers)
– Program to evaluate X = (A + B) * (C + D) :
MOV R1, A /* R1 ← M[A] */
ADD R1, B /* R1 ← R1 + M[B] */
MOV R2, C /* R2 ← M[C] */
ADD R2, D /* R2 ← R2 + M[D] */
MUL R1, R2 /* R1 ← R1 * R2 */
MOV X, R1 /* M[X] ← R1 */

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 One-, Zero-address Instructions
• One-address Instructions
– Use an implied AC register for all data manipulation
– Program to evaluate X = (A + B) * (C + D) :
LOAD A /* AC ← M[A] */
ADD B /* AC ← AC + M[B] */
STORE T /* M[T] ← AC */
LOAD C /* AC ← M[C] */
ADD D /* AC ← AC + M[D] */
MUL T /* AC ← AC * M[T] */
STORE X /* M[X] ← AC */
• Zero-address Instructions
Can be found in a stack-organized computer
Program to evaluate X = (A + B) * (C + D) :
PUSH A /* TOS ← A */
PUSH B /* TOS ←B */
ADD /* TOS ← (A + B) */
PUSH C /* TOS ←C */
PUSH D /* TOS ←D */
ADD /* TOS ← (C + D) */
MUL /* TOS ← (C + D) * (A + B) */
POP X /* M[X] ← TOS */
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 ARM Data Types
ARM processors support data types of:
• 8 (byte)
• 16 (halfword)
• 32 (word) bits in length

Alignment checking
All three data types can also • When the appropriate control bit is
be used for twos complement set, a data abort signal indicates an
signed integers alignment fault for attempting
unaligned access

For all three data types an

unsigned interpretation is Unaligned access
supported in which the • When this option is enabled, the
value represents an processor uses one or more memory
accesses to generate the required
unsigned, nonnegative transfer of adjacent bytes
integer transparently to the programmer

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Figure 13.5: ARM Endian Support—Word
Load/Store with E-Bit

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Arithmetic
• Most machines provide the basic arithmetic operations of
add, subtract, multiply, and divide
• These are provided for signed integer (fixed-point) numbers
• Often, they are also provided for floating-point and packed
decimal numbers
• Other possible operations include a variety of single-
operand instructions:
– Absolute: Take the absolute value of the operand
– Negate: Negate the operand
– Increment: Add 1 to the operand
– Decrement: Subtract 1 from the operand

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Arithmetic Microoperations

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Table 13.6: Basic Logical Operations

P Q NOT P P AND Q P OR Q P XOR Q P = Q

0 0 1 0 0 0 1
0 1 1 0 1 1 0

1 0 0 0 1 1 0
1 1 0 1 1 0 1

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Logic Microoperations

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HW Implementation of Logic Microoperations

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Applications of Logic Microoperations

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Selective Set, Selective Complement

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Selective Clear, Mask Operation
• Selective clear: The bit pattern in B is used to clear certain
bits in A
– If a bit in B is set to 1, the same position in A gets set to 0,
– Otherwise, it is unchanged
• Example
1 1 0 0 At
1010 B
0 1 0 0 At+1 (A ← A ∧ B’)

• Mask operation: the bit pattern in B is used to clear certain

bits in A
– If a bit in B is set to 0, the same position in A gets set to 0,
– Otherwise, it is unchanged
• Example
1 1 0 0 At
1010 B
1 0 0 0 At+1 (A ← A ⋅ B)
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Clear Operation

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Insert Operation

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In Class Activity
Q: Register A holds the 8-bit binary 11011001 .
Determine the B operand and the logic microoperation
to be performed in order to change the value in A to:
a- 01101101
b. 11111101

Solution
A = 11011001⊕ A= 11011001(OR)
B = 10110100 B= 111 11101
A ← A ⊕ B 01101101 11111101 A ← AVB

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Shift Microoperations

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Logical Shift

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 Logical Shift-2

Logical left shift one bit Logical right shift one bit

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Arithmetic Shift

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Arithmetic Shift

Left arithmetic shift Right arithmetic shift

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Arithmetic Shift’

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Circulate Shift

Left circular shift Right circular shift.

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Figure 13.6: Summarizes of Shift and Rotate Operations

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Table 13.7
Examples of Shift and Rotate Operations
Input Operation Result

10100110 Logical right shift (3 bits) 00010100

10100110 Logical left shift (3 bits) 00110000

10100110 Arithmetic right shift (3 bits) 11110100

10100110 Arithmetic left shift (3 bits) 10110000

10100110 Right rotate (3 bits) 11010100

10100110 Left rotate (3 bits) 00110101

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HW Implementation of Shift Microoperations

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 Arithmetic Logic Shift Unit

arithmetic
operation

logic
operations
shift
operations
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Transfer of Control
• Reasons why transfer-of-control operations are required:
– It is essential to be able to execute each instruction more than once
– Virtually all programs involve some decision making
– It helps if there are mechanisms for breaking the task up into smaller
pieces that can be worked on one at a time

• Most common transfer-of-control operations found in

instruction sets:
– Branch
– Skip
– Procedure call

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Program Control Instructions
+1
In-Line Sequencing
(Fetch next instr from the next adjacent location in the
memory)
Address from other source (Current instr, Stack, etc.):
Branch, Conditional Branch, Subroutine, etc.
 Program Control Instructions

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Figure 13.7: Branch Instructions

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 Flag, Processor Status Word
• In BC processor,
– The processor has several (status) flags
– Each flag is 1 bit value that indicates various info about the processor’s state
– E, FGI, FGO, I, IEN, R

• In some other processors,

– Flags are often combined into a register
▪ processor status register (PSR) or processor status word (PSW)

• Common flags in PSW :

– C (Carry): 1 if the carry out of the ALU is 1
– S (Sign): the MSB bit of the ALU’s output
– Z (Zero): 1 if the ALU’s output is all 0’s
– V (Overflow): 1 if there is an overflow

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Subroutine Call and Return
• Subroutine Call Instructions (instr that transfer program control
to a subroutine):
– aka: Call subroutine, Jump to subroutine, Branch to subroutine,
Branch and save return address
• Two most important operations :
1. Save the return address to get the address of the location in the
calling program upon exit from the subroutine
2. Branch to the beginning of the subroutine (Same as the branch or
conditional branch)
• Locations for storing return address :
– Fixed location in the subroutine (memory)
– Fixed Location in memory
– In a processor register
– In memory stack -- most efficient way
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x86 Operation Types
• The x86 provides a complex array of operation types including a number
of specialized instructions
• The intent was to provide tools for the compiler writer to produce
optimized machine language translation of high-level language
programs
• Provides four instructions to support procedure call/return:
– CALL
– ENTER
– LEAVE
– RETURN
• When a new procedure is called the following must be performed upon
entry to the new procedure:
– Push the return point on the stack
– Push the current frame pointer on the stack
– Copy the stack pointer as the new value of the frame pointer
– Adjust the stack pointer to allocate a frame

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 Code Symbol Condition Tested Comment
0000 EQ Z=1 Equal
0001 NE Z=0 Not equal
Table 13.11 0010 CS/HS C=1 Carry set/unsigned higher or same

ARM 0011 CC/LO C=0 Carry clear/unsigned lower

Conditions
00100 MI N=1 Minus/negative
00101 PL N=0 Plus/positive or zero
for 00110 VS V=1 Overflow

Conditional 00111 VC V=0 No overflow

1000 HI C = 1 AND Z = 0 Unsigned higher
Instruction 1001 LS C = 0 OR Z = 1 Unsigned lower or same
Execution 1010 GE N=V Signed greater than or equal
[(N = 1 AND V = 1)
OR (N = 0 AND V = 0)]
1011 LT N≠V Signed less than
[(N = 1 AND V = 0)
OR (N = 0 AND V = 1)]
1100 GT (Z = 0) AND (N = V) Signed greater than
1101 LE (Z = 1) OR (N ≠ V) Signed less than or equal
1110 AL – Always (unconditional)
1111 – – This instruction can only be executed
unconditionally
(Table can be found on page 465 in the textbook.)
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 Conditional Branch Instructions

47

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 Conditional Branch Instr. (cont.)
• Subtraction is done in the same way in both signed and
unsigned numbers.
– For example, to evaluate (A – B) it is computed as the
result of adding A to the 2’s complement of B.

• Let A = 11110000, and B = 00010100

• To perform A – B, the ALU takes 2’s comp of B
(11101100) and adds it to A
– So, A-B = 11110000 + 11101100 = 11011100
– And flags C = 1, S = 1, V = 0, Z = 0
– A-B = 11011100, C=1, S=1, V=0, Z=0

48

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 Conditional Branch Instr. (cont .)
• If we assume unsigned numbers
– A = 240, B = 20 , A-B = 220.
– A > B, A ≠ B, (C = 1, Z = 0),
– So the instr that will cause branch after this comparison will be
BHI, BHE, and BNE.

• If we assume signed numbers

– A = -16, B = 20 , A-B = -36.
– A < B, A ≠ B, (S = 1, V = 0, Z = 0),
– So the instr that will cause branch after this comparison will be
BLT, BLE, and BNE.

49

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