Synchronous Sequential Logic

Part II

Sheis Abolmaali

School of ECE
Semnan University
1
 State Reduction and Assignment
• In the design process of sequential circuits
certain techniques are useful in reducing the
circuit complexity
– state reduction
– state assignment
• State reduction
– Fewer states  fewer number of flip-flops
– m flip-flops  2m states
– Example: m = 5  2m = 32
• If we reduce the number of states to 21 do we
reduce the number of flip-flops?
2
 Example: State Reduction
0/0

a
0/0
1/0 Note that we use
0/0 0/0
letters to designate
b c 0/0 the states for
1/0 the time being
1/0

1/1 0/0
g d e

1/1
1/1
0/0 f

1/1
3
 Example: State Reduction
state a a b c f g f f g a a
input 0 1 0 1 0 1 1 0 0 0 0
output 0 0 0 0 0 1 1 0 0 0

• What is important
– not the states
– but the output values the circuit generates
• Therefore, the problem is to find a circuit
– with fewer number of states,
– but that produces the same output pattern for any
given input pattern, starting with the same initial state
4
State Reduction Technique 1/7 0/0
a
1/0
• Step 1: get a state table b

present state next state Output

x=0 x=1 x=0 x=1
a a b 0 0
b c d 0 0
c c f 0 0
d e f 0 1
e a f 0 1
f g f 0 1
g a f 0 1 5
 State Reduction Technique 2/7
• Step 2: Inspect the state table for equivalent
states
– Equivalent states: Two states,
1. that produce exactly the same output
2. whose next states are identical
– for each input combination

6
 State Reduction Technique 3/7
present state next state Output
x=0 x=1 x=0 x=1
a a b 0 0
b c d 0 0
c c f 0 0
d e f 0 1
e a f 0 1
f g f 0 1
g a f 0 1

• States “e” and “g” are equivalent

• One of them can be removed 7
 State Reduction Technique 4/7
present state next state Output
x=0 x=1 x=0 x=1
a a b 0 0
b c d 0 0
c c f 0 0
d e f 0 1
e a f 0 1
f e f 0 1

• We keep looking for equivalent states

8
 State Reduction Technique 5/7
present state next state Output
x=0 x=1 x=0 x=1
a a b 0 0
b c d 0 0
c c d 0 0
d e d 0 1
e a d 0 1

• We keep looking for equivalent states

9
 State Reduction Technique 6/7

present state next state Output

x=0 x=1 x=0 x=1
a a b 0 0
b b d 0 0
d e d 0 1
e a d 0 1

• We stop when there are no equivalent states

10
 State Reduction Technique 7/7
0/0 present next state Output
state
x=0 x=1 x=0 x=1
a a a b 0 0

0/0 0/0 b b d 0 0
1/0 d e d 0 1
e a d 0 1
0/0 b

1/0
1/0
0/0
d e

1/1 We need two flip-flops

1/1

state a a b b d e d d e a a
input 0 1 0 1 0 1 1 0 0 0 0
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output 0 0 0 0 0 1 1 0 0 0
 State Assignments 1/4
• We have to assign binary values to each state
• If we have m states, then we need a code with
minimum n bits, where n = log2m
• There are different ways of encoding
• Example: Six states: S0, S1, S2, S3, S4, S6

State Binary Gray One-hot

S0 000 000 000001
S1 001 001 000010
S2 010 011 000100
S3 011 010 001000
S4 100 110 010000
S5 101 100 100000 12
13
 State Assignments 2/4
• The circuit complexity depends on the state
encoding (assignment) scheme
• Previous example: binary state encoding

present state next state Output

x=0 x=1 x=0 x=1
(a) 00 00 01 0 0
(b) 01 01 10 0 0
(d) 10 11 10 0 1
(e) 11 00 10 0 1

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 0/0
State Assignments 3/4 a
0/0 0/0
1/0
• Gray encoding
0/0 b
1/0
1/0 0/0
d e
1/1

present state next state Output

x=0 x=1 x=0 x=1
(a) 00 00 01 0 0
(b) 01 01 11 0 0
(d) 11 10 11 0 1
(e) 10 00 11 0 1
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State Assignments 4/4

• One-hot encoding

present state next state Output

x=0 x=1 x=0 x=1
(a) 0001 0001 0010 0 0
(b) 0010 0010 0100 0 0
(d) 0100 1000 0100 0 1
(e) 1000 0001 0100 0 1
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 Designing Sequential Circuits
• Combinational circuits
– can be designed given a truth table
• Sequential circuits
– We need,
• state diagram or
• state table
– Two parts
• flip-flops: number of flip-flops is determined by the
number of states
• combinational part:
– flip-flop input equations
– output equations
17
 Design Process
• Once we know the types and number of flip-
flops, design process is reduced to design
process of combinational circuits
• Therefore, we can apply the techniques of
combinational circuit design
• The design steps
1. Given a verbal description of desired operation,
derive state diagram
2. Reduce the number of states if necessary and
possible
3. State assignment
18
 Design Steps (cont.)
4. Obtain the encoded state table
5. Derive the simplified flip-flop input equations
6. Derive the simplified output equations
7. Draw the logic diagram
• Example: Verbal description
– “we want a (sequential) circuit that detects three or
more consecutive 1’s in a string of bits”
– Input: string of bits of any length
– Output:
• “1” if the circuit detects the pattern in the string
• “0” otherwise

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 Example: State Diagram
• Step 1: Derive the state diagram
0
1

S0 /0 S1/0

0 1 Moore Machine
0

S3/1 S2/0
1

1
20
 Synthesis with D Flip-Flops 1/5
• The number of flip-flops
– Four states
0
– ? flip-flops 1

• State reduction S0 /0 S1/0

0
– not possible in this case
0 1
• State Assignment 0

– Use binary encoding S3/1 S2/0

1
• S0  00
1
• S1  01
• S2  10
• S3  11 21
 Synthesis with D Flip-Flops 2/5
• Step 4: Obtain the state table

0
1

Present state Input Next state Output

S0 /0 S1/0
A B x A B y
0
0 0 0
0 0 1 0 1
0
0 1 0
0 1 1 S3/1 S2/0
1
1 0 0
1 0 1 1
1 1 0
1 1 1

22
 Synthesis with D Flip-Flops 3/5
• Step 5: Choose the flip-flops
– D flip-flops
• Step 6: Derive the simplified flip-flop input
equations
– Boolean expressions for DA and DB
Present state Input Next state Output
A B x A B y Bx
0 0 0 0 0 0 A 00 01 11 10
0 0 1 0 1 0
0 0 0 1 0
0 1 0 0 0 0
0 1 1 1 0 0 1 0 1 1 0
1 0 0 0 0 0
1 0 1 1 1 0
1 1 0 0 0 1
DA = Ax + Bx
1 1 1 1 1 1 23
 Synthesis with D Flip-Flops 3/5
Present state Input Next state Output Bx
A B x A B y
A 00 01 11 10
0 0 0 0 0 0
0 0 1 0 1 0 0 0 1 0 0
0 1 0 0 0 0 1 0 1 1 0
0 1 1 1 0 0
1 0 0 0 0 0
1 0 1 1 1 0
DB = Ax + B’x
1 1 0 0 0 1
1 1 1 1 1 1

Bx
• Step 7: Derive the simplified A 00 01 11 10
output equations 0 0 0 0 0
– Boolean expressions for y. 1 0 0 1 1
y = AB 24
 Synthesis with D Flip-Flops 5/5
• Step 8: Draw the logic diagram
DA = Ax + Bx DB = Ax + B’x y = AB

x DA A
D Q

C
R

y
DB B
D Q

C
R

clock reset 25
 Synthesis with T Flip-Flops 1/4
• Example: 3-bit binary counter with T flip-flops
– 012 ...  7  0  1  2

S0 How many flip-flops?

S1 S7
State assignments:
• S0  000
S2 S6 • S1  001
• S2  010
• ...
S3 S5 • S7  111
S4

State Diagram 26
 Synthesis with T Flip-Flops 2/4

• State Table

present state next state FF inputs

A2 A1 A0 A2 A1 A0 T2 T1 T0
0 0 0 0 0 1
0 0 1 0 1 0
0 1 0 0 1 1
0 1 1 1 0 0
1 0 0 1 0 1
1 0 1 1 1 0
1 1 0 1 1 1
1 1 1 0 0 0 27
 Synthesis with T Flip-Flops 3/4
Present state FF inputs
A2 A1 A0 T2 T1 T0
• Flip-Flop input equations
0 0 0 0 0 1
0 0 1 0 1 1 A1 A0
0 1 0 0 0 1 A2 00 01 11 10
0 1 1 1 1 1
0 0 0 1 0
1 0 0 0 0 1
1 0 1 0 1 1 1 0 0 1 0
1 1 0 0 0 1
1 1 1 1 1 1 T2 = A1A0

A1 A0
A2 00 01 11 10
0 0 1 1 0 T0 = 1
1 0 1 1 0

T1 = A0 28
 Synthesis with T Flip-Flops 4/4
• Circuit logic-1 T0
Q
A0
T

C
T2 = A1A0 R

T1 = A0
T1 A1
T0 = 1 T Q

C
R

T2 A2
T Q

clock C
R

reset 29
 Synthesis with JK Flip-Flops 1/4
J K Q(t+1)
0 0 Q
Q(t+1) = JQ’ + K’Q
0 1 0
1 0 1
• State Table & JK FF Inputs 1 1 Q’

Present state Input next state Flip-flop inputs

A B x A B JA KA JB KB
0 0 0 0 0 0 X 0 X
0 0 1 0 1 0 X 1 X
0 1 0 1 0 1 X X 1
0 1 1 0 1 0 X X 0
1 0 0 1 0 X 0 0 X
1 0 1 1 1 X 0 1 X
1 1 0 1 1 X 0 X 0
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1 1 1 0 0 X 1 X 1
 Synthesis with JK Flip-Flops 2/4
• Optimize the flip-flop input equations
Flip-flop inputs
A B x A(t+1) B(t+1) JA KA JB KB
0 0 0 0 0 0 X 0 X
0 0 1 0 1 0 X 1 X
0 1 0 1 0 1 X X 1
0 1 1 0 1 0 X X 0
1 0 0 1 0 X 0 0 X
1 0 1 1 1 X 0 1 X
1 1 0 1 1 X 0 X 0
1 1 1 0 0 X 1 X 1

Bx Bx
A 00 01 11 10 A 00 01 11 10
0 0 0 0 1 0 0 1 X X
1 X X X X 1 0 1 X X
JA = Bx’ JB = x
Synthesis with JK Flip-Flops 3/4
Flip-flop inputs
A B x A(t+1) B(t+1) JA KA JB KB
0 0 0 0 0 0 X 0 X
0 0 1 0 1 0 X 1 X
0 1 0 1 0 1 X X 1
0 1 1 0 1 0 X X 0
1 0 0 1 0 X 0 0 X
1 0 1 1 1 X 0 1 X
1 1 0 1 1 X 0 X 0
1 1 1 0 0 X 1 X 1

Bx Bx
A 00 01 11 10 A 00 01 11 10
0 X X X X 0 X X 0 1
1 0 0 1 0 1 X X 1 0
KA = Bx KB = (A  x)’ 32
 Synthesis with JK Flip-Flops 4/4
• Logic diagram
JA = Bx’ KA = Bx JB = x KB = (A  x)’

x J Q A
C
K

J
D Q B
clk C
C
K

33
 Unused States
S0
Modulo-5 counter
S1 S4

S2 S3

Present State Next State

A B C A B C
0 0 0 0 0 1
0 0 1 0 1 0
0 1 0 0 1 1
0 1 1 1 0 0
1 0 0 0 0 0 34
 Example: Unused States 1/4
Present State Next State
BC
A B C A B C
A 00 01 11 10
0 0 0 0 0 1
0
0 0 1 0 1 0
1
0 1 0 0 1 1
0 1 1 1 0 0 A(t+1) =
1 0 0 0 0 0

BC BC
A 00 01 11 10 A 00 01 11 10
0 0
1 1

B(t+1) = C(t+1) =
35
 Example: Unused States 2/4

Present State Next State 111

A B C A B C
0 0 0 0 0 1 000
0 0 1 0 1 0
0 1 0 0 1 1 001 100
0 1 1 1 0 0
1 0 0 0 0 0
010 011
1 1 0 0 1 0
1 1 1 1 0 0

A(t+1) = BC 101 110

B(t+1) = B  C
C(t+1) = A’C’ 36
 Example: Unused States 3/4
• Not using don’t care conditions
BC
Present State Next State A 00 01 11 10
A B C A B C
0 0 0 1 0
0 0 0 0 0 1
1 0 0 0 0
0 0 1 0 1 0
0 1 0 0 1 1 A(t+1) = A’BC
0 1 1 1 0 0
1 0 0 0 0 0
BC BC
A 00 01 11 10 A 00 01 11 10
0 0 1 0 1 0 1 0 0 1
1 0 0 0 0 1 0 0 0 0

B(t+1) = A’B’C + A’BC’ C(t+1) = A’C’

37
= A’(B  C)
 Example: Unused States 4/4
Present State Next State
A B C A B C 101 110 111
0 0 0 0 0 1
0 0 1 0 1 0
0 1 0 0 1 1 000
0 1 1 1 0 0
1 0 0 0 0 0
001 100

010 011

A(t+1) = A’BC
B(t+1) = A’(B  C)
C(t+1) = A’C’
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 Sequential Circuit Timing 1/3
• It is important to analyze the timing behavior of
a sequential circuit
– Ultimate goal is to determine the maximum clock
frequency

clk

ts th

tp, FF 39
 Sequential Circuit Timing 2/3
tp

clk

tp,FF tp,COMB ts

Combinational Circuit tp = tp,FF + tp,COMB + ts

inputs outputs
tp,COMB

current
state Flip-flop
Flip-flops inputs
Q D
tp,FF
ts
clock C 40
 Sequential Circuit Timing 2/3
tp

clk

tp,FF tp,COMB ts

Combinational Circuit tp,FF + tp,COMB >> th

inputs outputs
tp,COMB

current
state Flip-flop
Flip-flops inputs
Q D
tp,FF

clock C 41
 Sequential Circuit Timing 3/3
• Minimum clock period (or maximum clock
frequency)
tp

clk

tp,FF tp,COMB ts

tp

clk

tp,FF tp,COMB ts
42
 Example: Sequential Circuit Timing

A D Q B
C
B’
clk

y
x
tp,NOT = 0.5 ns
Find the longest path delay from
tp,XOR = 2.0 ns external input to the output
tp,FF = 2.0 ns
tp,XOR + tp,XOR = 2.0 + 2.0 = 4.0 ns
tp,AND = ts = 1.0 ns
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th = 0.25 ns
 Example: Sequential Circuit Timing

A D Q B
C
B’
clk

y
x
tp,NOT = 0.5 ns

tp,XOR = 2.0 ns
Find the longest path delay in the
circuit from external input to
tp,FF = 2.0 ns positive clock edge
tp,AND = ts = 1.0 ns tp,XOR + tp,NOT = 2.0 + 0.5 = 2.5 ns
th = 0.25 ns 44
 Example: Sequential Circuit Timing

A D Q B
C
B’
clk

y
x
tp,NOT = 0.5 ns

tp,XOR = 2.0 ns Find the longest path delay from positive

clock edge to output
tp,FF = 2.0 ns
tp,AND = ts = 1.0 ns tp,FF + tp,XOR = 2.0 + 2.0 = 4.0 ns
th = 0.25 ns 45
 Example: Sequential Circuit Timing

A D Q B
C
B’
clk

y
x
tp,NOT = 0.5 ns

tp,XOR = 2.0 ns Find the longest path delay from positive

clock edge to positive clock edge
tp,FF = 2.0 ns
tp,AND = ts = 1.0 ns
tp,FF + tp,AND + tp,XOR + tp,NOT
= 2.0 + 1.0 + 2.0 + 0.5 = 5.5 ns
th = 0.25 ns 46
 Example: Sequential Circuit Timing

A D Q B
C
B’
clk

y
x
tp,NOT = 0.5 ns Determine the maximum frequency of
operation of the circuit in megahertz
tp,XOR = 2.0 ns
tp = tp,FF + tp,AND + tp,XOR + tp,NOT + ts
tp,FF = 2.0 ns
= 2.0 + 1.0 + 2.0 + 0.5 + 1.0 = 6.5 ns
tp,AND = ts = 1.0 ns
fmax = 1/tp = 1/(6.5×10-9)  154 MHz
th = 0.25 ns 47
 Example
Binary encoding

S0 S3
D Q x1
C

S1 S2

tp,XOR = 2.0 ns D Q x0
C
tp,FF = 2.0 ns x 0’
ts = 1.0 ns

tp = tp,FF + tp,XOR + ts = 2.0 + 2.0 + 1.0 = 5.0 ns

fmax = 1/tp = 1/(5.0×10-9)  200 MHz 48

 Example: One-Hot-Encoding
S0  0001
S1  0010 D Q y0
S2  0100 C
S3  1000

tp,FF = 2.0 ns D Q y1
C
ts = 1.0 ns

D Q y2
tp = tp,FF + ts = 2.0 + 1.0 = 3.0 ns
C

fmax = 1/tp = 1/(3.0×10-9)  333 MHz

D Q y3
C

49