Combinational Logic

Sheis Abolmaali

School of ECE
Semnan University
1
 Classification
1. Combinational
– no memory
– outputs depends on only the present inputs
– expressed by Boolean functions
2. Sequential
– storage elements + logic gates
– the content of the storage elements define the state
of the circuit
– outputs are functions of both input and current state
– state is a function of previous inputs
– outputs not only depends the present inputs but also
the past inputs
2
 Combinational Circuits

n binary Combinational m binary

circuit
inputs (logic gates)
outputs

– n input bits  2n possible binary input combinations

– For each possible input combination, there is one
possible output value
• truth table
• Boolean functions (with n input variables)
– Examples: adders, subtractors, comparators,
decoders, encoders, and multiplexers.
3
 Analysis & Design of
Combinational Logic
• Analysis: to find out the function that a given
circuit implements
– We are given a logic circuit and
– we are expected to find out
1. Boolean function(s)
2. truth table
3. A possible explanation of the circuit operation
(i.e. what it does)
• Firstly, make sure that the given circuit is,
indeed, combinational.
4
 Analysis of Combinational Logic
– Verifying the circuit is combinational
• No memory elements
• No feedback paths (connections)
• Secondly, obtain a Boolean function for each
output or the truth table
• Lastly, interpret the operation of the circuit
from the derived Boolean functions or truth
table
– What is it the circuit doing?
– Addition, subtraction, multiplication, etc.

5
 Obtaining Boolean Function
Example
a T1
b F1
c

a T2
b T4
c

a T3
b
a F2
c

b
c
6
 Example: Obtaining Boolean Function
• Boolean expressions for named wires
– T1 = abc
– T2 = a + b + c
– F2 = ab + ac + bc
– T3 = F2’ = (ab + ac + bc)’
– T4 = T3T2 = (ab + ac + bc)’ (a + b + c)
– F1 = T1 + T4
= abc + (ab + ac + bc)’ (a + b + c)
= abc + ((a’ + b’)(a’ + c’)(b’ + c’)) (a + b + c)
= abc + ((a’ + a’c’ + a’b’ + b’c’)(b’ + c’)) (a + b + c)
= abc + (a’b’ + a’c’ + a’b’c’ + b’c’) (a + b + c)

7
 Example: Obtaining Boolean Function
• Boolean expressions for outputs
– F2 = ab + ac + bc
– F1 = abc + (a’b’ + a’c’ + b’c’) (a + b + c)
– F1 = abc + a’b’c + a’bc’ + ab’c’
– F1 = a(bc + b’c’) + a’(b’c + bc’)
– F1 = a(b  c)’ + a’(b  c)
– F1 =

8
Example: Obtaining Truth Table
F1 =
F2 = ab + ac + bc carry sum

a b c T1 T2 T3 T4 F2 F1
0 0 0 0 0 1 0 0
0 0 1 0 1 1 1 1
0 1 0 0 1 1 1 1
0 1 1 0 1 0 0 0
1 0 0 0 1 1 1 1
1 0 1 0 1 0 0 0
1 1 0 0 1 0 0 0
1 1 1 1 1 0 0 1

This is what we call full-adder (FA) 9

 Design of Combinational Logic
• Design Procedure:
– We start with the verbal specification about what
the resulting circuit will do for us (i.e. which function
it will implement)
• Specifications are often verbal, and very likely
incomplete and ambiguous (if not faulty)
• Wrong interpretations can result in incorrect
circuit
– We are expected to find
1. firstly, Boolean function(s) (or truth table) to
realize the desired functionality
2. Logic circuit implementing the Boolean function(s)
(or the truth table)
10
 Possible Design Steps

1. Find out the number of inputs and outputs

2. Derive the truth table that defines the
required relationship between inputs and
outputs
3. Obtain a simplified Boolean function for each
output
4. Draw the logic diagram (enter your design into
CAD)
5. Verify the correctness of the design

11
 Design Constraints
• From the truth table, we can obtain a variety of
simplified expressions
• Question: which one to choose?
• The design constraints may help in the selection
process
• Constraints:
– number of gates
– propagation time of the signal all the way from the
inputs to the outputs
– number of inputs to a gate
– number of interconnections
– power consumption
– driving capability of each gate 12
 Example: Design Process
• BCD-to-2421 Converter
• Verbal specification:
– Given a BCD digit (i.e. {0, 1, …, 9}), the circuit computes
2421 code equivalent of the decimal number
• Step 1: how many inputs and how many outputs?
– four inputs and four outputs
• Step 2:
– Obtain the truth table
– 0000  0000
– 1001  1111
– etc.
13
 BCD-to-2421 Converter
• Truth Table
Inputs Outputs
A B C D x y z t
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 0
0 0 1 1 0 0 1 1
0 1 0 0 0 1 0 0
0 1 0 1 1 0 1 1
0 1 1 0 1 1 0 0
0 1 1 1 1 1 0 1
1 0 0 0 1 1 1 0
1 0 0 1 1 1 1 1
14
 BCD-to-2421 Converter
• Step 3: Obtain simplified Boolean expression
for each output A B C D x

• Output x: 0
0
0
0
0
0
0
1
0
0
0 0 1 0 0

CD 0 0 1 1 0
0 1 0 0 0
AB 00 01 11 10
0 1 0 1 1
00 0 0 0 0 0 1 1 0 1
0 1 1 1 1
01 0 1 1 1 1 0 0 0 1
1 0 0 0 1
11
The rest X

10 1 1

x = BD + BC + A 15
 Boolean Expressions for Outputs
CD • Output y:
AB 00 01 11 10
00 A B C D y z
0 0 0 0
0 0 0 0 0 0
01 1 0 1 1 0 0 0 1 0 0

11 0 0 1 0 0 1
X X X X
0 0 1 1 0 1
10 1 1 X X 0 1 0 0 1 0
0 1 0 1 0 1

CD • Output z: 0 1 1 0 1 0
0 1 1 1 1 0
AB 00 01 11 10
1 0 0 0 1 1
00 0 0 1 1 1 0 0 0 1 1
The rest X X
01 0 1 0 0
11 X X X X
10 1 1 X X 16
 Boolean Expressions for Outputs
• Output t:
CD
A B C D T
AB 00 01 11 10 0 0 0 0 0
00 0 1 1 0 0 0 0 1 1
0 0 1 0 0
01 0 1 1 0 t=D 0 0 1 1 1
11 X X X X 0 1 0 0 0
0 1 0 1 1
10 0 1 X X 0 1 1 0 0
0 1 1 1 1
• Step 4: Draw the logic diagram 1 0 0 0 0
1 0 0 0 1
x = BC + BD + A The rest X

y = A + BD’ + BC
z = A + B’C + BC’D
17
 Example: Logic Diagram
A
B
C x = BC + BD + A
D

y = A + BD’ + BC

z = A + B’C + BC’D

t=D 18
 Example: Verification
• Step 5: Check the functional correctness of the
logic circuit
• Apply all possible input combinations
• And check if the circuit generates the correct
outputs for each input combinations
• For large circuits with many input combinations,
this may not be feasible.
• Statistical techniques may be used to verify the
correctness of large circuits with many input
combinations
19
 Binary Adder/Subtractor
• (Arithmetic) Addition of two binary digits
– 0 + 0 = 0, 0 + 1 = 1, 1 + 0 = 1, and 1 + 1 = 10
– The result has two components
• the sum (S)
• the carry (C)
• (Arithmetic) Addition of three binary digits
0 + 0 + 0 = 0 0
0 + 0 + 1 = 0 1
0 + 1 + 0 = 0 1
0 + 1 + 1 = 1 0
1 + 0 + 0 = 0 1
1 + 0 + 1 = 1 0
1 + 1 + 0 = 1 0
20
1 + 1 + 1 = 1 1
 Half Adder
• Truth table
x y C S
0 0 0 0 S = x’y + xy’ = x  y
0 1 0 1
1 0 0 1
C = xy
1 1 1 0

x
S
y

C
HA
21
 Full Adder 1/2
• A circuit that performs the arithmetic sum of
three bits
– Three inputs
– the range of output is [0, 3]
– Two binary outputs

x y z C S
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
22
1 1 1 1 1
 Full Adder 2/2
• Karnaugh Maps

yz
yz
x 00 01 11 10
x 00 01 11 10
0 0 1 0 1 0 0 0 1 0
1 1 0 1 0 1 0 1 1 1

S = xy’z’ + x’y’z + xyz + x’yz’ C = xy + xz + yz

= ...
Two level implementation
= ...
1st level: three AND gates
=xyz 2nd level: One OR gate
23
Full Adder: Hierarchical Realization
• Sum
– S=xyz
• Carry
– C = xy + xz + yz
= (x + y) z + xy
= (x  y) z + xy
• This allows us to implement a full-adder using two
half adders.
xyz=S
x S S

HA HA
y C C C

z
24
 Full Adder Using Half Adders

x HA
HA
y S

C
z

25
 Integer Addition 1/2
• Binary adder:
– A digital circuit that produces the arithmetic sum of
two binary numbers
– A = (an-1, an-2, …, a1, a0)
– B = (bn-1, bn-2, …, b1, b0)
• A simple case: 4-bit binary adder
a3 b3 a2 b2 a1 b1 a0 b0

x y x y x y x y
C4 C3 C2 C1
C FA z C FA z C FA z C HA
S S S S

S3 S2 S1 S0
26
 Integer Addition 2/2

a3 b3 a2 b2 a1 b1 a0 b0

x y x y x y x y
C4 C3 C2 C1 C0=0
C FA z C FA z C FA z C FA z

S S S S

S3 S2 S1 S0

Ripple-carry adder

27
 Hierarchical Design Methodology
• The design methodology we used to build carry-
ripple adder is what is referred as hierarchical
design.
• In classical design, we have:
– 9 inputs including C0.
– 5 outputs
– Truth tables with 29 = 512 entries
– We have to optimize five Boolean functions with 9
variables each.
• Hierarchical design
– we divide our design into smaller functional blocks
– connect functional units to produce the big
functionality
28
 Subtractor
• Recall how we do subtraction (2’s complement)
– X – Y = X + (2n – Y) = X + ~Y + 1
x3 y3 x2 y2 x1 y1 x0 y0
logic-1

a3 b3 a2 b2 a1 b1 a0 b0

C4 4-bit adder circuit C0

S3 S2 S1 S0

C4 S3 S2 S1 S0 29
 Overflow
• How to detect overflows:
– two n-bit numbers
– we add them, and result may be an (n+1)-bit number 
overflow.
– Unsigned numbers:
• easy
• check the carryout.
– Signed numbers
• more complicated
• overflow occurs in addition, when the operands are
of the same sign

30
 Examples: Overflows
• Example 1: 8-bit signed numbers

…00 0 1 0 0 0 1 0 0 68
…00 0 1 0 1 1 0 1 1 91
…00 1 0 0 1 1 1 1 1 159

• Example 2: 8-bit signed numbers

…11 1 0 1 1 1 1 0 0 -68
…11 1 0 1 0 0 1 0 1 -91
…11 0 1 1 0 0 0 0 1 -159

31
 How to Detect Overflows:
• First Method
1. If both operands are positive and the MSB of the
result is 1.
2. If both operands are negative and the MSB of the
result is 0.
an-1 bn-1 Sn-1 V
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 0
32
Detecting Overflows: First Method

bn-1Sn-1
an-1 00 01 11 10
0 0 1 0 0
1 0 0 0 1

• V = an-1’ bn-1’ Sn-1 + an-1 bn-1 Sn-1’

• Can we do it better?

33
 Detecting Overflows
• Second method:
– Remember we have other variables when adding:
• Carries
…00 0 1 0 0 0 1 0 0 A
…00 0 1 0 1 1 0 1 1 B
0 C Look at C7
…00 1 0 0 1 1 1 1 1 S and C8 in
both cases
…11 1 0 1 1 1 1 0 0 A
…11 1 0 1 0 0 1 0 1 B
0 C
…11 0 1 1 0 0 0 0 1 S
34
 Detecting Overflows: Second Method
• Observations
– Case 1: V = 1 when C7 = 1 and C8 = 0
– Case 2: V = 1 when C7 = 0 and C8 = 1
– V = C7  C8 = 1
– Think about whether this could happen when the
operands have different signs.
• C7 = C8
• Overflow detection logic
– Which one is simpler?
– V = C7  C8
– V = a7’ b7’ S7 + a7 b7 S7’

35
 Carry Propagation
• What is the total propagation time of 4-bit
ripple-carry adder?
– FA: propagation time of a single full adder.
– We have four full adders connected in cascaded
fashion
– Total propagation time: 4FA.

ai Pi
bi Si
Gi
Ci+1
Ci

4FA  8XOR 36
 Faster Adders
• The carry propagation technique is a limiting
factor in the speed with which two numbers are
added.
• Two alternatives
1. use faster gates with reduced delays
2. Increase the circuit complexity (i.e. put more gates)
in such a way that the carry delay time is reduced.
• An example for the latter type of solution is
carry lookahead adders
– Two binary variables:
1. Pi = ai  bi – carry propagate
2. Gi = aibi – carry generate 37
 Carry Lookahead Adders
• Sum and carry can be expressed in terms of Pi
and Gi:
– Pi = ai  bi; Gi = aibi
– S i = Pi  C i
– Ci+1 = Gi + PiCi
• Why the names (carry propagate and generate)?
– If Gi = 1 (both ai = bi = 1), then a “new” carry is
generated
– If Pi = 1 (either ai = 1 or bi = 1), then a carry coming
from the previous lower bit position is propagated to
the next higher bit position
38
 Generating Pi and Gi Signals
• Example: 4-bit operands
a3
b3 P3

G3
a2
b2 P2

G2
a1
b1 P1

G1
a0
b0 P0

G0
39
 4-bit Carry Lookahead Adder
• We can use the carry propagate and carry
generate signals to compute carry bits used in
addition operation
– C0 = input
– C1 = G0 + P0C0
– C2 = G1 + P1C1
= G1 + P1(G0 + P0C0) = G1 + P1G0 + P1P0C0
– C3 = G2 + P2C2 = G2 + P2(G1 + P1G0 + P1P0C0)
= G2 + P2G1 + P2P1G0 + P2P1P0C0

– C4 = G3 + P3G2 + P3P2G1 + P3P2P1G0 + P3P2P1P0C0

40
 4-bit Carry Lookahead Circuit 1/3
C1 = G0 + P0C0
C2 = G1 + P1G0 + P1P0C0
C3 = G2 + P2G1 + P2P1G0 + P2P1P0C0

C3

P2
G2

P1
C2
G1

P0 C1
G0
41
C0
 4-bit Carry Lookahead Circuit 2/3
• All three carries (C1, C2, C3) can be realized as
two-level implementation (i.e. AND-OR)
• C3 does not have to wait for C2 and C1 to
propagate
• C3 has its own circuit
• The propagations happen concurrently
• Certain parts are repeated.

42
 4-bit Carry Lookahead Circuit 3/3

• Two levels of logic

43
 4-bit Carry Lookahead Adder
a3
b3 P3 C4 C4
G3
P3
a2 C3 S3
b2 P2
G2 P2
S2
Carry C2
a1 Lookahead
b1 P1
circuit
G2 P1
C1 S1
a0
b0 P0
G0 P0
C0 S0
C0 C0
44
 Propagation Time of
P2
P1 Carry Lookahead Adders
P0
C0
P2
P1
G0 C3
P2
G1 XOR = 2AND = 2OR
G2
P2
P1
P0
a1
C0
b1 C3
P2
P1
S3
G0
P2 P3
G1
G2 45
 Generating C4
C0 Delay 3.5 XOR
P0
P1
Area: 14 gates
P2
P3

G0
P1
P2
P3

G1
P2

P3

G2
P3
C4
G3

46
 Summary
• Half adder  HA
• Full adder  FA
– critical path delay
– time complexity: 2XOR (assume XOR = 2AND = 2OR)
• 4-bit carry-ripple adder
– 4 FAs in serial
• carry propagation
– time complexity: 8XOR
• Faster Adder
– Separate carry generation circuits (more complex)
– time complexity:  4XOR
47
 Hybrid Approach for 16-bit Adder

a15 a12 b15 b12 a11 a8 b11 b8 a7 a4 b7 b4 a3 a0 b3 b0

… … … … … … … …

c16 c12 c8 c4
4-bit CLA 4-bit CLA 4-bit CLA 4-bit CLA

… … … …
s15 s12 s11 s8 s7 s4 s3 s0

48
 Binary Multipliers
• Two-bit multiplier
y1 y0 Y
× x1 x0 X
x0 y1 x0 y0
+ x1 y1 x1 y0
z3 z2 z1 z0 Z
y1 y0
x0
y1 y0
x1

HA HA

z3 z2 z1 z0 49
 (3x4)-bit Multiplier: Method

y3 y2 y1 y0 Y

× x2 x1 x0 X
x0 y3 x0 y2 x0 y1 x0 y0

x1 y3 x1 y2 x1 y1 x1 y0

+ x2 y3 x2 y2 x2 y1 x2 y0

z6 z5 z4 z3 z2 z1 z0

50
 (3x4)-bit Multiplier: Method

y3 y2 y1 y0 Y

× x2 x1 x0 X
x0 y3 x0 y2 x0 y1 x0 y0

x1 y3 x1 y2 x1 y1 x1 y0

t4 t3 t2 t1 t0

+ x2 y3 x2 y2 x2 y1 x2 y0

z6 z5 z4 z3 z2 z1 z0

51
 4-bit Multiplier: Circuit
y3 y2 y1 y0
x0
y3 y2 y1 y0
x1

4-bit Adder

y3 y2 y1 y0
x2

4-bit Adder

z6 z5 z4 z3 z2 z1 z0 52
 mxn-bit Multipliers
• Generalization:
• multiplier: m-bit integer
• multiplicand: n-bit integers
• mn AND gates
• (m-1) adders
– each adder is n-bit

53
 Magnitude Comparator
• Comparison of two integers: A and B.
– A > B  (1, 0, 0) = (x, y, z)
– A = B  (0, 1, 0) = (x, y, z)
– A < B  (0, 0, 1) = (x, y, z)
• Example: 4-bit magnitude comparator
– A = (a3, a2, a1, a0) and B = (b3, b2, b1, b0)
1. (A = B) case
• they are equal if and only if ai = bi 0i3
• ti = (ai  bi)’ 0i3
• y = (A=B) = t3 t2 t1 t0

54
 4-bit Magnitude Comparator
2. (A > B) and (A < B) cases
– We compare the most significant bits of A and B
first.
• if (a3 = 1 and b3 = 0)  A > B
• else if (a3 = 0 and b3 = 1)  A < B
• else (i.e. a3 = b3) compare a2 and b2.
y = (A=B) = t3 t2 t1 t0

x = (A>B) = a3 b3’ + t3 a2 b2’ + t3t2 a1 b1’ + t3t2t1 a0 b0’

z = (A<B) = a3’ b3 + t3 a2’ b2 + t3t2 a1’ b1 + t3t2t1 a0’ b0

55
4-bit Magnitude Comparator: Circuit
t3

t2

t1

t0

56
 Decoders
• A binary code of n bits
– capable of representing 2n distinct elements of coded
information
– A decoder is a combinational circuit that converts
binary information from n binary inputs to a maximum
of 2n unique output lines
x y d0 d1 d2 d3
d0 0 0 1 0 0 0
x
2x4 d1 0 1 0 1 0 0
decoder d2 1 0 0 0 1 0
y
d3 1 1 0 0 0 1

• d0 = • d2 =
• d1 = • d3 = 57
 Decoder with Enable Input

d0
x
2x4 d1
decoder d2
y d3

e
e x y d0 d1 d2 d3
0 X X 0 0 0 0
1 0 0 1 0 0 0
1 0 1 0 1 0 0
1 1 0 0 0 1 0
1 1 1 0 0 0 1
58
 2-to-4 Decoder
• Some decoders are constructed with NAND
gates.
– Thus, active output will be logic-0
– They also include an “enable” input to control the
circuit operation

e x y d0 d1 d2 d3
1 X X 1 1 1 1 • d0 = e + x + y
0 0 0 0 1 1 1 • d1 = e + x + y’
0 0 1 1 0 1 1 • d2 = e + x’ + y
0 1 0 1 1 0 1 • d3 = e + x’ + y’
0 1 1 1 1 1 0

59
2-to-4-Line Decoder with Enable
d0 = e + x + y =
d1 = e + x + y’ =
d2 = e + x’ + y =
d3 = e + x’ + y’ =

x d0

d1

y d2

d3

e 60
 Demultiplexer
• A demultiplexer is a combinational circuit
– it receives information from a single line and directs it
one of 2n output lines
– It has n selection lines as to which output will get the
input

d0 d0
x d1
2x4 d1 e
decoder d2 d2
y d3 d3
x, y

e d0 = e when x = 0 and y = 0
d1 = e when x = 0 and y = 1
d2 = e when x = 1 and y = 0
d3 = e when x = 1 and y = 1 61
 Combining Decoders
d0
y 2x4 d1 x y z active output
decoder d2
z e 0 0 0
d3
x 0 0 1
d4 0 1 0
2x4 d5
decoder d6 0 1 1
e d7 1 0 0
1 0 1
1 1 0
1 1 1

62
 Decoder as a Building Block
• A decoder provides the 2n minterms of n input
variable

d0 = x’y’
x
2x4 d1 = x’y
decoder d2 = xy’
y d3 = xy

• We can use a decoder and OR gates to realize

any Boolean function expressed as sum of
minterms
– Any circuit with n inputs and m outputs can be realized
using an n-to-2n decoder and ? OR gates.
63
Example: Decoder as a Building Block
• Full adder
– C = xy + xz + yz = (3, 5, 6, 7)
– S = x  y  z = (1, 2, 4, 7)

0
x 1
2 C
3x8 3
y decoder 4
5
6
S
z
7

64
 Encoders
• An encoder is a combinational circuit that
performs the inverse operation of a decoder
– number of inputs: 2n
– number of outputs: n
– the output lines generate the binary code
corresponding to the input value
• Example: n = 2

d0 d1 d2 d3 x y
1 0 0 0 0 0
0 1 0 0 0 1
0 0 1 0 1 0
0 0 0 1 1 1
65
 Priority Encoder
• Problem with a regular encoder:
– only one input can be active at any given time
– the output is undefined for the case when more than
one input is active simultaneously.
• Priority encoder:
– there is a priority among the inputs
d0 d1 d2 d3 x y V
0 0 0 0 X X 0
1 0 0 0 0 0 1
X 1 0 0 0 1 1
X X 1 0 1 0 1
X X X 1 1 1 1
66
 4-bit Priority Encoder
• In the truth table
– X for input variables represents both 0 and 1.
– Good for condensing the truth table
– Example: X100  (0100, 1100)
• This means d1 has priority over d0
• d3 has the highest priority
• d2 has the next
• d0 has the lowest priority

– V=?

67
 Maps for 4-bit Priority Encoder
d2d3
d0d1 00 01 11 10
00 X 1 1 1
01 0 1 1 1
11 0 1 1 1
10 0 1 1 1 –x=
d2d3
d0d1 00 01 11 10
00 X 1 1 0
01 1 1 1 0
11 1 1 1 0
–y=
10 0 1 1 0
68
 4-bit Priority Encoder: Circuit
– x = d2 + d3
– y = d1d2’ + d3
– V = d0 + d1 + d2 + d3

d3 y

d2

d1

V
d0
69
 Multiplexers
• A combinational circuit
– It selects binary information from one of the many
input lines and directs it to a single output line.
– Many inputs – m
– One output line
– selection lines n  n = ?
• Example: 2-to-1-line multiplexer
– 2 input lines I0, I1
S Y
– 1 output line Y
– 1 select line S 0 I0
1 I1
Y=? Function Table
70
 2-to-1-Line Multiplexer
Y=?
I0
S
Y

I1

• Special Symbol

I0 0
MUX Y
I1 1

S
71
 4-to-1-Line Multiplexer
• 4 input lines: I0, I1, I2, I3
• 1 output line: Y
• 2 select lines: S1, S0.

S1 S0 Y
Y=?
0 0 ?
0 1 ?
Interpretation:
1 0 ?
• In case S1 = 0 and S0 = 0, Y selects I0
1 1 ?
• In case S1 = 0 and S0 = 1, Y selects I1
• In case S1 = 1 and S0 = 0, Y selects I2
• In case S1 = 1 and S0 = 1, Y selects I3
72
 4-to-1-Line Multiplexer: Circuit
I0

I1 I0 0
I1 1 Y
MUX Y
I2 I2 2

I3 3

I3 S1 S 0

Y = S1’S0’I0 + S1’S0I1 + S1S0’I2 + S1S0I3

S1
73
S0
 Multiplexer with Enable Input
• To select a certain building block we use enable
inputs

E
E S Y
A 0 1 XX
B 1 0 00
MUX Y
C 2
0 01
0 10
D 3
0 11
S1 S0

74
 Multiple-Bit Selection Logic 1/2
• A multiplexer is also referred as a “data
selector”
• A multiple-bit selection logic selects a group of
bits
E
2 A=
A 0
2
MUX Y B=
2
B 1
1
Y=

75
Multiple-bit Selection Logic 2/2

E S Y
1 X all 0’s
0 0 A
E 0 1 B
2
Aa01 00
2
MUX
MUX yY10
2
Bb01 11
1
S
S

76
 Design with Multiplexers 1/2
• Reminder: design with decoders
• Half adder
– C = xy = 
– S = x  y = x’y + xy’ = 

0
x
2x4 1
S
decoder 2
y 3 C

• A closer look will reveal that a multiplexer is

nothing but a decoder with OR gates
77
 Design with Multiplexers 2/2
• 4-to-1-line multiplexer

I0 0 • S1 x
I1 1 • S0 y
MUX Y
I2 2 • S1’S0’ = x’y’,
I3 3 • S1’S0 = x’y,
• S1S0’ = xy’,
S1 S0
• S1S0 = xy
• Y = S1’S0’ I0 + S1’S0 I1 + S1S0’ I2 + S1S0 I3.
• Y = x’y’ I0 + x’y I1 + xy’ I2 + xyI3
• Y= 78
 Example: Design with Multiplexers
• Example: S = (1, 2)

= I0 0
= I1 1
MUX Y = xy’ + x’y
= I2 2

= I3 3

S1 S0
x y

79
Design with Multiplexers Efficiently
• More efficient way to implement an n-variable
Boolean function
1. Use a multiplexer with n-1 selection inputs
2. First (n-1) variables are connected to the selection
inputs
3. The remaining variable is connected to data inputs
• Example: Y = (1, 2)

? = I0 0
MUX Y = S’ I0 + S I1
? = I1 1 Y = x’I0 + x I1
80
x
 Example: Design with Multiplexers
• F(x, y, z) = (1, 2, 6, 7)
– F = x’y’z + x’yz’ + xyz’ + xyz
– Y = S1’S0’ I0 + S1’S0 I1 + S1S0’ I2 + S1S0 I3
– I0 = , I1 = , I2 = , I3 =
x y z F
0 0 0 0 F=
0 0 1 1
0 1 0 1
F=
0 1 1 0
1 0 0 0
F=
1 0 1 0
1 1 0 1
F=
1 1 1 1 81
Example: Design with Multiplexers
F = x’y’z + x’yz’ + xyz’ + xyz
F = z when x = 0 and y = 0
F = z’ when x = 0 and y = 1
F = 0 when x = 1 and y = 0
F = 1 when x = 1 and y = 1

0
1
MUX F = x’y’z + x’yz’ + xy
2

x y
82
 Design with Multiplexers
• General procedure for n-variable Boolean
function
– F(x1, x2, ..., xn)
1. The Boolean function is expressed in a truth table
2. The first (n-1) variables are applied to the selection
inputs of the multiplexer (x1, x2, ..., xn-1)
3. For each combination of these (n-1) variables,
evaluate the value of the output as a function of the
last variable, xn.
• 0, 1, xn, xn’
4. These values are applied to the data inputs in the
proper order.
83
Combining Multiplexers
0
1
MUX
2

3 0
MUX
x y
1
0
z
1
MUX
2

84
x y
 Three-State Buffers
• A different type of logic element
– Instead of two states (i.e. 0, 1), it exhibits three
states (0, 1, Z)
– Z (Hi-Z) is called high-impedance
– When in Hi-Z state the circuit behaves like an open
circuit (the output appears to be disconnected, and
the circuit has no logic significance)

input A Y=A if C =1
Y = Hi-Z if C = 0
control C
input

85
 3-State Buffers
• Remember that we cannot connect the outputs of
other logic gates.
• We can connect the outputs of three-state
buffers
– provided that no two three-state buffers drive the
same wire to opposite 0 and 1 values at the same time.

C A Y

0 X Hi-Z

1 0 0

1 1 1
86
Multiplexing with 3-State Buffers
TA
A Y

TB
B

S S A B TA TB Y
0 0 X 0 Z 0
0 1 X 1 Z 1

It is, in fact, a 1 X 0 Z 0 0
2-to-1-line MUX 1 X 1 Z 1 1
87
 Two Active Outputs - 1
TA
A Y C1 C0 A B Y
C0 0 0 X X Z
TB 0 1 0 X 0
B
0 1 1 X 1
C1
1 0 X 0 0
What will happen 1 0 X 1 1
if C1 = C0 = 1? 1 1 0 0 0
1 1 1 1 1
1 1 0 1
1 1 1 0
88
 Design Principle with 3-State Buffers
• Designer must be sure that only one control input
must be active at a time.
– Otherwise the circuit may be destroyed by the large
amount of current flowing from the buffer output at
logic-1 to the buffer output at logic-0.

x w

y
S1
2x4
decoder z
S0
t
E
89
 Busses with 3-State Buffers
• There are important uses of three-state buffers

CPU Memory

I/O Device

90