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Lab 5

Lab5

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12A115 Hưng
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12 views15 pages

Lab 5

Lab5

Uploaded by

12A115 Hưng
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Lab 5: Design sequential circuit

Assignments
Continuous assignment:
➢ Continuous assignments continuously monitor the RHS (right – hand side) and update the LHS (left –
hand side) immediately when the RHS change, does not introduce any timing delays.
➢ Multiple continuous assignment executes concurrently, order of statements is not important.
➢ Used outside always statement to design simple combinational circuit.
➢ Syntax: assign a = b;

Blocking assignment:
➢ Cause the RHS expression to be evaluated immediately, and the LHS variable is updated before
moving to the next statement.
➢ Multiple blocking assignments are executed sequentially in the order they appear in the code, order
of statements is important.
➢ Used inside always statement to design combinational circuit.
➢ Syntax: a = b;
Non – blocking assignment:
➢ Updating for the variables on the LHS occur at the end of current time step, typically on a clock edge.
➢ Multiple non-blocking assignments executes concurrently, order of statements is not important.
➢ Used inside always statement to design more complex sequential circuit.
➢ Syntax: a <= b;
Compare between types of assignments
Continous Blocking Non-blocking
assignment assignment assignment
Update LHS to RHS Immediately Immediately At the end of
current time step,
typically on a clock
edge
Order of execution Concurrently In order Concurrently
statements
Using to design Simple Combinational Sequential circuit
combinational circuit
circuit
Inside or outside Outside Inside Inside
always

Syntax assign a = b a=b a <= b


Always statement
Syntax:
always @(sensitivity list)
statement;
➢ Statements in always statement is executed only when the event specified in sensitivity list
occurs.
➢ Always statement can be used to design flip-flop, latches or combinational circuit depend
on the sensitivity list and statement.

- Types of always statement:


+ always @(sensitivity list) can be used to design sequential or combinational circuit based on
sensitivity list
➢ always_latch is dedicated for design latch
➢ always_ff is dedicated for design flip flop
To design D flip-flop: always@(posedge clk)
Statement
always_ff (Flip-flop) always_latch (Latch)

Update Đồng bộ theo cạnh clock Không đồng bộ, hoạt động theo
tín hiệu enable
Syntax always_ff @(posedge clk) hoặc always_latch
@(negedge clk)
Using to design Dùng cho các mạch đồng bộ Dùng cho các mạch không đồng
bộ
State change Thay đổi tại cạnh xung clock Thay đổi bất kỳ khi nào có enable

Applications Thanh ghi, bộ đếm, mạch trạng thái Mạch giữ dữ liệu, các mạch điều
khiển giữ trạng thái
Common used statement
for while
for (initialization; condition; increment) begin while (condition) begin
// Loop body // Statements to execute while the condition is true
end end

if – else case
if (condition) begin case (expression)
// Statements to execute when the condition is true value1: begin
end // Code for when expression matches value1
else begin end
// Statements to execute when the condition is false value2: begin
end // Code for when expression matches value2
end
// More value cases...
default: begin
// Code for when no value case matches the expression
end
endcase
D flipflop
Design D flip flop using always_ff and non-blocking assignment.
D flipflop truth table
clk d q

1 1

0 0

other values x previous value

Ex: always_ff @(posedge clock) begin


// Your sequential logic here
end
- Using non-blocking assignment.
D- flipflop
d_flipflop.sv d_flipflop_tb.sv
module d_flipflop(input logic clk, d, module d_flipflop_tb();
output logic q);
always_ff@(posedge clk) logic clk, d, q;
begin d_flipflop dut(clk, d, q);
q <= d;
end //Clock signal generation
always begin
clk = ~ clk; #5;
endmodule end

initial begin
clk = 0;
d = 0;

for (int i = 0; i < 20; i++)


begin
d = ~ d; #3;
end

end

endmodule
D- flipflop simulation result
Pin assignments
D flipflop
Ex1: Design an D flipflop having following truth table using in SystemVerilog and simulate on
ModelSim.
S-R flipflop
Ex2: Design an S-R flipflop having following truth table using in SystemVerilog and simulate on
ModelSim.
JK flipflop
Ex3: Design an JK flipflop having following truth table using in SystemVerilog and simulate on
ModelSim.
S-R latch
Ex4: Design an S-R latch having following truth table using in SystemVerilog and simulate on
ModelSim.

enable D Q next Q’ next

0 X Keep_state Keep_state

1 0 0 1

1 1 1 0
D latch
Ex5: Design an D latch having following truth table using in SystemVerilog and simulate on
ModelSim.

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