Computer Organization UNIT-5 II B.

SC [SEM-3]

UNIT-5
Computer Arithmetic and Parallel Processing: Data representation – fixed point, floating point,
addition and subtraction, Multiplication and division algorithms.
Parallel Processing:- Parallel Processing, Pipelining, Arithmetic Pipeline, Instruction Pipeline.

Data Representation: Data types:

• Bit: The most basic unit of information in a digital computer is called a bit, which is a
contraction of binary digit.
• Byte: In 1964, the designers of the IBM System/360 main frame computer established a
convention of using groups of 8 bits as the basic unit of addressable computer storage.
They called this collection of 8 bits a byte.
• Word: Computer words consist of two or more adjacent bytes that are sometimes addressed
and almost always are manipulated collectively. The word size represents the data size that
is handled most efficiently by a particular architecture. Words can be 16 bits, 32 bits, 64
bits.
• Nibbles: Eight-bit bytes can be divided into two 4-bit halves call nibbles.
COMPUTER ARITHMETIC Introduction:-
→ Arithmetic instructions in digital computers manipulate data to produce results necessary
for the solution of computational problems.
→ These instructions perform arithmetic calculations and are responsible for the bulk of
activity involved in processing data in a computer.
→ The four basic arithmetic operations are addition, subtraction, multiplication and
division. From these four bulk operations, it is possible to formulate other arithmetic
functions and solve scientific problems by means of numerical analysis methods.
→ An arithmetic processor is the part of a processor unit that executes arithmetic operations.
The data type assumed to reside in processor registers during the execution of an
arithmetic instruction is specified in the definition of the instruction. A:n arithmetic
instruction may specify binary or decimal data, and in each case the data may be in fixed-
point or floating-point form.
→ We must be thoroughly familiar with the sequence of steps to be followed in order to carry
out the operation and achieve a correct result. The solution to any problem that is stated by
a finite number of well-defined procedural steps is called an algorithm.
→ Usually, an algorithm will contain a number of procedural steps which are dependent on
results of previous steps. A convenient method for presenting algorithms is a flowchart.

Addition and Subtraction:

➢ As we have discussed, there are three ways of representing negative fixed-point binary
numbers: signed-magnitude, signed-1's complement, or signed-2's complement. Most
computers use the signed-2's complement representation when performing arithmetic
operations with integers.

i. Addition and Subtraction with Signed-Magnitude Data:

When the signed numbers are added or subtracted, we find that there are eight different
conditions to consider, depending on the sign of the numbers and the operation performed.

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Algorithm: (Addition with Signed-Magnitude Data)

i. When the signs of A and B are identical ,add the two magnitudes and attach the sign of A to
the result.
ii. When the signs of A and B are different, compare the magnitudes and subtract the smaller
number from the larger. Choose the sign of the result to be the same as A if A > B or the
complement of the sign of A if A < B.
iii. If the two magnitudes are equal, subtract B from A and make the sign of the result positive.

Algorithm: (Subtraction with Signed-Magnitude Data)

i. When the signs of A and B are different, add the two magnitudes and attach the sign of A to
the result.
ii. When the signs of A and B are identical, compare the magnitudes and subtract the smaller
number from the larger. Choose the sign of the result to be the same as A if A > B or the
complement of the sign of A if A < B.
iii. If the two magnitudes are equal, subtract B from A and make the sign of the result positive.

Hardware Implementation:
To implement the two arithmetic operations with hardware, it is first necessary that the two
numbers be stored in registers.
i. Let A and B be two registers that hold the magnitudes of the numbers, and AS and BS be two
flip-flops that hold the corresponding signs.
ii. The result of the operation may be transferred to a third register: however, a saving is
achieved if the result is transferred into A and AS. Thus A and AS together form an
accumulator register.
Consider now the hardware implementation of the algorithms above.
• First, a parallel-adder is needed to perform the microoperation A + B.
• Second, a comparator circuit is needed to establish if A > B, A = B, or A < B.
• Third, two parallel-subtractor circuits are needed to perform the microoperations A - B and
B - A. The sign relationship can be determined from an exclusive-OR gate with AS and BS as
inputs.
The below figure shows a block diagram of the hardware for implementing the addition and
subtraction operations. It consists of registers A and B and sign flip-flops AS and BS.

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• Subtraction is done by adding A to the 2' s complement of B. The output carry is transferred
to flip-flop E, where it can be checked to determine the relative magnitudes of the two
numbers.
• The add-overflow flip-flop AVF holds the overflow bit when A and B are added.

Figure (i): Hardware for addition and subtraction with Signed-Magnitude Data

The complementer provides an output of B or the complement of B depending on the state of the
mode control M.
❖ When M = 0, the output of B is transferred to the adder, the input carry is 0, and the output
of the adder is equal to the sum A + B.
❖ When M= 1, the l's complement of B is applied to the adder, the input carry is 1, and output
This is equal to A plus the 2's complement of B, which is equivalent to the subtraction A - B.

Hardware Algorithm:

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ii) Addition and Subtraction with Signed-2's Complement Data

➢ The register configuration for the hardware implementation is shown in the below Figure(a).
We name the A register AC (accumulator) and the B register BR. The leftmost bit in AC and
BR represents the sign bits of the numbers. The two sign bits are added or subtracted
together with the other bits in the complementer and parallel adder. The overflow flip-flop V
is set to 1 if there is an overflow. The output carry in this case is discarded.
➢ The algorithm for adding and subtracting two binary numbers in signed-2' s complement
representation is shown in the flowchart of Figure(b). The sum is obtained by adding the
contents of AC and BR (including their sign bits). The overflow bit V is set to 1 if the exclusive-
OR of the last two carries is 1, and it is cleared to 0 otherwise. The subtraction operation is
accomplished by adding the content of AC to the 2's complement of BR.
➢ Comparing this algorithm with its signed-magnitude counterpart, we note that it is much
simpler to add and subtract numbers if negative numbers are maintained in signed-2' s
complement representation.
Example:+32 is represented as 00100001 and -32 as 11011111. Note that 11011111 is the 2’s
complement of 00100001.

Multiplication Algorithms:
Multiplication of two fixed-point binary numbers in signed-magnitude representation is done with
paper and pencil by a process of successive shift and adds operations. This process is best
illustrated with a numerical example.

The process of multiplication:

• It consists of looking at successive bits of the multiplier, least significant bit first.
• If the multiplier bit is a 1, the multiplicand is copied down; otherwise, zeros are copied down.

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• The numbers copied down in successive lines are shifted one position to the left from the
previous number.
• Finally, the numbers are added and their sum forms the product.

The sign of the product is determined from the signs of the multiplicand and multiplier. If they are
alike, the sign of the product is positive. If they are unlike, the sign of the product is negative.

Hardware Implementation for Signed-Magnitude Data

→ The registers A, B and other equipment are shown in Figure (a). The multiplier is stored in
the Q register and its sign in Qs. The sequence counter SC is initially set to a number equal to
the number of bits in the multiplier. The counter is decremented by 1 after forming each
partial product. When the content of the counter reaches zero, the product is formed and the
process stops.

Figure(k): Hardware for multiply operation

→ Initially, the multiplicand is in register B and the multiplier in Q, their corresponding signs
are in Bs and Qs, respectively
→ The sum of A and B forms a partial product which is transferred to the EA register.
→ Both partial product and multiplier are shifted to the right. This shift will be denoted by the
statement shr EAQ to designate the right shift.
→ The least significant bit of A is shifted into the most significant position of Q, the bit fromE is
shifted into the most significant position of A, and 0 is shifted into E. After the shift, one bit
of the partial product is shifted into Q, pushing the multiplier bits one position to the right.In
this manner, the rightmost flip-flop in register Q, designated by Qn, will hold the bit of the
multiplier, which must be inspected next.

Hardware Algorithm:
→ Initially, the multiplicand is in B and the multiplier in Q. Their corresponding signs are in Bs
and Qs, respectively. The signs are compared, and both A and Q are set to correspond to the
sign of the product since a double-length product will be stored in registers A and Q. Registers
A and E are cleared and the sequence counter SC is set to a number equal to the number of
bits of the multiplier.
→ After the initialization, the low-order bit of the multiplier in Qn is tested.
i. If it is 1, the multiplicand in B is added to the present partial product in A .

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ii. If it is 0 , nothing is done. Register EAQ is then shifted once to the right to form the
new partial product.
→ The sequence counter is decremented by 1 and its new value checked. If it is not equal to
zero, the process is repeated and a new partial product is formed. The process stops when
SC = 0.
→ The final product is available in both A and Q, with A holding the most significant bits and Q
holding the least significant bits. A flowchart of the hardware multiply algorithm is shown in
the below figure (l).

Figure(l): Flowchart for multiply operation

Figure (m): Numerical Example of multiplication

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Booth Multiplication Algorithm:(multiplication of 2’s complement data):

• Booth algorithm gives a procedure for multiplying binary integers in signed-2's
complement representation.
• Booth algorithm requires examination of the multiplier bits and shifting of the partial
product. Prior to the shifting, the multiplicand may be added to the partial product,
subtracted from the partial product, or left unchanged according to the following
rules:
1. The multiplicand is subtracted from the partial product upon encountering the first
least significant 1 in a string of 1's in the multiplier.
2. The multiplicand is added to the partial product upon encountering the first 0
(provided that there was a previous 1) in a string of O's in the multiplier.
3. The partial product does not change when the multiplier bit is identical to the previous
multiplier bit.
Hardware implementation of Booth algorithm Multiplication:

Figure (n): Hardware for Booth Algorithm

The hardware implementation of Booth algorithm requires the register configuration

shown in figure (n). This is similar addition and subtraction hardware except that the sign
bits are not separated from the rest of the registers. To show this difference, we rename
registers A, B, and Q, as AC, BR, and QR, respectively. Qn designates the least significant bit
of the multiplier in register

QR. An extra flip-flop Qn+1, is appended to QR to facilitate a double bit inspection of the
multiplier. The flowchart for Booth algorithm is shown in Figure (o).
Hardware Algorithm for Booth Multiplication:
• AC and the appended bit Qn+1 are initially cleared to 0 and the sequence counter SC is
set to a number n equal to the number of bits in the multiplier. The two bits of the
multiplier in Qn and Qn+1 are inspected.
i. If the two bits are equal to 10, it means that the first 1 in a string of 1's has been
encountered. This requires a subtraction of the multiplicand from the partial product in
AC.
ii. If the two bits are equal to 01, it means that the first 0 in a string of 0's has been
encountered. This requires the addition of the multiplicand to the partial product in AC.
iii. When the two bits are equal, the partial product does not change.
iv. The next step is to shift right the partial product and the multiplier (including bit Qn+1).
This is an arithmetic shift right (ashr) operation which shifts AC and QR to the right and
leaves the sign bit in AC unchanged. The sequence counter is decremented and the

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computational loop is repeated n times.

Figure (o): Booth Algorithm for multiplication of 2’s complement numbers

Example: multiplication of ( - 9) x ( - 13) = + 117 is shown below. Note that the multiplier in QR is
negative and that the multiplicand in BR is also negative. The 10-bit product appears in AC and QR
and is positive.

Figure (p): Example of Multiplication with Booth Algorithm.

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Division Algorithms:
→ Division of two fixed-point binary numbers in signed-magnitude representation is done with
paper and pencil by a process of successive compare, shift, and subtract operations.
→ The division process is illustrated by a numerical example in the below figure (q).
→ The divisor B consists of five bits and the dividend A consists of ten bits. The five most
significant bits of the dividend are compared with the divisor. Since the 5-bit number is
smaller than B, we try again by taking the sixth most significant bits of A and compare this
number with B. The 6-bit number is greater than B, so we place a 1 for the quotient bit. The
divisor is then shifted once to the right and subtracted from the dividend.
→ The difference is called a partial remainder because the division could have stopped here
to obtain a quotient of 1 and a remainder equal to the partial remainder. The process is
continued by comparing a partial remainder with the divisor.
→ If the partial remainder is greater than or equal to the divisor, the quotient bit is equal to 1.
The divisor is then shifted right and subtracted from the partial remainder.
→ If the partial remainder is smaller than the divisor, the quotient bit is 0 and no subtraction
is needed. The divisor is shifted once to the right in any case. Note that the result gives both
a quotient and a remainder.

Figure (q): Example of Binary Division

Hardware Implementation for Signed-Magnitude Data:

The hardware for implementing the division operation is identical to that required for
multiplication.
✓ The divisor is stored in the B register and the double-length dividend is stored in registers A
and Q. The dividend is shifted to the left and the divisor is subtracted by adding its 2's
complement value. The information about the relative magnitude is available in E.
✓ If E = 1, it signifies that A≥B. A quotient bit 1 is inserted into Q, and the partial remainder is
shifted to the left to repeat the process.
✓ If E = 0, it signifies that A < B so the quotient in Qn remains a 0. The value of B is then added
to restore the partial remainder in A to its previous value. The partial remainder is shifted to
the left and the process is repeated again until all five quotient bits are formed.
✓ Note that while the partial remainder is shifted left, the quotient bits are shifted also and
after five shifts, the quotient is in Q and the final remainder is in A.
✓ The sign of the quotient is determined from the signs of the dividend and the divisor. If the
two signs are alike, the sign o f the quotient is plus. If they are unalike, the sign is minus. The
sign of the remainder is the same as the sign of the dividend.

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Hardware Algorithm:
1. The dividend is in A and Q and the divisor in B . The sign of the result is transferred into Qs
to be part of the quotient. A constant is set into the sequence counter SC to specify the number of
bits in the quotient.
2. A divide-overflow condition is tested by subtracting the divisor in B from half of the bits of
the dividend stored in A. If A ≥ B, the divide-overflow flip-flop DVF is set and the operation is
terminated prematurely. If A < B, no divide overflow occurs so the value of the dividend is restored
by adding B to A.
3. The division of the magnitudes starts by shifting the dividend in AQ to the left with the high-
order bit shifted into E. If the bit shifted into E is 1, we know that EA > B because EA consists of a 1
followed by n-1 bits while B consists of only n -1 bits. In this case, B must be subtracted from EA and
1 inserted into Qn for the quotient bit.
4. If the shift-left operation inserts a 0 into E, the divisor is subtracted by adding its 2's
complement value and the carry is transferred into E . If E = 1, it signifies that A ≥ B; therefore, Qn
is set to 1 . If E = 0, it signifies that A < B and the original number is restored by adding B to A . In
the latter case we leave a 0 in Qn.

This process is repeated again with registers EAQ. After n times, the quotient is formed in
register Q and the remainder is found in register A

Figure (r ): Flowchart for Divide operation

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Figure (s): Example of Binary Division

Floating-point arithmetic operations: -

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Division:-

Q) Explain about Parallel Processing.

Parallel Processing: -
Parallel processing can be described as a class of techniques which enables the system to achieve
simultaneous data-processing tasks to increase the computational speed of a computer system.
A parallel processing system can carry out simultaneous data-processing to achieve faster
execution time. For instance, while an instruction is being processed in the ALU component of the
CPU, the next instruction can be read from memory.
The primary purpose of parallel processing is to enhance the computer processing capability and
increase its throughput, i.e. the amount of processing that can be accomplished during a given
interval of time.
A parallel processing system can be achieved by having a multiplicity of functional units that
perform identical or different operations simultaneously. The data can be distributed among
various multiple functional units.

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The following diagram shows one possible way of separating the execution unit into eight functional units
operating in parallel.

The operation performed in each functional unit is indicated in each block if the diagram:

• The adder and integer multiplier performs the arithmetic operation with integer numbers.
• The floating-point operations are separated into three circuits operating in parallel.
• The logic, shift, and increment operations can be performed concurrently on different data. All units
are independent of each other, so one number can be shifted while another number is being
incremented.

Q) Explain about Pipeling.

Pipelining: - Pipelining is a computer architecture technique that allows a processor to execute
multiple instructions simultaneously, improving overall performance

Pipelining is a technique of decomposing a sequential process into sub operations, with each sub
process being executed in a special dedicated segment that operates concurrently with all other
segments.

Example:

Suppose we need to perform multiply and add operation with a stream of numbers

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The operation to be performed on the numbers is decomposed into sub-operations with each
sub- operation to be implemented in a segment within a pipeline.

The sub-operations performed in each segment of the pipeline are defined as:

The following block diagram represents the combined as well as the sub-operations performed
in each segment of the pipeline.

Registers R1, R2, R3, and R4 hold the data and the combinational circuits operate in a
particular segment. The above figure shows R1 through R5 are registers that receive new data
with every clock pulse.

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Table: Content of Registers in pipeline Example

The Above diagram shows the first clock pulse transfers A1 and B1 intoR1 and R2. The second
clock pulse transfers the product of R1 and R2 into R3 and C1 into R4. The same clock pulse
transfers A2 and B2 into R1 and R2.The third clock pulse operates on all three segments
simultaneously.

It places A3 and B3 into R1 and R2, transfer the product of R1 and R2 into R3, transfers C2 into
R4, and places the sum of R3 and R4 into R5. It takes three clock pulses to fill up pipe and retrieve
the first output from R5.

Four Segment pipeline:

The general structure of a four-segment pipeline is shown in figure. The operand pass through all
four segments in a fixed sequence. Each segment combinational circuit Si that performs a sub
operation over the data stream flowing through the pipe.

Space time diagram for pipeline.

The above space time diagram consists of Horizontal axis display the time in clock cycles and
vertical axis gives the segment number. The diagram shows six tasks T1 through T6 executed in
four segments. Initially task T1 is handled by segment 1. After the first clock, segment 2 is busy
with T1, while segment 1 is busy with task T2. Continuing in manner.

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Q) Explain about Arithmetic Pipeline.

Arithmetic Pipeline: -
Arithmetic Pipelines are mostly used in high-speed computers. They are used to implement
floating-point operations, multiplication of fixed-point numbers, and similar computations
encountered in scientific problems.

To understand the concepts of arithmetic pipeline in a more convenient way, let us consider an
example of a pipeline unit for floating-point addition and subtraction.

The inputs to the floating-point adder pipeline are two normalized floating-point binary numbers
defined as:

X = A * 2a = 0.9504 * 103
Y = B * 2b = 0.8200 * 102

Where A and B are two fractions that represent the mantissa and a and b are the exponents.

The combined operation of floating-point addition and subtraction is divided into four segments. Each
segment contains the corresponding suboperation to be performed in the given pipeline. The suboperations
that are shown in the four segments are:

1. Compare the exponents by subtraction.

2. Align the mantissas.
3. Add or subtract the mantissas.
4. Normalize the result.
The following block diagram represents the suboperations performed in each segment of the pipeline.

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Note: Registers are placed after each suboperation to store the intermediate results.
1. Compare exponents by subtraction:
The exponents are compared by subtracting them to determine their difference. The larger exponent is
chosen as the exponent of the result.
The difference of the exponents, i.e., 3 - 2 = 1 determines how many times the mantissa associated with the
smaller exponent must be shifted to the right.

2. Align the mantissas:

The mantissa associated with the smaller exponent is shifted according to the difference of exponents
determined in segment one.
X = 0.9504 * 103
Y = 0.08200 * 103

3. Add mantissas: - The two mantissas are added in segment three.

Z = X + Y = 1.0324 * 103

4. Normalize the result:- After normalization, the result is written as:

Z = 0.1324 * 104

Q) Explain about Instruction Pipeline.

Pipeline processing can occur not only in the data stream but in the instruction stream as well.

Most of the digital computers with complex instructions require instruction pipeline to carry out
operations like fetch, decode and execute instructions.

In general, the computer needs to process each instruction with the following sequence of steps.

1. Fetch instruction from memory.

2. Decode the instruction.
3. Calculate the effective address.
4. Fetch the operands from memory.
5. Execute the instruction.
6. Store the result in the proper place.

Each step is executed in a particular segment, and there are times when different segments may
take different times to operate on the incoming information. Moreover, there are times when two
or more segments may require memory access at the same time, causing one segment to wait until
another is finished with the memory.

The organization of an instruction pipeline will be more efficient if the instruction cycle is divided
into segments of equal duration. One of the most common examples of this type of organization is
a Four-segment instruction pipeline.

A four-segment instruction pipeline combines two or more different segments and makes it as a
single one. For instance, the decoding of the instruction can be combined with the calculation of
the effective address into one segment.

The following block diagram shows a typical example of a four-segment instruction pipeline. The
instruction cycle is completed in four segments.

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Segment 1:
The instruction fetch segment can be implemented using first in, first out (FIFO) buffer.
Segment 2:
The instruction fetched from memory is decoded in the second segment, and eventually, the effective
address is calculated in a separate arithmetic circuit.

Segment 3:
An operand from memory is fetched in the third segment.

Segment 4:
The instructions are finally executed in the last segment of the pipeline organization.

END OF THE UNIT- 5

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