FLOORPLAN

What is floorplan?
Inputs of floorplan
Objectives of floorplan
Types of floorplan techniques?
Steps of floorplan
Outputs of floorplan
Checks after floorplan
Some important commands

Venkatesh.G
 PHYSICAL DESIGN

FLOORPLANING

Floorplaning is the art of any physical design. The good floorplan decides the quality of
design with higher performance and optimum area.
In floorplan we deals with creation of core area , calculation of Aspect ratio , specifying
core to die boundary spacing ( core offset) ,std cell rows , placing of I/O ports , macro
placement, creating halos , adding placement blockages.
Aspect ratio: Aspect ratio will decide the size and shape of the chip. It is the ratio between
horizontal routing resources to vertical routing resources (or) ratio of height and width.
Aspect ratio = width/height
Core utilization:- Utilization will define the area occupied by the standard cells, macros,
and other cells. If core utilization is 0.8 (80%) that means 80% of the core area is used for
placing the standard cells, macros, and other cells, and the remaining 20% is used for
routing purposes.
core utilization = (macros area + std cell area +pads area)/ total core area
 Inputs of floorplan:
1. Gate level netlist(.v)
2. Logic library or timing library(.lib)
3. Physical library(.lef)
4. Technology file(.tf for synopsys and .techlef for cadence)
5. Synopsys design constraints or Standard design constraints(.sdc)
6. TLU+ file
7. Unified power format(upf file for multi-voltage design block)
8. Multi mode multi corner(mcmm)
 Objectives of floorplan
• minimize the area
• minimize the timing
• minimize the power
• minimize congestion
• reduce the wirelength
• optimize dataflow
Types of floorplan techniques:
• Abutted:- When the chip is divided into blocks in the abutted design there is no
gap between the blocks.
• In block level there is no channel spacing between macros.
• Non abutted:- In this design there is a gap between blocks. The connection
between the blocks is done through the routing nets.

• The mix of both: This design is a combination of both abutted and non- abutted .
 Steps of floorplan
• Perform sanity checks
• Create a floorplan
• Placing the I/O ports
• Placing macros by following macro placement guidelines
• Set the keepout margin and fix the macros
• Add Endcap cell
• Add Tap cells
• Check Legality
Sanity Checks :
We need to perform some sanity checks before we start our physical
design flow, to ensure that inputs received from various team such as synthesis
team, library team etc are correct. If we missed this checks than it can create
problem in later stage.
Below are input fies which we are mainly checking
1.check_design or check_netlist
2.check_ timing
3.check_library or report_design_mismatch
• Check_design:
It checks the current design for consistency and It checks the internal
representation of the current design forconsistency and issues error and warning
messages as appropriate.
• It checks the quality of netlist and identifies:
- Floating pins
- Multidriven nets
- Black box module
- Undriven input ports
- Unloaded output ports
- Unconstrained pins
• Check_timing:
PNR tool wont optimize the paths which are not constrained. So, we have
to check if any unconstrained paths are exist in the design.
This checks:
- Clock reaching all the clock pins of flops or not
- Ports missing input/output delay
- Multiple clocks driving same register
- Unconstrained end points
- Combinational loops
• Check_library:
It performs consistency checks between logical and physical libraries. Suppose, if
designer forgot to load either HVT, LVT or .lib, then there will be inconsistency. It checks
library qualities in three main areas:
- Physical library quality
- Logic versus physical library consistency
- Logic versus logic library consistency
- Missing pin information
- Missing cell information
- Duplicate cells
 To create floorplan, given
a. Core Utilization
b. Aspect ratio
c. Space between die area and core area
• ICC2 Command:
initialize_floorplan –core_utilization value -core_offset{value}

 Placing the I/O ports:

• Commands:
Set the constraints for the pin placement
set_block_pin_constraints -self –allowed_layers {metal layers} -sides{value}
For input port:
place_pins -ports [get_ports -filter direction==in]
For output port:
place_pins -ports [get_ports -filter direction==out]
• To fix the ports, Command:
set_attribute [get_ports *] physical_status_fixed
• To check whether ports are fixed or not
get_attribute [get_ports *] is_fixed

• Types of macros:
Hard macros: The circuit is fixed. We can’t see the functionality information about
macros. Only we know the timing information.
Soft macros: The circuit is not fixed and we can see the functionality and which type
of gates are using inside it. Also we know the timing information.

 Placing macros by following macro placement guidelines

1. check the hierarchy of macros and place together as per hierarchy
2. Check fly-line analysis
*Priority to fly-line connections:
. Macro to I/O ports
. Macro to Macro
. Macro to std-cells
3. Keep the sufficient channel space between macros.
channel width= [no. of pins*metal pitch of highest metal layer]/[no. of layers/2]

4. Avoid notches while placing macros, if anywhere notches is present then use hard
blockages in that area

5. Avoid criss-cross connections

6. Avoid placing macros in the centre of the core area. Else, it may lead to detours and
congestion.
7. See the macro pin face core side
8. Avoid placing macros near to I/O ports which might block the routing for I/O ports
If you place macros where more I/O ports are present, provide enough space
between I/O and macros to avoid routing congestion

9. Make sure the macros are oriented to match the std-cell poly orientation

10. Have keepout margin/ Halo, usually 0.5um-1um around macros as a protection
Command:
create_keepout_margin -type hard -outer {boundary values} [get_cells –physical_context
-filter design_type==macro]

We need more empty space around macros, and in channel area to provide
sufficient routing space to route the macro pins.
• Apply placement blockages between macros to avoid congestion
Blockages used in Physical Design mainly for two purpose, Placement and
Routing.
Placement Blockages: There are mainly three types.
1. Hard Blockage
2. Soft Blockage
3. Partial Blockage

• Hard Blockage- No cell is allowed to place in specified region.

• Soft Blockage- Only buffers/inverters needed for optimization are allowed to place in
specified region.
• Partial Blockage- Any type of cells are allowed to place but only for defined area of specific
region. (like 60% of specified area)
Commands:
• For soft blockage:
create_placement_blockage -boundary {values} -name PB1 -type soft
• For hard blockage:
create_placement_blockage -boundary {values} -name PB1 -type hard
• For partial blockage:
create_placement_blockage -boundary {values} -type partial
-blocked_percentage 40

Routing Blockages: There are mainly two types.

1. Hard Blockage
2. Signal Blockage

• Hard Blockage- any type of net is not allowed to route through specified region.
• Signal Blockage- any type of data and clock signal net is not allowed to route through
specified region, but power net is allowed to route.
• Difference b/w halo and blockages
Halo:
Halo is the region around the boundary of fixed macro in the design in which no other
macro or standard cells can be placed. Halo allows placement of buffers and inverters in its area.

Blockages:
Blockages are specified locations where placing cells are prevented or blocked. These act as
guidelines for placing standard cells in the design.

• If macro are moved from one place to another place, halos will also be moved. But in case of
blockages if the macros are moved from one place to another place the blockages can't be
moved.
 Automatically also we can place macros in core area by using command with congestion, timing
efforts.
• Command to place macros:
create_placement -floorplan -congestion_driven –timing_driven
But here placement also happening to remove placement, we have command
reset_placement

• Command to fix macros:

set_attribute [get_cells -physical_context -filter design_type==macro] physical_status_fixed
(or)
set_fixed_objects [get_flat_cells* -filter {is_macros==true}]
• Command to check whether macros are fixed or not:
get_attribute [get_cells -physical_context -filter design_type==macro] is_fixed
• Command to check whether macros are placed or not:
get_attribute [get_cells -physical_context -filter design_type==macro] physical_status
Adding End cap cells and Tap cells
End Cap or boundary cell:
• Placed to avoid well proximity effect
• There are high chances to get damaged the gate of standard cells placed at the boundary
during the manufacturing of chip. To prevent such damages at the boundary we have a
special kind of cell in the standard cell library is called end cap cell or boundary cell
• The end cap cells place at boundaries of core area
• These cells ensure that gaps do not occur between the well and implant layer and to
prevent from the DRC violations.
Command:
addEndCap -prefix <name>
• Tap cell:
- used to prevent the latch-up issue
-These cells are typically used when most or all of the standard cells in the library contain no
substrate or well taps
-This cell connects the power VDD and ground VSS to the n-well and substrate (i.e n-well to VDD
and p-substrate to VSS). It ensures n-well substrate continuity in the design. By placing well taps
at regular intervals in design the n-well potential is held constant for proper electrical functionality.
 Figure-3: Well tap cell placement

• Well tap cells are generally placed in a straight column in the alternate row as shown in
figure and such a pattern is called checkerboard pattern to provide maximum coverage for
well tap. If a macro comes in the path of vertical columns, then the placement of vertical
column shifted alongside macro as shown in the figure.
Latch-up issue:
• It is the condition when low impedance path gets formed between POWER and GND terminal and
there is direct current flow from VDD to GND which might result in a complete failure of chip.
• While the formation of CMOS INVERTER we saw the formation of PN junctions and because of
these PN junctions there may be formation of parasitics elements like diode and transistors.

FIG: latch-up phenomenon

• Transistors Q1(NPN) and Q2(PNP) are parasitics transistors that are getting formed during the
manufacturing of CMOS inverter. If these two parasitic transistors are in on condition then
current starts flowing from VDD to VSS and creates a short circuit. while manufacturing these
devices the designer made sure that all PN junction should be in reverse bias so that no
parasitic transistor will turn on and hence the normal operation will not be affected. but
sometimes what happened because of external elements (like input and output) the parasitic
transistors get turned on.

• For parasitics transistor gets turned on there are two scenarios:

1.When the input and output > VDD: PNP transistor in ON condition:
Because now P region is more positive than N region in Nwell, therefore
Base-Emitter junction of PNP (Q2) transistor is in Forward biased and now this transistor will
turn on. Now if we see in the fig the collector of PNP transistor is connected to the base of NPN
transistor, because of this connection the current is flowing from collector (PNP) to base (NPN)
and then because of this base current the NPN transistor gets turn on and the current flowing
from VDD to VSS through these two parasitics transistors. This current is flowing even if we
removed the external inputs and outputs and parasitic transistors make a feedback path in
which current is latched up and creates a short circuit path.
2.When input and output <VSS: NPN transistor in ON condition:
Now N region is more negative than P region in P substrate, therefore
Base-Emitter junction of NPN (Q1) transistor is in Forward biased and now this transistor will
turn on. Now if we see in the fig the Base of NPN transistor is connected to the Collector of PNP
transistor, because of this connection the current is flowing from Base (NPN) to Collector (PNP)
and then because of this Collector current the PNP transistor gets turn on and current flowing
from VDD to VSS through these two parasitics transistors. This current is flowing even if we
removed the external inputs and outputs and parasitic transistors make a feedback path in
which current is latched up and creates a short circuit path.

• In the fig shown above, the value of Rnwell and Rpsub resistance is quite high, if the values
of these resistances will reduced then what will happen? The current flowing from the
collector of PNP transistor will flow from these resistance paths, i.e current find the low
resistance path to reach from VDD to VSS and NPN transistor will never get turn on and in this
way, latchup problem will not occur.
• Solution for latch-up problem:
Reducing the resistance values: tap the n-well to VDD and p-substrate to GND externally.

fig: tapping the VDD with n-well and VSS with p-sub
externally

• Fixes for latch-up:

1. Use guard rings
2. Use silicon-on insulator devices
3. Use lightly doped epitaxial layers
4. Increase well and substrate doping concentrations.
• Command for Tap cell:
create_tap_cells -lib_cell myreflib/mytapcell -distance 30
or
addTapCell -cell <cellname> -cellinterval <maxgap> -prefix <name>
• Check legality for End cap and Tap cells
check the placement of end cap cells and tap cells are proper, and no violations
run the following commands.
check_legality -cells [get_cells bound*]
check_legality -cells [get_cells tap*]
Outputs of floorplan:
1. get core and boundary area
2. IO ports/pins placed
3. macros placement done
4. floorplan def file

 How can you say the floorplan is good?

a good floorplan should meet the following constraints:
1. minimize the total chip area
2. routing should be easy
Checks after floorplan:
• All I/O ports are placed and in fixed state. They should be on track
• All macros are placed in correct orientation and in fixed state
• No macros are overlapping
• I/O port routing should not be blocked by macro placement
• Checking legality (cells are legally placed or not)
• Utilization report
Some important commands to remember
1. To get I/O ports in your design
get_ports
2. To get the count of the ports
sizeof_collection [get_ports *]
3. For utilization, first we have to create then we have to analyze the report
create_utilization_configuration -scope block core_utilization -include {all}
report_utilization -config core_utilization
4. To check how many macros, std-cells, buffers/inverters and area of core..
report_design
5. To get all macros in the design
get_flat_cells* -filter {is_macro==true}
6. To get cells in the design
get_cells
7. To get the hierarchy cells of the design
get_cells –hierarchy
8. To select any object
change_selection
THANK YOU