ICE5ARxxxxBZS

Fixed Frequency 700 V/800 V CoolSET™ - in DIP-

7 Package

Product highlights
 Integrated 700 V/ 800 V avalanche rugged CoolMOS™
 Enhanced Active Burst Mode with selectable entry and exit standby
power to reach the lowest standby power <100 mW PG-DIP-7
 Digital frequency reduction for better overall system efficiency
 Fast startup achieved with cascode configuration
 Frequency jitter and soft gate driving for low EMI
 Integrated error amplifier
 Comprehensive protection
 Pb-free lead plating, halogen-free mold compound, RoHS compliant

Features Product validation

 Integrated 700 V/ 800 V avalanche rugged Product qualified according to JEDEC Standard
CoolMOS™
 Enhanced Active Burst Mode with selectable entry
and exit standby power
Description
 Digital frequency reduction for better overall The ICE5ARxxxxBZS is the 5th generation of fixed
system efficiency frequency integrated power IC (CoolSET™) optimized
 Fast startup achieved with cascode configuration for off-line switch mode power supply in cascode
configuration. The CoolSET™ package has 2 separate
 DCM and CCM operation with slope compensation
chips inside; one is controller chip and the other is a
 Frequency jitter and soft gate driving for low EMI 700 V/ 800 V CoolMOS™ chip. The cascode
 Built-in digital soft start configuration helps achieve fast startup. The
 Integrated error amplifier to support direct frequency reduction with soft gate driving and
feedback in non-isolated flyback frequency jitter operation offers lower EMI and better
 Comprehensive protection with VCC over voltage,
efficiency between light load and 50% load. The
selectable entry and exit standby power ABM enables
VCC under voltage, overload/open loop, over
flexibility and ultra-low power consumption at
temperature
standby mode with small and controllable output
 All protections are in auto restart mode voltage ripple. The product has a wide operating
 Limited charging current for VCC short to GND range (10.0 ~ 25.5 V) of IC power supply and lower
power consumption. The numerous protection
functions support the power supply system in failure
Applications situations. All these make the 5th generation
 Auxiliary power supply for home appliances/white CoolSET™ series an outstanding integrated power
goods, TV, PC & server stage fixed frequency flyback converter in the market.
 Blu-ray player, set-top box & LCD/LED monitor

Datasheet Please read the Important Notice and Warnings at the end of this document V 2.3
www.infineon.com page 1 of 36 2020-02-03
ICE5ARxxxxBZS

Wp DO1 Lf1
Cbus RSTARTUP Snubber CO1 Cf1 VO1
Ws1
85 ~ 300 VAC RVCC DVCC
CVCC
DO2 Lf2
CO2 Cf2 VO2
Wa Ws2
Dr1~Dr4
VCC GATE DRAIN
CPS
CoolMOSTM
Power Management

D
PWM controller
Current Mode Control
Cycle-by-Cycle Gate
GND current limitation Rb1 Rb2 Rovs1 # Rovs3
Driver CS RCS
Digital Control
VERR Rc1
Error Amplifier
FB
Active Burst Mode Control Unit
# Optional Cc1 Cc2

# RSel
RSel (Burst mode detect) C2
Protections TL431
Rovs3 (V02 feedback) TM Optocoupler Rovs2
ICE5ARxxxxBZS CoolSET

Figure 1 Typical application in isolated flyback using TL431 and optocoupler

Wp DO1 Lf1
Cbus RSTARTUP Snubber CO1 Cf1 VO1
Ws1
85 ~ 300 VAC RVCC DVCC
CVCC

Wa
Dr1~Dr4
VCC GATE DRAIN LfP1 DP1
TM
CoolMOS VP1 W
Power Management CfP1 CP1 P1

D CPS
PWM controller
Current Mode Control
Cycle-by-Cycle Gate
GND current limitation Driver CS RCS RF2
Digital Control
VERR
Error Amplifier
FB
Active Burst Mode RF1
# Optional Control Unit R1
C2
# RSel

RSel (Burst mode detect) Protections C1

ICE5ARxxxxBZS CoolSET TM

Figure 2 Typical application in non-isolated flyback utilizing integrated error amplifier

Output power of 5th generation Fixed-Frequency CoolSET™

Table 1 Output power of 5th generation Fixed-Frequency CoolSET™
220 V AC 85-300 V AC2 85-300 V AC2
Type Package Marking VDS Fsw RDSon1
±20%2 at DCM at DCM at CCM
ICE5AR4770BZS PG-DIP-7 5AR4770BZS 700 V 100 kHz 4.73 Ω 26.5 W 14.5 W 16 W
ICE5AR4780BZS PG-DIP-7 5AR4780BZS 800 V 100 kHz 4.13 Ω 27.5 W 15 W 16 W
ICE5AR0680BZS PG-DIP-7 5AR0680BZS 800 V 100 kHz 0.71 Ω 66 W 39 W 41 W

1
Typ. at TJ =25 °C (inclusive of low side MOSFET)
2
Calculated maximum output power rating in an open frame design at Ta=50 °C, TJ=125 °C (integrated high voltage MOSFET) and using
minimum drain pin copper area in a 2 oz copper single sided PCB. The output power figure is for selection purpose only. The actual
power can vary depending on particular designs. Please contact to a technical expert from Infineon for more information.

Datasheet Please read the Important Notice and Warnings at the end of this document V 2.3
www.infineon.com page 2 of 36 2020-02-03
Fixed Frequency 700 V/800 V CoolSET™ - in DIP-7 Package

Pin configuration and functionality

Table of contents
Product highlights .......................................................................................................................... 1
Features ........................................................................................................................................ 1
Applications ................................................................................................................................... 1
Product validation .......................................................................................................................... 1
Description .................................................................................................................................... 1
Output power of 5th generation Fixed-Frequency CoolSET™................................................................. 2
Table of contents ............................................................................................................................ 3
1 Pin configuration and functionality .......................................................................................... 5
2 Representative block diagram ................................................................................................. 6
3 Functional description ............................................................................................................ 7
3.1 VCC pre-charging and typical VCC voltage during start-up ....................................................................... 7
3.2 Soft-start .................................................................................................................................................. 8
3.3 Normal operation .................................................................................................................................... 8
3.3.1 PWM operation and peak current mode control .............................................................................. 8
3.3.1.1 Switch-on determination.............................................................................................................. 8
3.3.1.2 Switch-off determination ............................................................................................................. 8
3.3.2 Current sense ..................................................................................................................................... 9
3.3.3 Frequency reduction ........................................................................................................................ 10
3.3.4 Slope compensation ........................................................................................................................ 10
3.3.5 Oscillator and frequency jittering.................................................................................................... 11
3.3.6 Modulated gate drive ....................................................................................................................... 11
3.4 Peak current limitation ......................................................................................................................... 11
3.4.1 Propagation delay compensation ................................................................................................... 11
3.5 Active Burst Mode (ABM) with selectable power level ......................................................................... 13
3.5.1 Entering ABM operation ................................................................................................................... 13
3.5.2 During ABM operation ...................................................................................................................... 13
3.5.3 Leaving ABM operation .................................................................................................................... 13
3.5.4 ABM configuration............................................................................................................................ 15
3.6 Non-isolated/isolated configuration .................................................................................................... 15
3.7 Protection functions ............................................................................................................................. 16
3.7.1 VCC over/under voltage ..................................................................................................................... 16
3.7.2 Overload/ open loop ........................................................................................................................ 16
3.7.3 Over temperature............................................................................................................................. 16
3.7.4 VCC short to GND................................................................................................................................ 16
3.7.5 Protection modes............................................................................................................................. 16
4 Electrical characteristics ........................................................................................................ 19
4.1 Absolute maximum ratings ................................................................................................................... 19
4.2 Operating range .................................................................................................................................... 20
4.3 Operating conditions ............................................................................................................................ 20
4.4 Internal voltage reference..................................................................................................................... 21
4.5 PWM section .......................................................................................................................................... 21
4.6 Error amplifier ....................................................................................................................................... 21
4.7 Current sense......................................................................................................................................... 22
4.8 Soft start ................................................................................................................................................ 22
4.9 Active Burst Mode.................................................................................................................................. 22
4.10 VCC over voltage protection ................................................................................................................... 23
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Fixed Frequency 700 V/800 V CoolSET™ - in DIP-7 Package

Pin configuration and functionality

4.11 Overload protection .............................................................................................................................. 23

4.12 Thermal protection ............................................................................................................................... 23
4.13 CoolMOS™ section ................................................................................................................................. 24
5 CoolMOS™ performance characteristics ................................................................................... 25
6 Output power curve .............................................................................................................. 31
7 Outline dimension ................................................................................................................. 33
8 Marking................................................................................................................................ 34
Revision history............................................................................................................................. 35

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Fixed Frequency 700 V/800 V CoolSET™ - in DIP-7 Package

Pin configuration and functionality

1 Pin configuration and functionality

The pin configuration is shown in Figure 3 and the functions are described in Table 2.

VERR 1 PG-DIP-7 8 GND

FB 2 7 VCC

CS 3

GATE 4 5 DRAIN

Figure 3 Pin configuration

Table 2 Pin definitions and functions

Pin Symbol Function
1 VERR Error amplifier
VERR pin is internally connected to the transconductance error amplifier for non-isolated
flyback application. Connect this pin to GND for isolated flyback application.
2 FB Feedback and ABM entry/exit control
FB pin combines the functions of feedback control, selectable burst entry/exit control
and overload/open loop protection.
3 CS Current sense
The CS pin is connected to the shunt resistor for the primary current sensing externally
and to the PWM signal generator block for switch-off determination (together with the
feedback voltage) internally.
4 GATE Gate driver output
The GATE pin is connected to the Gate of the internal CoolMOS™ and additionally, a pull
up resistor is connected from bus voltage to turn on the internal CoolMOS™ for charging
up the VCC capacitor during startup.
5 DRAIN DRAIN(Drain of integrated CoolMOS™)
The DRAIN pin is connected to the drain of the integrated CoolMOS™.
7 VCC VCC(Positive voltage supply)
The VCC pin is the positive voltage supply to the IC. The operating range is between
VVCC_OFF and VVCC_OVP.
8 GND Ground
The GND pin is the common ground of the controller.

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Representative block diagram

2 Representative block diagram

VCC GATE DRAIN

Power Management Thermal Protection

Undervoltage Lockout 50 µs
16.0V Voltage Internal Tj > Tjcon_OT P Blanking S Q
Reference Bias time OTP
10.0V
Mode
R

C20 tVCC_OVP_B Tj < Tjcon_OTP-TjHYS_OTP Autorestart

VVCC_OVP Protect

CoolMOSTM
Error Amplifier fOSC_2
OSC with
Non- Jitter and
Isolated Frequency
Detector Reduction fOSC
OSC D1
VERR
ERR
VERR_REF Gate Driver
VREF Gate
Drive
Protection and PWM Digital Control
RFB
Overload Protection Gate
Drive
Burst
Mode GND
detect VFB_OLP/ C12 tFB_OLP_B
VFB_LB VCS_BLP VREF
VCS_BHP
FB C13
Slope
Active Burst Block Peak current Comp
limit
Burst Mode
25kΩ

VCS_Nx Leading
Level Select
C15 Edge 10kΩ
VFB_EBHP
VFB_EBLP Active
Blanking CS
tCS_LEB 1pF D2
No burst C9 tFB_BEB
Burst Mode PWM
Comparator C15a
2pF V1 CPWM
C10 Soft-start
VFB_BOn PWM OP Delay
VPWM
C19
tCS_STG VCS_STG
C11 GPWM
VFB_BOff Current Mode
Slope Compensation/Current Limiting

Figure 4 Representative block diagram

Note: Junction temperature of the controller chip is sensed for over temperature protection. The
CoolMOSTM is a separate chip from the controller chip in the same package. Please refer to the
design guide and/or consult a technical expert for the proper thermal design.

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Functional description

3 Functional description
3.1 VCC pre-charging and typical VCC voltage during start-up
As shown in Figure 1, once the line input voltage is applied, a rectified voltage appears across the capacitor CBUS.
The pull up resistor RSTARTUP provides a current to charge the Ciss (input capacitance) of CoolMOS™ and gradually
generate one voltage level. If the voltage over Ciss is high enough, CoolMOS™ on and VCC capacitor will be
charged through primary inductance of transformer LP, CoolMOS™ and internal diode D1 with two steps
constant current source IVCC_ Charge11 and IVCC_ Charge31.
A very small constant current source (IVCC_Charge1) is charged to the VCC capacitor till VCC reach VCC_SCP to protect the
controller from VCC pin short to ground during the start up. After this, the second step constant current source
(IVCC_Charge3) is provided to charge the VCC capacitor further, until the VCC voltage exceeds the turned-on threshold
VVCC_ON. As shown in the time phase I in Figure 5, the VCC voltage increase almost linearly with two steps.

VVCC
VVCC_ON I II III

VVCC_OFF
tA tB
VVCC_SCP t

IVCC

IVCC_Normal
t
0
IVCC_Charge1

IVCC_Charge2/3
-IVCC t1 t2

Figure 5 VCC voltage and current at startup

The time taking for the VCC pre-charging can then be approximately calculated as:

𝑉𝑉𝐶𝐶_𝑆𝐶𝑃 ∙ 𝐶𝑉𝐶𝐶 (𝑉𝑉𝐶𝐶_𝑂𝑁 − 𝑉𝑉𝐶𝐶_𝑆𝐶𝑃 ) ∙ 𝐶𝑉𝐶𝐶 (1)

𝑡1 = 𝑡A + 𝑡B = +
𝐼𝑉𝐶𝐶_𝐶ℎ𝑎𝑟𝑔𝑒1 𝐼𝑉𝐶𝐶_𝐶ℎ𝑎𝑟𝑔𝑒3

When the VCC voltage exceeds the VCC turn on threshold VVCC_ON at time t1, the IC begins to operate with soft-start.
Due to power consumption of the IC and the fact that there is still no energy from the auxiliary winding to
charge the VCC capacitor before the output voltage is built up, the VCC voltage drops (Phase II). Once the output
voltage rises close to regulation, the auxiliary winding starts to charge the VCC capacitor from the time t2 onward
and delivering the IVCC_ Normal2 to the CoolSET™. The VCC then will reach a constant value depending on output
load.

1
IVCC_ Charge1/2/3 is charging current from the controller to VCC capacitor during start up
2
IVCC_ Normal is supply current from VCC capacitor or auxiliary winding to the CoolSET™ during normal operation

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Functional description

3.2 Soft-start
As shown in Figure 6, the IC begins to operate with a soft-start at time ton. The switching stresses on the power
MOSFET, diode and transformer are minimized during soft-start. The soft-start implemented in ICE5ARxxxxBZS
is a digital time-based function. The preset soft-start time is tSS (12 ms) with 4 steps. If not limited by other
functions, the peak voltage on CS pin will increase step by step from 0.3 V to VCS_N (0.8 V) finally. The normal
feedback loop will take over the control when the output voltage reaches its regulated value.

Figure 6 Maximum current sense voltage during soft start

3.3 Normal operation

The PWM controller during normal operation consists of a digital signal processing circuit including regulation
control and an analog circuit including a current measurement unit and a comparator. Details about the full
operation of the CoolSET™ in normal operation are illustrated in the following paragraphs.

3.3.1 PWM operation and peak current mode control

3.3.1.1 Switch-on determination

The power MOSFET turn-on is synchronized with the internal oscillator with a switching frequency fSW that
corresponds to the voltage level VFB (see Figure 8).

3.3.1.2 Switch-off determination

In peak current mode control, the PWM comparator monitors voltage V1 (see Figure 4) which is the
representation of the instantaneous current of the power MOSFET. When V1 exceeds VFB, the PWM comparator
sends a signal to switch off the GATE of the power MOSFET. Therefore, the peak current of the power MOSFET is
controlled by the feedback voltage VFB (see Figure 7).
At switch on transient of the power MOSFET, a voltage spike across RCS can cause V1 to increase and exceed VFB.
To avoid a false switch off, the IC has a blanking time tCS_LEB before detecting the voltage across RCS to mask the
voltage spike. Therefore, the minimum turn on time of the power MOSFET is tCS_LEB.
For some reason that the voltage level at V1 takes long time to exceed VFB, the IC has implemented a maximum
duty cycle control to force the power MOSFET to switch off when DMAX = 0.75 is reached.

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Functional description

Figure 7 Pulse width modulation

3.3.2 Current sense

The power MOSFET current generates a voltage VCS across the current sense resistor RCS connected between the
CS pin and the GND pin. VCS is amplified with gain GPWM, then, added with an offset VPWM to become V1 as
described below in below equation 3.

𝑉CS = 𝐼D × 𝑅CS (2)

𝑉1 = 𝑉CS ∗ 𝐺PWM + 𝑉PWM (3)

where, VCS : CS pin voltage

ID : power MOSFET current
RCS : resistance of the current sense resistor
V1 : voltage level compared to VFB as described in section 3.3.1.2
GPWM : PWM-OP gain
VPWM : offset for voltage ramp
If the voltage at the current sense pin is lower than the preset threshold VCS_STG after the time tCS_STG_SAM for three
consecutive pulses during on-time of the power switch, this abnormal VCS will trigger IC into auto restart mode.

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Functional description

3.3.3 Frequency reduction

Frequency reduction is implemented in ICE5ARxxxxBZS to achieve a better efficiency during the light load. At
light load, the reduced switching frequency FSW improves efficiency by reducing the switching loses.
When load decreases, VFB decreases as well. FSW is dependent on the VFB as shown in Figure 8. Therefore, FSW
decreases as the load decreases.
Typically, FSW at high load is 100 kHz kHz and starts to decrease at VFB = 1.7V. There is no further frequency
reduction once it reached the fOSC4_MIN even the load is further reduced.

fSW(VFB) VCS (VFB)

Vcs
VCS_N
0.80 V

fOSC4 Fsw
100 kHz

fOSC4_ABM BM
83 kHz

fOSC4_MIN No B M
43 kHz
BM VCS_BHP / VCS_BLP
0.27 V /0.22 V

No B M

VFB
VFB_EBxP VFB_OLP
0.5 V 0.93 / 1.03 V 1.35 V 1.7 V 2.73 V
Figure 8 Frequency reduction curve

3.3.4 Slope compensation

ICE5ARxxxxBZS can operate at Continuous Conduction Mode (CCM). At CCM operation, duty cycle greater than
50% may generate a sub-harmonic oscillation. To avoid the sub-harmonic oscillation, slope compensation is
added to VCS pin when the gate of the power MOSFET is turned on for more than 40% of the switching cycle
period. The relationship between VFB and the VCS for CCM operation is described in below equation 4:

𝑉FB = 𝑉CS ∗ 𝐺PWM + 𝑉PWM + 𝑀COMP ∗ (𝑇ON − 40% ∗ 𝑇PERIOD ) (4)

where, TON : gate turn on time of the power MOSFET

MCOMP : slope compensation rate
TPERIOD : switching cycle period
Slope compensation circuit is disabled and no slope compensation is added into the VCS pin during active burst
mode to save the power consumption.

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Functional description

3.3.5 Oscillator and frequency jittering

The oscillator generates a frequency of 100 kHz with frequency jittering of ±4% at a jittering period of TJITTER (4
ms). The frequency jittering helps to reduce conducted EMI.
A capacitor, a current source and current sink which determine the frequency are integrated. The charging and
discharging current of the implemented oscillator capacitor are internally trimmed in order to achieve a highly
accurate switching frequency.
Once the soft-start period is over and when the IC goes into normal operating mode, the frequency jittering is
enabled. There is also frequency jittering during frequency reduction.

3.3.6 Modulated gate drive

The drive-stage is optimized for EMI consideration. The switch on speed is slowed down before it reaches the
CoolMOS™ turn on threshold. That is a slope control of the rising edge at the output of driver (see Figure 9).
Thus the leading switch spike during turn on is minimized.

Figure 9 Gate rising waveform

3.4 Peak current limitation

There is a cycle by cycle peak current limitation realized by the current limit comparator to provide primary
over-current protection. The primary current generates a voltage VCS across the current sense resistor RCS
connected between the CS pin and the GND pin. If the voltage VCS exceeds an internal voltage limit VCS_N, the
comparator immediately turns off the gate drive.
The primary peak current IPEAK_PRI can be calculated as below:

𝐼PEAK_PRI = 𝑉CS_N⁄𝑅CS (5)

To avoid mistriggering caused by MOSFET switch on transient voltage spikes, a leading edge blanking time
(tCS_LEB) is integrated in the current sensing path.

3.4.1 Propagation delay compensation

In case of overcurrent detection, there is always a propagation delay from sensing the VCS to switching the
power MOSFET off. An overshoot on the peak current Ipeak caused by the delay depends on the ratio of dI/dt of
the primary current (see Figure 10).

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Functional description

Figure 10 Current limiting

The overshoot of Signal2 is larger than Signal1 due to the steeper rising waveform. This change in the slope is
depending on the AC input voltage. Propagation delay compensation is integrated to reduce the overshoot due
to dI/dt of the rising primary current. Thus the propagation delay time between exceeding the current sense
threshold VCS_N and the switching off of the power MOSFET is compensated over wide bus voltage range.
Current limiting becomes more accurate which will result in a minimum difference of overload protection
triggering power between low and high AC line input voltage.
Under CCM operation, the same VCS do not result in the same power. In order to achieve a close overload
triggering level for CCM, ICE5ARxxxxBZS has implemented a 2 compensation curve as shown Figure 11. One of
the curve is used for TON greater than 0.40 duty cycle and the other is for lower than 0.40 duty cycle.

Figure 11 Dynamic voltage threshold VCS_N

Similarly, the same concept of propagation delay compensation is also implemented in ABM with reduced
level. With this implementation, the entry and exit burst mode power can be close between low and high AC
line input voltage.

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Functional description

3.5 Active Burst Mode (ABM) with selectable power level

At light load condition, the IC enters ABM operation to minimize the power consumption. Details about ABM
operation are explained in the following paragraphs.

3.5.1 Entering ABM operation

The sytem will enter into ABM operation when two conditions below are met:
 the FB voltage is lower than the threshold of VFB_EBLP/VFB_EBHP depending on burst configuration option setup
 and a certain blanking time tFB_BEB

Once all of these conditions are fulfilled, the ABM flip-flop is set and the controller enters ABM operation. This
multi-condition determination for entering ABM operation prevents mis-triggering of entering ABM operation,
so that the controller enters ABM operation only when the output power is really low.

3.5.2 During ABM operation

After entering ABM, the PWM section will be inactive making the VOUT start todecrease. As the VOUT decreases, VFB
rises. Once VFB exceeded VFB_BOn, the internal circuit is again activated by the internal bias to start with the
switching.
If the PWM is still operating and the output load is still low, VOUT increases and VFB signal starts to decrease.
When VFB reaches the low threshold VFB_BOff, the internal bias is reset again and the PWM section is disabled with
no switching until VFB increases back to exceed VFB_BOn threshold.
In ABM, VFB is like a sawtooth waveform swinging between VFB_BOff and VFB_BOn shown in Figure 12.
During ABM, the switching frequency fOSC4_ABM is 83 kHz. The peak current IPEAK_ABMof the power MOSFET is defined
by:

𝐼PEAK_ABM = 𝑉CS_BxP⁄𝑅CS (6)

where VCS_BxP is the peak current limitation in ABM

3.5.3 Leaving ABM operation

The FB voltage immediately increases if there is a sudden increase in the output load. When VFB exceeds VFB_LB, it
will leave ABM and the peak current limitation trhreshold voltage will return back to VCS_N immediately.

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Functional description

VFB
Entering Active Burst Mode Leaving Active Burst Mode
VFB_LB
VFB_BOn
VFB_BOff

VFB_EBHP/VFB_EBLP

Blanking Window (tFB_BEB) t

VCS

VCS_N
Current limit level during Active Burst Mode

VCS_BHP/VCS_BLP

t
VVCC

VVCC_off

t
VO
Max. Ripple < 1%

t
Burst Mode Operation

Figure 12 Signals in Active Burst Mode

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Functional description

3.5.4 ABM configuration

The burst mode entry level can be selected by changing the different resistance RSel at FB pin. There are 3
configuration options depending on RSel which corresponds to the options of no ABM (Option 1), low range of
ABM power (Option 2) and high range of ABM power (Option 3). The table below shows the control logic for the
entry and exit level with the FB voltage.

Table 3 ABM configuration option setup

Entry level Exit level
Option RSel VFB VCS_BxP
VFB_EBxP VFB_LB
1 <470 kΩ VFB < VFB_P_BIAS1 - No ABM No ABM
2 720 kΩ ~ 790 kΩ VFB_P_BIAS1<VFB<VFB_P_BIAS2 0.22V 0.93 V 2.73 V
3(Default) >1210 kΩ VFB > VFB_P_BIAS2 0.27V 1.03 V 2.73 V

During IC first startup, the controller preset the ABM selection to Option 3, the FB resistor (RFB) is turned off by
internal switch S2 (see Figure 13)and a current source Isel is turned on instead.From VCC= 4.44 V to VCC on
threshold, the FB pin will start to charge resistor RSel with current ISel to a certain voltage level. When VCC reaches
VCC on threshold, the FB voltage is sensed. The burst mode option is then chosen according to the FB voltage
level. After finishing the selection, any change on the FB level will not change the burst mode option and the
current source (Isel) is turned off while the FB resistor (RFB) is connected back to the circuit (Figure 13).

Figure 13 ABM detect and adjust

3.6 Non-isolated/isolated configuration

ICE5ARxxxxBZS has a VERR Pin, which is connected to the input of an integrated error amplifier to support non-
isolated flyback application (see Figure 2). When VCC is charging and before reaching the VCC on threshold, a
current source IERR_P_BIAS from VERR pin together with RF1 and RF2 will generate a voltage across it. If VERR voltage
is more than VERR_P_BIAS (0.2 V), non-isolated configuration is selected, otherwise, isolated configuration is
selected. In isolated configuration, the error amplifier output is disconnected from the FB pin.
In case of non-isolated configuration, the voltage divider RF1 and RF2 is used to sense the output voltage and
compared with the internal reference voltage VERR_REF. The difference between the sensed voltage and the
reference voltage is converted as an output current by the error amplifier. The output current will
charge/discharge the resistor and capacitor network connected at the FB pin for the loop compensation.

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Functional description

3.7 Protection functions

The ICE5ARxxxxBZS provides numerous protection functions which considerably improve the power supply
system robustness, safety and reliability. The following table summarizes these protection functions and the
corresponding protection mode whether as a non switch auto restart, auto restart or odd skip auto restart
mode. Refer to Figure 14, Figure 15 and Figure 16 for the waveform illustration of protection modes.

Table 4 Protection functions

Protection Functions Normal Mode Burst Mode Protection Mode
Burst ON Burst OFF
VCC over voltage √ √ NA1 Odd skip auto restart
VCC under voltage √ √ √ Auto restart
Overload/ open loop √ NA1 NA1 Odd skip auto restart
Over temperature √ √ √ Non switch auto restart
VCC short to GND √ √ √ No startup

3.7.1 VCC over/under voltage

During operation, the VCC voltage is continuously monitored. If VCC is either below VVCC_OFF for 50 µs (tVCC_OFF_B) or
above VVCC_OVP for 55 µs (tVCC_OVP_B), the power MOSFET is kept switch off. After the VCC voltage falls below the
threshold VVCCoff, the new start up sequence is activated. The VCC capacitor is then charged up. Once the voltage
exceeds the threshold VVCC_ON, the IC begins to operate with a new soft-start.

3.7.2 Overload/ open loop

In case of open control loop or output overload, the FB voltage will be pulled up. When VFB exceeds VFB_OLP after
a blanking time of tFB_OLP_B, the IC enters odd skip auto restart mode. The blanking time enables the converter to
provide a peak power in case the increase in VFB is due to a sudden load increase.

3.7.3 Over temperature

If the junction temperature of controller exceeds Tjcon_OTP, the IC enters into Over Temperature Protection (OTP)
auto restart mode. The IC has also implemented with a 40 °C hysteresis. That means the IC can only be recovered
from OTP when the controller junction temperature is dropped 40 °C lower than the over temperature trigger
point.

3.7.4 VCC short to GND

To limit the power dissipation of the startup circuit at VCC short to GND condition, the VCC charging current is
limited to a minimum level of IVCC_ Charge1. With such low current, the power loss of the IC is limited to prevent
overheating.

3.7.5 Protection modes

All the protections are in auto restart mode with a new soft start sequence. The three auto restart modes are
illustrated in the following figures.

1
Not Applicable

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Functional description

Fault Fault released

detected

Switching start at the

Start up and detect at
VVCC every charging cycle
following restartt cycle

VCC_ON

VCC_OFF

VCS t
No switching

Figure 14 Non switch auto restart mode

Fault Fault released

detected

Start up and detect at every

charging cycle Switching start at the
VVCC t cycle
following restart

VCC_ON

VCC_OFF

VCS t

Figure 15 Auto restart mode

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Functional description

Fault Fault released

detected

Start up and detect at

every even charging
cycle Switching start at the
VVCC following event restart
No detect No detect cycle

VCC_ON

VCC_OFF

VCS t

Figure 16 Odd skip auto restart

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Electrical characteristics

4 Electrical characteristics
Attention: All voltages are measured with respect to ground (Pin 8). The voltage levels are valid if other
ratings are not violated.

4.1 Absolute maximum ratings

Attention: Stresses above the maximum values listed here may cause permanent damage to the device.
Exposure to absolute maximum rating conditions for extended periods may affect device
reliability. Maximum ratings are absolute ratings; exceeding any one of these values may
cause irreversible damage to the integrated circuit. For the same reason, make sure that any
capacitor that will be connected to pin 7 (VCC) is discharged before assembling the
application circuit. Ta=25 °C unless otherwise specified.

Table 5 Absolute maximum ratings

Parameter Symbol Limit Values Unit Note / Test Condition
Min. Max.
Drain Voltage VDRAIN V Tj = 25 °C
ICE5ARxx70BZS - 700
ICE5ARxx80BZS - 800
Pulse drain current ID,Pulse A
ICE5AR4770BZS - 2.21

ICE5AR4780BZS - 2.61
ICE5AR0680BZS - 5.82
Avalanche energy, repetitive, tAR limited EAR mJ
by max. TJ=150 °C and TJ,Start = 25 °C
ICE5AR4770BZS - 0.02 ID=0.14 A, VDD=50 V
ICE5AR4780BZS - 0.02 ID=0.20 A, VDD=50 V
ICE5AR0680BZS - 0.22 ID=1.80 A, VDD=50 V
Avalanche current, repetitive,tAR limited IAR A
by max. TJ=150 °C and TJ,Start = 25 °C
ICE5AR4770BZS - 0.14
ICE5AR4780BZS - 0.20
ICE5AR0680BZS - 1.80
VCC Supply Voltage VCC -0.3 27.0 V
GATE Voltage VGATE -0.3 27.0 V
FB Voltage VFB -0.3 3.6 V
VERR Voltage VERR -0.3 3.6 V
CS Voltage VCS -0.3 3.6 V
Maximum DC current on any pin -10.0 10.0 mA Except DRAIN and CS pin

1
Pulse width tP limited by Tj,max
2
Pulse width tP = 20 µs and limited by Tj,max

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Electrical characteristics

ESD robustness HBM VESD_HBM - 2000 V According to EIA/JESD22

ESD robustness CDM VESD_CDM - 500 V
Junction temperature range TJ -40 150 °C Controller & CoolMOS
Storage Temperature TSTORE -55 150 °C
Thermal Resistance (Junction- Ambient) RthJA K/W Setup according to the JEDEC
ICE5AR4770BZS - 106 standard JESD51 and using
ICE5AR4780BZS - 107 minimum drain pin copper
area in a 2 oz copper single
ICE5AR0680BZS - 100
sided PCB

4.2 Operating range

Note: Within the operating range, the IC operates as described in the functional description.

Table 6 Operating range

Parameter Symbol Limit Values Unit Remark
Min. Max.
VCC Supply Voltage VVCC VVCC_OFF VVCC_OVP
Junction Temperature of TjCon_op -40 TjCon_OTP ˚C Max value limited due to OTP
controller of controller chip
Junction Temperature of CoolMOS TjCoolMOS_op -40 150 ˚C

4.3 Operating conditions

Note: The electrical characteristics involve the spread of values within the specified supply voltage and
junction temperature range TJ from – 40 °C to 125 °C. Typical values represent the median values,
which are related to 25 °C. If not otherwise stated, a supply voltage of VCC = 18 V is assumed.

Table 7 Operating conditions

Parameter Symbol Limit Values Unit Note / Test Condition
Min. Typ. Max.
VCC Charge Current IVCC_Charge1 -0.35 -0.20 -0.09 mA VVCC=0 V, RStartUp=50 MΩ and
VDRAIN=90 V
IVCC_Charge2 - -3.2 - mA VVCC=3 V, RStartUp=50 MΩ and
VDRAIN=90 V
IVCC_Charge3 -5 -3 -1 mA VVCC=15 V, RStartUp=50 MΩ
and VDRAIN=90 V
Current Consumption, Startup Current IVCC_Startup - 0.25 - mA VVCC=15 V
Current Consumption, Normal IVCC_Normal - 0.9 - mA IFB=0 A (No gate switching)
Current Consumption, Auto Restart IVCC_AR - 410 - µA
Current Consumption, Burst Mode – IVCC_Burst - 0.54 - mA
Isolated Mode_ISO

Current Consumption, Burst Mode – IVCC_Burst - 0.61 - mA

Non-Isolated Mode_NISO

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Electrical characteristics

VCC Turn-on Threshold Voltage VVCC_ON 15.3 16.0 16.5 V

VCC Turn-off Threshold Voltage VVCC_OFF 9.4 10.0 10.4 V
VCC Short Circuit Protection VVCC_SCP - 1.1 1.9 V
VCC Turn-off blanking tVCC_OFF_B - 50 - µs

4.4 Internal voltage reference

Table 8 Internal voltage reference
Parameter Symbol Limit Values Unit Note / Test Condition
Min. Typ. Max.
Internal Reference Voltage VREF 3.20 3.30 3.39 V Measured at pin FB IFB=0 A

4.5 PWM section

Table 9 PWM section
Parameter Symbol Limit Values Unit Note / Test
Min. Typ. Max. Condition
Fixed Oscillator Frequency – fOSC3 92 100 108 kHz
100 kHz fOSC4 94 100 106 kHz Tj = 25 °C
Fixed Oscillator Frequency – fOSC4_ABM 71 83 94 kHz Tj = 25 °C
100 kHz (Active Burst Mode)
Fixed Oscillator Frequency – fOSC4_MIN 36 43 51 kHz Tj = 25 °C
100 kHz (Minimum Fsw)
Frequency Jittering Range FJITTER - +/- 4 - % Tj = 25 °C
Frequency Jittering period TJITTER - 4 - ms Tj = 25 °C
Maximum Duty Cycle DMAX 70 75 80 %
Feedback Pull-Up Resistor RFB 11 15 20 kΩ
PWM-OP Gain GPWM 1.91 2.03 2.16
Offset for Voltage Ramp VPWM 0.42 0.50 0.58 V

Slope Compensation rate - MCOMP 41 50 58 mV/μs Vcs=0 V

100 kHz

4.6 Error amplifier

Table 10 Error amplifier
Parameter Symbol Values Unit Note / Test
Min. Typ. Max. Condition
Transconductance GERR_M 2.14 2.80 3.44 mA/V
Transconductance – Burst Mode GERR_BM 6.9 9.2 11.6 mA/V
Error Amplifier Source Current IERR_SOURCE 85 150 223 μA
Error Amplifier Sink Current IERR_SINK 85 150 223 μA
Error Amplifier Reference Voltage VERR_REF 1.76 1.80 1.84 V

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Electrical characteristics

Error Amplifier Output Dynamic VERR_DYN 0.05 - 3.15 V

Range of Transconductance
Error Amplifier Mode Bias Current IERR_P_BIAS 9.5 14.0 18.5 μA
Error Amplifier Mode Threshold VERR_P_BIAS 0.16 0.20 0.24 V

4.7 Current sense

Table 11 Current sense
Parameter Symbol Limit Values Unit Note / Test Condition
Min. Typ. Max.
Peak current limitation in normal VCS_N 0.72 0.80 0.88 V dvsense/dt = 0.41V/ μ s
operation
Peak current limitation in normal VCS_N15 0.74 0.79 0.84 V
operation, 15% of TON
Leading Edge Blanking time tCS_LEB 70 220 365 ns
Peak Current Limitation in Active VCS_BHP 0.23 0.27 0.31 V
Burst Mode - High Power
Peak Current Limitation in Active VCS_BLP 0.18 0.22 0.26 V
Burst Mode - Low Power
VCS_STG 0.06 0.10 0.15 V
Abnormal CS voltage threshold

Abnormal CS voltage PCS_STG - 3 - cycle

Consecutive Trigger
Abnormal CS voltage Sample tCS_STG_SAM tPERIOD * tPERIOD * tPERIOD * µs
period 0.36 0.4 0.44

4.8 Soft start

Table 12 Soft start
Parameter Symbol Limit Values Unit Note / Test Condition
Min. Typ. Max.
Soft-Start time tSS 7.3 12.0 - ms
Soft-start time step tSS_S 1
- 3 - ms
CS peak voltage at first step of soft VSS11 - 0.30 - V CS peak voltage
start
Step increment of CS peak voltage VSS_S1 - 0.15 - V CS peak voltage
in soft start

4.9 Active Burst Mode

Table 13 Active Burst Mode
Parameter Symbol Limit Values Unit Note / Test Condition
Min. Typ. Max.

1
The parameter is not subjected to production test - verified by design/characterization

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Electrical characteristics

Charging current to select burst Isel 2.5 3.0 3.5 µA

mode
Burst mode selection reference VFB_P_BIAS1 1.65 1.73 1.80 V
voltage Threshold
Burst mode selection reference VFB_P_BIAS2 2.76 2.89 3.01 V
voltage Threshold
Feedback voltage for entering VFB_EBHP 0.98 1.03 1.08 V
ABM for high power
Feedback voltage for entering VFB_EBLP 0.88 0.93 0.98 V
ABM for low power
Blanking time for entering tFB_BEB - 36 - ms
Active Burst Mode
Feedback voltage for leaving VFB_LB 2.63 2.73 2.83 V
Active Burst Mode
Feedback voltage for burst-on VFB_Bon_ISO 2.26 2.35 2.45 V
– Isolated Case
Feedback voltage for burst-off VFB_BOff_ISO 1.88 2.00 2.05 V
– Isolated Case
Feedback voltage for burst-on VFB_Bon_NISO 1.88 1.95 2.05 V
– Non-Isolated Case
Feedback voltage for burst-off VFB_BOff_NISO 1.50 1.55 1.64 V
– Non-Isolated Case

4.10 VCC over voltage protection

Table 14 VCC over voltage protection
Parameter Symbol Limit Values Unit Note / Test Condition
Min. Typ. Max.
VCC Over Voltage threshold VVCC_OVP 24.0 25.5 27.0 V
VCC Over Voltage blanking tVCC_OVP_B - 55 - µs

4.11 Overload protection

Table 15 Overload protection
Parameter Symbol Limit Values Unit Note / Test Condition
Min. Typ. Max.
Over Load Detection threshold for VFB_OLP 2.63 2.73 2.83 V
OLP protection at FB pin
Over Load Protection Blanking Time tFB_OLP_B 30 54 - ms

4.12 Thermal protection

Table 16 Thermal protection
Parameter Symbol Limit Values Unit Note / Test Condition
Min. Typ. Max.

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Electrical characteristics

Over temperature protection Tjcon_OTP1 129 140 150 °C Junction temperature of

the controller chip (not the
Over temperature Hysteresis TjHYS_OTP - 40 - °C
CoolMOS™ chip)
Over temperature Blanking Time Tjcon_OTP_B - 50 - µs

4.13 CoolMOS™ section

Table 17 ICE5ARxxxxBZS
Parameter Symbol Limit Values Unit Note / Test
Min. Typ. Max. Condition
Drain Source Breakdown Voltage V(BR)DSS V Tj = 25°C
ICE5ARxx70BZS 700 - -
ICE5ARxx80BZS 800 - -
Drain Source On-Resistance (inclusive of low RDSon Ω
side MOSFET)
ICE5AR4770BZS - 4.73 5.18 Tj = 25°C
- 8.732 - Tj=125°C at ID =0.4A
ICE5AR4780BZS - 4.13 4.85 Tj = 25°C
- 8.691 - Tj=125°C at ID =0.4A
ICE5AR0680BZS - 0.71 0.80 Tj = 25°C
- 1.271 - Tj=125°C at ID =2A

Effective output capacitance, energy related1 Co(er) pF

ICE5AR4770BZS - 3.4 - VGS=0V, VDS=0~480V
ICE5AR4780BZS - 3 - VGS=0V, VDS=0~500V
ICE5AR0680BZS - 24 - VGS=0V, VDS=0~500V

Rise Time trise3 - 30 - ns

Fall Time tfall2 - 30 - ns

1
The parameter is not subjected to production test - verified by design/characterization
2
The parameter is not subjected to production test - verified by design/characterization
3
Measured in a typical flyback converter application

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CoolMOS™ performance characteristics

5 CoolMOS™ performance characteristics

Figure 17 Safe Operating Area (SOA) curve for ICE5AR4770BZS

Figure 18 Safe Operating Area (SOA) curve for ICE5AR4780BZS

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CoolMOS™ performance characteristics

Figure 19 Safe Operating Area (SOA) curve for ICE5AR0680BZS

Figure 20 Power dissipation of ICE5AR4770BZS; Ptot=f(Ta), (Maximum ratings as given in section 4.1
must not be exceeded)

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CoolMOS™ performance characteristics

Figure 21 Power dissipation of ICE5AR4780BZS; Ptot=f(Ta), (Maximum ratings as given in section 4.1
must not be exceeded)

Figure 22 Power dissipation of ICE5AR0680BZS; Ptot=f(Ta), (Maximum ratings as given in section 4.1
must not be exceeded)

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CoolMOS™ performance characteristics

Figure 23 Drain-source breakdown voltage ICE5ARxx70BZS; VBR(DSS)=f(TJ), ID=1 mA

Figure 24 Drain-source breakdown voltage ICE5ARxx80BZS; VBR(DSS)=f(TJ), ID=1 mA

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CoolMOS™ performance characteristics

Figure 25 Typical CoolMOS™ capacitances of ICE5AR4770BZS (C=f(VDS);VGS=0 V; f=1 MHz)

Figure 26 Typical CoolMOS™ capacitances of ICE5AR4780BZS (C=f(VDS);VGS=0 V; f=250 kHz)

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CoolMOS™ performance characteristics

Figure 27 Typical CoolMOS™ capacitances of ICE5AR0680BZS (C=f(VDS);VGS=0 V; f=250 kHz)

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Output power curve

6 Output power curve

The calculated output power curves versus ambient temperature are shown below. The curves are derived
based on a typical DCM/CCM flyback in an open frame design setting the maximum TJ of the integrated
CoolMOS™ at 125 °C, using minimum drain pin copper area in a 2 oz copper single sided PCB and steady state
operation only (no design margins for abnormal operation modes are included).
The output power figure is for selection purpose only. The actual power can vary depending on a particular
design. In a power supply system, appropriate thermal design margins must be considered to make sure that
the operation of the device is within the maximum ratings given in section 4.1.

Figure 28 Output power curve of ICE5AR4770BZS

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Output power curve

Figure 29 Output power curve of ICE5AR4780BZS

Figure 30 Output power curve of ICE5AR0680BZS

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Outline dimension

7 Outline dimension

Figure 31 PG-DIP-7

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Marking

8 Marking

Figure 32 Marking of PG-DIP-7

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Revision history

Revision history
Document Date of release Description of changes
version
V 2.0 21 Nov 2017 First release
V 2.1 27 Feb 2018 Page 1
Product validation text content revised
V 2.2 2 Oct 2019 Page 34
Update marking with reference to PCN 2019-142-A
V 2.3 3 Feb 2020 Update of CS pin function and description
(refer to errata sheet ES_2001_PL83_2002_024629)

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