M. S. P.

Mandal’s
Deogiri Institute of Engineering and Management Studies, Chhatrapati
Sambhajinagar
Approved by AICTE, Recognized by Govt. of Maharashtra and Affiliated to Dr. B. A. T. University Lonere
(M.S.)
Accredited 'A' Grade by NAAC and NBA

Department of Electronics and Telecommunication

Engineering
Second Year of Engineering
A.Y. 2024-2025
Semester-III

Digital Electronics
Laboratory Manual
BTETL306

Prepared By
Prof. S. A. Karmude
Assistant Professor
Department of Electronics and Telecommunication Engineering
Deogiri Institute of Engineering and Management Studies, Chhatrapati
Sambhajinagar
DEPARTMENT OF ELECTRONICS AND TELECOMMUNICATION ENGINEERING

VISION OF THE DEPARTMENT

“To provide valuable resources for Industry and Society through research and
excellence in Electronics and Telecommunication Engineering.”

MISSION OF THE DEPARTMENT

I. Educating students with requisite technical expertise to meet the growing
challenges of the industry.
II. Promoting research through constant interaction with research bodies and
various Industries.
III. Equipping students with fundamental subject knowledge to enable them for
continuing Education.

PROGRAM EDUCATIONAL OBJECTIVES (PEOs)

PEO1: Graduates would be able to provide the Engineering solution with strong
research capabilities in the areas of Electronics and Telecommunication
Engineering
PEO2: Graduates would be able to achieve good career using improved skill sets.
PEO3: Graduates would be able to provide a solid foundation and advanced
programming skill in the field of Electronics.

PROGRAM SPECIFIC OUTCOMES (PSOs)

PSO1: Apply knowledge to use modern tools and techniques for Electronics and
Telecommunication Engineering
PSO2: Identify, Design, and Test Analog, Digital Communication Systems and
Signal Processing using software and hardware tools.
PSO3: Design and develop computing systems while using best practices for
software and hardware implementations.
PSO4: Create social and professional skills awareness for lifelong learning.
 Lab Manual / Semester 3th
Electronics and Telecommunication Engineering Department, DIEMS, Chh. Sambhajinagar

Lab Overview

Year / Semester 2rd Year /3rd Semester Academic Year 2024-2025

Laboratory Title Signal and Systems Laboratory Laboratory Code BTETL306
Total Credits 02 Hours per Week 2 Hours
CA Marks 30M ESE Marks 20M

Lab Objectives

• To know the concepts of Combinational circuits. 

• To understand the concepts of flipflops, registers and counters
• To help the students in developing hardware and software skills using VHDL

Lab Course Outcomes

• The student, after successful completion of the course, will be able to Analyze basics of gates, to construct
combinational and sequencial circuits.

Prerequisites
• Basic Electrical & Electronics Engineering practices Lab

Base Course
• Digital electronics

Resources Required
• Breadboard, Digital IC’s.
• Xilinx software or edaplayground.com online simulator for VHDL code.

Reference Material
• R.P. Jain, ―Modern digital electronics‖, 3rd edition, 12threprint Tata McGraw Hill
• Publication,2007.
• 2. M. Morris Mano, ―Digital Logic and Computer Design‖ 4th edition, Prentice Hall of
• India,2013.
• 3. Anand Kumar, ―Fundamentals of digital circuits‖ 1st edition, Prentice Hall of India,
• 2001.
• 4. Pedroni V.A., “Digital Circuit Design with VHDL”, Prentice Hall India, 2nd 2001
• Edition.

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 Lab Manual / Semester 3th
Electronics and Telecommunication Engineering Department, DIEMS, Chh. Sambhajinagar

PROGRAM OUTCOMES (POs)

PO1 Engineering knowledge: Apply the knowledge of mathematics, science, engineering

fundamentals, and an engineering specialization to the solution of complex engineering
problems.

PO2 Problem analysis: Identify, formulate, review research literature, and analyze complex
engineering problems reaching substantiated conclusions using first principles of
mathematics, natural sciences, and engineering sciences.
PO3 Design/development of solutions: Design solutions for complex engineering problems and
design system components or processes that meet the specified needs with appropriate
consideration for the public health and safety, and the cultural, societal, and environmental
considerations
PO4 Design/development of solutions: Design solutions for complex engineering problems and
design system components or processes that meet the specified needs with appropriate
consideration for the public health and safety, and the cultural, societal, and environmental
considerations
PO5 Modern tool usage: Create, select, and apply appropriate techniques, resources, and
modern engineering and IT tools including prediction and modeling to complex
engineering activities with an understanding of the limitations.
PO6 The engineer and society: Apply reasoning informed by the contextual knowledge to
assess societal, health, safety, legal and cultural issues and the consequent responsibilities
relevant to the professional engineering practice.
PO7 Environment and sustainability: Understand the impact of the professional engineering
solutions in societal and environmental contexts, and demonstrate the knowledge of, and
need for sustainable development.
PO8 Ethics: Apply ethical principles and commit to professional ethics and responsibilities and
norms of the engineering practice.
PO9 Individual and team work: Function effectively as an individual, and as a member or
leader in diverse teams, and in multidisciplinary settings.
PO10 Communication: Communicate effectively on complex engineering activities with the
engineering community and with society at large, such as, being able to comprehend and
write effective reports and design documentation, make effective presentations, and give
and receive clear instructions.
PO11 Project management and finance: Demonstrate knowledge and understanding of the
engineering and management principles and apply these to one’s own work, as a member
and leader in a team, to manage projects and in multidisciplinary environments.
PO12 Life-long learning: Recognize the need for, and have the preparation and ability to engage
in independent and lifelong learning in the broadest context of technological change.

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 Lab Manual / Semester 3th
Electronics and Telecommunication Engineering Department, DIEMS, Chh. Sambhajinagar

MARATHWADA SHIKSHAN PRASARK MANDAL’S

DEOGIRI INSTITUTE OF ENGINEERING AND MANAGEMENT STUDIES,
CHH. SAMBHAJINAGAR
DEPARTMENT OF ELECTRONICS AND TELECOMMUNICATION
PRACTICAL EXPERIMENT INTRUCTION SHEET
CLASS: LAB:
SY(E&TC)
SUBJECT: SIGNALS & SYSTEMS
SEMESTER: VERSION:
2024-25 SEM-I

List of Experiments

Page
Sr. No Title of Experiment No.

1 To study & perform Logic Gates 2

2 To study & perform Half Adder and Full Adder 4

3 To study and perform Half Subtractor and Full Subtractor 6

4 To study & perform binary-to-gray and gray-to-binary code conversion 8

5 To study & perform Multiplexer. 10

6 To study & perform Demultiplexer 12

7 To study & perform Flip-flops 14

8 To study VHDL and simulate the same using software 16

Prepared by: Mr. S. A. Karmude Approved by: Head, Dept. of E&TC

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 Lab Manual / Semester 3th
Electronics and Telecommunication Engineering Department, DIEMS, Chh. Sambhajinagar

EXPERIMENT NO 1
Aim: To study & perform Logic Gates
Component Required:-

PROCEDURE: -
 Place the IC on breadboard.
 Make circuit connection as per diagram
 Connect Vcc and Ground to respective pins on breadboard
 Connect the outputs to the LEDs
 Apply all the possible combinations of inputs according to truth table and observe
conditions on LEDs
Theory:
An electronic computer is a system which processes and stores very large amounts of data and
which solves scientific problem of numerical calculations of high complexity with tremendous
speed. The digital computer consists of logic circuits. These logic circuits are tiny electronic
devices, which work according to certain rules in conformity with Boolean or switching algebra.
A building is made from bricks and Mortar. Similarly a digital computer is made from "Logic
Circuits” which are bricks and "connecting wires" which acts as a mortar. These logic
circuits or gates can be interconnected to construct a variety of computer configurations depending
upon the service required. These logic circuits are not only essential for computer operation but they
have practically unlimited field of applications. Logic gates are the basic building blocks in digital
electronics. They are classified as follows.
OR GATE: -
The OR gate has two or more input signals but only one output signal. If any input signal is high,
the output is high.

NOR GATES: -
The NOR gate has two or more input signals but only one output signal. All inputs must be low to
get a high output. In other words, the NOR gate recognizes only the input word whose bits are all
zeros. NOR gate are OR gates followed by an NOT gate (inverter).

NAND GATE: -
The NAND gate has two or more input signals but only one output signal. All input signal must be
high to get a low output. It is an AND gate followed by an NOT gate (inverter). Therefore final
output is NOT - AND gate. The circuit is now referred to as NAND gate. If one or more inputs are
low the result of the anding is low; therefore, the final inverted output is high.

EX-OR GATES: -
An OR gate recognizes words with one or more 1s. The Exclusive OR gate is different. It
recognizes only words that have an odd number of 1s. For two input EX-OR gate, the output is high
when one or the other input is high but not both. This is why the circuit is known as an Exclusive
OR gate. In other words, the output is 1 only when the inputs are different.

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Electronics and Telecommunication Engineering Department, DIEMS, Chh. Sambhajinagar

NOTE: -
1] LED ON indicates LOGIC 1 while LED OFF indicates LOGIC 0.
2] Circuit uses a TTL IC and hence any input if left open will assume a high logic level input and
only when shorted with ground will assume a low logic level input.

Conclusion:

EXPERIMENT NO 2
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 Lab Manual / Semester 3th
Electronics and Telecommunication Engineering Department, DIEMS, Chh. Sambhajinagar

Aim: To study & perform Half Adder and Full Adder

PROCEDURE: -
 Place the IC on breadboard.
 Make circuit connection as per diagram
 Connect Vcc and Ground to respective pins on breadboard
 Connect the outputs to the LEDs
 Apply all the possible combinations of inputs according to truth table and observe
conditions on LEDs

Theory:

1)Half Adder Truth Table

If we assume A and B as the two bits whose addition is to be performed, a truth table for half adder
with A, B as inputs and Sum, Carry as outputs can be tabulated as follows.

The sum output of the binary addition carried out above is similar to that of an Ex-OR operation
while the carry output is similar to that of an AND operation. The same can be verified with help of
Karnaugh Map.

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Electronics and Telecommunication Engineering Department, DIEMS, Chh. Sambhajinagar

The truth table and K Map simplification for sum output is shown below.

Sum = A B' + A' B

The truth table and K Map simplification for carry is shown below.

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Electronics and Telecommunication Engineering Department, DIEMS, Chh. Sambhajinagar

Carry = AB

If A and B are binary inputs to the half adder, then the logic function to calculate sum S is Ex – OR
of A and B and logic function to calculate carry C is AND of A and B. Combining these two, the
logical circuit to implement the combinational circuit of half adder is shown below.

Half Adder Logic Diagram

As we know that NAND and NOR are called universal gates as any logic system can be
implemented using these two, the half adder circuit can also be implemented using them. We know
that a half adder circuit has one Ex – OR gate and one AND gate.

Half Adder using NAND gates

Five NAND gates are required in order to design a half adder. The circuit to realize half adder using
NAND gates is shown below.

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Electronics and Telecommunication Engineering Department, DIEMS, Chh. Sambhajinagar

Realization of half adder using NAND gates

Half Adder using NOR gates

Five NOR gates are required in order to design a half adder. The circuit to realize half adder using
NOR gates is shown below.

Realization of half adder using NOR Gates

2)Full Adder

Full adder is a digital circuit used to calculate the sum of three binary bits which is the main
difference between full adder and half adder. Full adders are complex and difficult to implement
when compared to half adders. Two of the three bits are same as before which are A, the augend bit
and B, the addend bit. The additional third bit is carry bit from the previous stage and is called
'Carry' – in generally represented by CIN. It calculates the sum of three bits along with the carry.
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Electronics and Telecommunication Engineering Department, DIEMS, Chh. Sambhajinagar

The output carry is called Carry – out and is represented by COUT.

The block diagram of a full adder with A, B and CIN as inputs and S, COUT as outputs is shown
below.

Full Adder Block Diagram and Truth Table

Based on the truth table, the Boolean functions for Sum (S) and Carry – out (COUT) can be derived using K
– Map.

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 Lab Manual / Semester 3th
Electronics and Telecommunication Engineering Department, DIEMS, Chh. Sambhajinagar

The simplified equation for sum is S = A'B'Cin + A'BCin' + ABCin

The simplified equation for COUT is COUT = AB + ACIN + BCIN
In order to implement a combinational circuit for full adder, it is clear from the equations derived above, that
we need four 3-input AND gates and one 4-input OR gates for Sum and three 2-input AND gates and one 3-
input OR gate for Carry – out

Full Adder Logic Diagram

Conclusion:
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 Lab Manual / Semester 3th
Electronics and Telecommunication Engineering Department, DIEMS, Chh. Sambhajinagar

EXPERIMENT NO 3

Aim: To study & perform Half Subtractor and Full Subtractor

PROCEDURE: -
 Place the IC on breadboard.
 Make circuit connection as per diagram
 Connect Vcc and Ground to respective pins on breadboard
 Connect the outputs to the LEDs
 Apply all the possible combinations of inputs according to truth table and observe
conditions on LEDs
Theory:
1) Half Subtractor
The half-subtractor is a combinational circuit which is used to perform subtraction of two bits. It has
two inputs, X (minuend) and Y (subtrahend) and two outputs D (difference) and B (borrow). The
logic symbol and truth table are shown below.

Figure-1: Logic Symbol of Half subtractor

Figure-2:Truth Table of Half subtractor

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Electronics and Telecommunication Engineering Department, DIEMS, Chh. Sambhajinagar

Figure-3:Circuit Diagram of Half subtractor

From the above truth table we can find the boolean expression.

D=X⊕Y
B = X' Y
From the equation we can draw the half-subtractor circuit as shown in the figure 3.

2) Full Subtractor

A full subtractor is a combinational circuit that performs subtraction involving three bits, namely
minuend, subtrahend, and borrow-in . It accepts three inputs: minuend, subtrahend and a borrow bit
and it produces two outputs: difference and borrow. The logic symbol and truth table are shown
below.

Figure-4:Logic Symbol of Full subtractor

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Electronics and Telecommunication Engineering Department, DIEMS, Chh. Sambhajinagar

Figure-5:Truth Table of Full subtractor

From the above truth table we can find the boolean expression.

D = A ⊕ B ⊕ Bin
B = A' Bin + A' B + B Bin
From the equation we can draw the Full-subtractor circuit as shown in the figure 6.

Figure-6:Circuit Diagram of Full subtractor

Conclusion:

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 Lab Manual / Semester 3th
Electronics and Telecommunication Engineering Department, DIEMS, Chh. Sambhajinagar

EXPERIMENT NO 4

Aim: To study & perform binary to gray and gray to binary code conversion

PROCEDURE: -
 Place the IC on breadboard.
 Make circuit connection as per diagram
 Connect Vcc and Ground to respective pins on breadboard
 Connect the outputs to the LEDs
 Apply all the possible combinations of inputs according to truth table and observe
conditions on LEDs
Theory:
Binary Numbers is default way to store numbers, but in many applications binary numbers are
difficult to use and a variation of binary numbers is needed. This is where Gray codes are very
useful.

Gray code has property that two successive numbers differ in only one bit because of this property
gray code does the cycling through various states with minimal effort and used in K-maps, error
correction, communication etc.

In computer science many a times we need to convert binary code to gray code and vice versa. This
conversion can be done by applying following rules :

1) Binary to Gray conversion :

1. The Most Significant Bit (MSB) of the gray code is always equal to the MSB of the given
binary code.
2. Other bits of the output gray code can be obtained by Ex-ORing binary code bit at that index
and previous index.

There are four inputs and four outputs. The input variable are defined as B3, B2, B1, B0 and
the output variables are defined as G3, G2, G1, G0. From the truth table, combinational
circuit is designed.The logical expressions are defined as :

B3 = G3

B2 ⊕ B3 = G2

B1 ⊕ B2 = G1

B0 ⊕ B1 = G0

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 Lab Manual / Semester 3th
Electronics and Telecommunication Engineering Department, DIEMS, Chh. Sambhajinagar

Figure-1: Binary to Gray Code Converter Circuit

Figure-2: Binary to Gray Code Converter Truth Table

2) Gray to binary conversion :

1.The Most Significant Bit (MSB) of the binary code is always equal to the MSB of the given
binary number.
2.Other bits of the output binary code can be obtained by checking gray code bit at that index. If
current gray code bit is 0, then copy previous binary code bit, else copy invert of previous binary
code bit.

There are four inputs and four outputs. The input variable are defined as G3, G2, G1, G0 and the
output variables are defined as B3, B2, B1, B0. From the truth table, combinational circuit is
designed.The logical expressions are defined as :

G0 ⊕ G1 ⊕ G2 ⊕ G3 = B0

G1 ⊕ G2 ⊕ G3 = B1
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Electronics and Telecommunication Engineering Department, DIEMS, Chh. Sambhajinagar

G2 ⊕ G3 = B2

G3 = B3

Figure-3: Gray to Binary Code Converter Circuit

Figure-4: Gray to Binary Code Converter Truth Table

Conclusion:

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 Lab Manual / Semester 3th
Electronics and Telecommunication Engineering Department, DIEMS, Chh. Sambhajinagar

EXPERIMENT NO 5

Aim: To study & perform Multiplexer

PROCEDURE: -
 Place the IC on breadboard.
 Make circuit connection as per diagram
 Connect Vcc and Ground to respective pins on breadboard
 Connect the outputs to the LEDs
 Apply all the possible combinations of inputs according to truth table and observe
conditions on LEDs
Theory:
The function of a multiplexer is to select the input of any ‘n’ input lines and feed that to one output
line. The function of a de-multiplexer is to inverse the function of the multiplexer and the shortcut
forms of the multiplexer. The de-multiplexers are mux and demux. Some multiplexers perform both
multiplexing and de-multiplexing operations.

Figure-1:Block diagram of Multiplexer and De-multiplexer

1) Multiplexer

Multiplexer is a device that has multiple inputs and a single line output. The select lines determine
which input is connected to the output, and also to increase the amount of data that can be sent over
a network within certain time. It is also called a data selector.

Multiplexers are classified into four types:

a) 2-1 multiplexer (1 select line)

b) 4-1 multiplexer (2 select lines)
c) 8-1 multiplexer(3 select lines)
d) 16-1 multiplexer (4 select lines)

1.1) 4x1 Multiplexer

4x1 Multiplexer has four data inputs I3, I2, I1 & I0, two selection lines S1 & S0 and one output Y.
The block diagram of 4x1 Multiplexer is shown in the following figure.One of these 4 inputs will be
connected to the output based on the combination of inputs present at these two selection lines.
Truth table of 4x1 Multiplexer is shown below.
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Electronics and Telecommunication Engineering Department, DIEMS, Chh. Sambhajinagar

Figure-2:Block diagram of 4x1 Multiplexer

Figure-3:Truth table of 4x1 Multiplexer

Conclusion:

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 Lab Manual / Semester 3th
Electronics and Telecommunication Engineering Department, DIEMS, Chh. Sambhajinagar

EXPERIMENT NO 6

Aim: To study & perform De-Multiplexer

PROCEDURE: -
 Place the IC on breadboard.
 Make circuit connection as per diagram
 Connect Vcc and Ground to respective pins on breadboard
 Connect the outputs to the LEDs
 Apply all the possible combinations of inputs according to truth table and observe
conditions on LEDs
Theory:

De-multiplexer

De-multiplexer is also a device with one input and multiple output lines. It is used to send a signal
to one of the many devices. The main difference between a multiplexer and a de-multiplexer is that
a multiplexer takes two or more signals and encodes them on a wire, whereas a de-multiplexer does
reverse to what the multiplexer does.

De-multiplexer are classified into four types:

a)1-2 demultiplexer (1 select line)

b)1-4 demultiplexer (2 select lines)
c)1-8 demultiplexer (3 select lines)
d)1-16 demultiplexer (4 select lines)

2.2) 1x4 De-multiplexer

1x4 De-Multiplexer has one input I, two selection lines, S1 & S0 and four outputs Y3, Y2, Y1 &
Y0. The block diagram of 1x4 De-Multiplexer is shown in the following figure.

Figure-4:Block diagram of 1x4 De-Multiplexer

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Electronics and Telecommunication Engineering Department, DIEMS, Chh. Sambhajinagar

Figure-5:Truth table of 1x4 De-Multiplexer

Conclusion:

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 Lab Manual / Semester 3th
Electronics and Telecommunication Engineering Department, DIEMS, Chh. Sambhajinagar

EXPERIMENT NO 7

Aim: : To study & perform different Flip-flops

PROCEDURE: -
 Place the IC on breadboard.
 Make circuit connection as per diagram
 Connect Vcc and Ground to respective pins on breadboard
 Connect the outputs to the LEDs
 Apply all the possible combinations of inputs according to truth table and observe
conditions on LEDs
Theory:

A flip flop is an electronic circuit with two stable states that can be used to store binary data. The
stored data can be changed by applying varying inputs. Flip-flops and latches are fundamental
building blocks of digital electronics systems used in computers, communications, and many other
types of systems.

1) R-S flip flop

2) D flip flop
3) J-K flip flop
4) T flip flop
The basic NAND gate RS flip flop circuit is used to store the data and thus provides feedback from
both of its outputs again back to its inputs. The RS flip flop actually has three inputs, SET, RESET
and its current output Q relating to its current state as shown in figure below.

Figure-1:R-S flip flop circuit diagram

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Electronics and Telecommunication Engineering Department, DIEMS, Chh. Sambhajinagar

Figure-2:Characteristics table of R-S flip flop

2) D flip flop

A D flip flop has a single data input. This type of flip flop is obtained from the SR flip flop by
connecting the R input through an inverter, and the S input is connected directly to data input. The
modified clocked SR flip-flop is known as D-flip-flop and is shown below. From the truth table of
SR flip-flop we see that the output of the SR flip-flop is in unpredictable state when the inputs are
same and high. In many practical applications, these input conditions are not required. These input
conditions can be avoided by making them complement of each other.

Figure-3:Circuit diagram of D flip flop

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Electronics and Telecommunication Engineering Department, DIEMS, Chh. Sambhajinagar

Figure-4:Characteristics table of D flip flop

3) J-K flip flop

In a RS flip-flop the input R=S=1 leads to an indeterminate output. The RS flip-flop circuit may be
re-joined if both inputs are 1 than also the outputs are complement of each other as shown in
characteristics table below.

Figure-5:Circuit diagram of J-K flip flop

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Electronics and Telecommunication Engineering Department, DIEMS, Chh. Sambhajinagar

Figure-6:Characteristics table of J-K flip flop

4) T flip flop

T flip-flop is known as toggle flip-flop. The T flip-flop is modification of the J-K flip-flop. Both the
JK inputs of the JK flip – flop are held at logic 1 and the clock signal continuous to change as
shown in table below.

Figure-7:Circuit diagram of T flip flop

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Electronics and Telecommunication Engineering Department, DIEMS, Chh. Sambhajinagar

Figure-8:Characteristics table of T flip flop

Conclusion:

EXPERIMENT NO 8
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Electronics and Telecommunication Engineering Department, DIEMS, Chh. Sambhajinagar

Aim: To study VHDL and simulate the same using software

-- Simple OR gate design

library IEEE;
use IEEE.std_logic_1164.all;

entity or_gate is
port(
a: in std_logic;
b: in std_logic;
q: out std_logic);
end or_gate;

architecture rtl of or_gate is

begin
process(a, b) is
begin
q <= a or b;
end process;
end rtl;
-- Simple half adder design

entity halfadd is
port ( a,b : in bit;
sum, carry : out bit);
end halfadd;
architecture equation of halfadd is
begin
sum <= ((not a)and b)or(a and(not b));
carry <= a and b;
end equation;

-- Simple full adder design

entity fulladd is
port ( a, b, c : in bit;
sum, carry : out bit);
end fulladd;
architecture equation of fulladd is
begin

sum<=(((not a)and(not b)and c)or((not a)and b and(not c))or(a and(not b)and(not c))or(a and b and
c));
carry<=(a and b)or(b and c)or(a and c);

end equation;

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Electronics and Telecommunication Engineering Department, DIEMS, Chh. Sambhajinagar

-- Simple full subtractor design

entity fullsub is
port ( a, b, c : in bit;
diff, borrow : out bit);
end fullsub;

architecture equation of fullsub is

begin

diff <= (((not a)and(not b)and c)or((not a)and b and(not c))or(a and(not b)and(not c))or(a and b and
c));
borrow <= ((not a) and b)or(b and c)or((not a) and c);

end equation;

Conclusion:

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