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EC312 (C) Assignment Questions II-MID 2024-25 For Students

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23 views1 page

EC312 (C) Assignment Questions II-MID 2024-25 For Students

Uploaded by

kesanpallisivanarayana1
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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R.V.R. & J.C.

COLLEGE OF ENGINEERING, GUNTUR-522019


(Autonomous)
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

EC312 VLSI Design Assignment Questions-II for III ECE-C section


QNo Mark UNIT
s
1 a. Explain Pseudo NMOS logic with its features. 6M
Unit-3
b. What are the issues in dynamic logic design? 6M
2. a. Explain the meaning of crosstalk and how to deal it. 6M
b. Design a dynamic CMOS AND-OR PLA using NOR gates as a basis. Design 6M
the circuitry such that inputs are a, b, c and outputs are Unit-4

3 a. Illustrate the advantages and disadvantages of BiCMOS and Explain 6M


BiCMOS inverters.
b. Design a tristate circuit that is in high impedance state when the control 6M
Unit-3
signal T=1 and act as a non-inverting buffer when T=0.
4 a. Design a clocked CMOS circuit that implements the function 6M

b. Explain how Write and Hold operations performed in a DRAM cell? 6M


5 a. Explain how to model the interconnect using single-rung ladder model. 6M
Unit-4
b. Build the following two Boolean functions with a PLA: 6M

6 a. Derive an expression for total number of stages ‘N’ and scaling factor 6M
in order to minimize delay in inverter cascade?
b. Draw the following circuits using complementary pass transistor logic 6M
i. AND/NAND circuit
ii. OR/NOR circuit
iii. XOR/XNOR circuit Unit-3
7 a. Derive expression for rise time delay and fall time delay for unit NOR2 6M
gate. Modify the expression for scaling factor m=3.
b. Differentiate between static and dynamic CMOS. Implement NAND2 6M
gate using dynamic CMOS.
8 a. Discuss ROM arrays in detail. 6M
b. Explain the operation of general SRAM cell with a neat circuit 6M Unit-4
diagram.

9 a Draw a tristate inverter. 1M


b What are the issues of driving large capacitive loads 1M Unit-3
c Define logical effort. 1M
d Draw general SRAM cell. 1M
e Draw the symbol of floating gate MOSFET. 1M Unit-4
f What is the advantage of PLA over ROM? 1M
g What are mirror circuits? 1M
h What are the advantages of dynamic CMOS? 1M
i What is the purpose of logical effort technique? 1M
Unit-3
j Define gate arrays. 1M
k Define crosstalk. 1M
l Give an advantage of charge sharing. 1M
m Draw the equivalent circuit of an interconnect line. 1M
n Define refresh frequency. 1M Unit-4
o How read operation is done in SRAM? 1M
*** ALL THE BEST***

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