FPGA Based Design (410)

Fall-2024
Total Marks
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LAB REPORT
Submitted By

Student Name Registration No.

Maria Bilqess BS-20-IB-103272
Hafsa Hassan BS-21-LB-106451
Muqdas Naz BS-21-IB-105314

Section: A
Date of Submission: 29 April, 2024
Title: Traffic Light Control System Lab 08
Lab Engineers: M.Waqas Arshad , M.Noman Rasool
Batch : EE 21-25

Department of Electrical Engineering

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1 Abstract
This report details the design and functionality of a time-based traffic light controller
system implemented using Verilog Hardware Description Language (HDL). The sys-
tem operates based on predefined timings for each traffic light sequence and utilizes
a counter to manage state transitions. The report outlines the system’s architecture,
operation, and output generation for various traffic light states.

2 Introduction
Traffic congestion is a major concern in urban areas. Efficient traffic management
systems are crucial for reducing congestion, improving traffic flow, and enhancing
pedestrian safety. Traffic light controllers play a significant role in regulating traffic
flow at intersections. This report presents a time-based traffic light controller system
designed using Verilog HDL.
article graphicx

3 System Design
The traffic light controller system is implemented as a Verilog module named Traf-
fic Light Controller. The module receives a clock signal (clk) and a reset signal (rst)
as inputs. It generates four output signals representing the light states for the follow-
ing directions:

• light M1: Main Road 1

• light S: Southbound Traffic
• light MT: Main Road Transversal
• light M2: Main Road 2

The system utilizes several internal signals for operation:

• ps: A 3-bit register to store the current traffic light state.

• count: A 4-bit register to keep track of the elapsed time in a particular state.

4 Functionality
The system operates based on the following logic:

• When the reset signal (rst) is asserted high, the state (ps) is initialized to S1,
and the counter (count) is reset to 0.
• A positive clock edge (posedge clk) triggers the state transition logic.
• The system employs a finite state machine (FSM) implemented using a case
statement on the current state (ps).
• Each state (S1 to S6) represents a specific traffic light sequence with predefined
timings stored in constant variables (sec7, sec5, sec2, sec3).

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 Figure 1.1: Caption

• The counter (count) increments on each positive clock edge within a state.

• Once the counter reaches the predefined time limit for the current state, the
system transitions to the next state based on the FSM logic.

• A separate case statement on the current state (ps) assigns the appropriate
light color combinations (0 - red, 1 - yellow, 2 - green) to the output signals
(light M1, light M2, light MT, light S).

5 Simulation Results
The simulation result of designed system are given in Fig 1.1

6 Conclusion
This report presented a time-based traffic light controller system implemented in
Verilog HDL. The system demonstrates a basic approach to traffic light control using
a state machine and timers.The desired time based system was simulated and it
worked as expected, While this design provides a fundamental understanding, real-
world traffic management systems often incorporate additional functionalities such as
sensor-based traffic detection and adaptive control algorithms for improved efficiency.

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 7 Code
listings color
1 module T r a f f i c _ L i g h t _ C o n t r o l l e r (
2 input clk , rst ,
3 output reg [2:0] light_M1 ,
4 output reg [2:0] light_S ,
5 output reg [2:0] light_MT ,
6 output reg [2:0] light_M2
7 );
8
9 parameter S1 =0 , S2 =1 , S3 =2 , S4 =3 , S5 =4 , S6 =5;
10 reg [3:0] count ;
11 reg [2:0] ps ;
12 parameter sec7 =7 , sec5 =5 , sec2 =2 , sec3 =3;
13
14 always@ ( posedge clk or posedge rst )
15 begin
16 if ( rst ==1)
17 begin
18 ps <= S1 ;
19 count <=0;
20 end
21 else
22 case ( ps )
23 S1 : if ( count < sec7 )
24 begin
25 ps <= S1 ;
26 count <= count +1;
27 end
28 else
29 begin
30 ps <= S2 ;
31 count <=0;
32 end
33 S2 : if ( count < sec2 )
34 begin
35 ps <= S2 ;
36 count <= count +1;
37 end
38 else
39 begin
40 ps <= S3 ;
41 count <=0;
42 end
43 S3 : if ( count < sec5 )
44 begin
45 ps <= S3 ;
46 count <= count +1;
47 end
48 else
49 begin
50 ps <= S4 ;
51 count <=0;
52 end
53 S4 : if ( count < sec2 )
54 begin
55 ps <= S4 ;
56 count <= count +1;

4
 57 end
58 else
59 begin
60 ps <= S5 ;
61 count <=0;
62 end
63 S5 : if ( count < sec3 )
64 begin
65 ps <= S5 ;
66 count <= count +1;
67 end
68 else
69 begin
70 ps <= S6 ;
71 count <=0;
72 end
73 S6 : if ( count < sec2 )
74 begin
75 ps <= S6 ;
76 count <= count +1;
77 end
78 else
79 begin
80 ps <= S1 ;
81 count <=0;
82 end
83 default : ps <= S1 ;
84 endcase
85 end
86
87 always@ ( ps )
88 begin
89 case ( ps )
90 S1 :
91 begin
92 light_M1 <=3 ' b001 ;
93 light_M2 <=3 ' b001 ;
94 light_MT <=3 ' b100 ;
95 light_S <=3 ' b100 ;
96 end
97 S2 :
98 begin
99 light_M1 <=3 ' b001 ;
100 light_M2 <=3 ' b010 ;
101 light_MT <=3 ' b100 ;
102 light_S <=3 ' b100 ;
103 end
104 S3 :
105 begin
106 light_M1 <=3 ' b001 ;
107 light_M2 <=3 ' b100 ;
108 light_MT <=3 ' b001 ;
109 light_S <=3 ' b100 ;
110 end
111 S4 :
112 begin
113 light_M1 <=3 ' b010 ;
114 light_M2 <=3 ' b100 ;
115 light_MT <=3 ' b010 ;
116 light_S <=3 ' b100 ;

5
117 end
118 S5 :
119 begin
120 light_M1 <=3 ' b100 ;
121 light_M2 <=3 ' b100 ;
122 light_MT <=3 ' b100 ;
123 light_S <=3 ' b001 ;
124 end
125 S6 :
126 begin
127 light_M1 <=3 ' b100 ;
128 light_M2 <=3 ' b100 ;
129 light_MT <=3 ' b100 ;
130 light_S <=3 ' b010 ;
131 end
132 default :
133 begin
134 light_M1 <=3 ' b000 ;
135 light_M2 <=3 ' b000 ;
136 light_MT <=3 ' b000 ;
137 light_S <=3 ' b000 ;
138 end
139 endcase
140 end
141 endmodule

Listing 1.1: Verilog HDL code for Traffic Light Controller