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Fpga Lab

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Chetan Cherry
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24 views92 pages

Fpga Lab

Uploaded by

Chetan Cherry
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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1. a.

Verilog modeling FPGA implementation of majority encoder

Verilog code for majority encoder:

module majenc(a,b,c,f);

input a,b,c;

output f;

assign f=(a&b)|(b&c)|(c&a);

endmodule

Testbench:

module majenc_tb();

reg a,b,c;

wire f;
majenc e1(a,b,c,f);

initial

begin

a=0; b=0; c=0;

#5

a=0; b=0; c=1;

#5

a=0; b=1; c=0;

#5

a=0; b=1; c=1;

#5

a=1; b=0; c=0;

#5

a=1; b=0; c=1;

#5

a=1; b=1; c=0;

#5

a=1; b=1; c=1;

#10 $finish;

end

//$monitor("a=%b,b=%b,c=%b,f=%b", a,b,c,f);

endmodule

Xdc file:

##Switches

set_property -dict { PACKAGE_PIN F22 IOSTANDARD LVCMOS33 } [get_ports { a }];


#IO_L24N_T3_RS0_15 Sch=sw[0]
set_property -dict { PACKAGE_PIN G22 IOSTANDARD LVCMOS33 } [get_ports { b }];
#IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1]

set_property -dict { PACKAGE_PIN H22 IOSTANDARD LVCMOS33 } [get_ports { c }];


#IO_L6N_T0_D08_VREF_14 Sch=sw[2]

#set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { SW[3] }];


#IO_L13N_T2_MRCC_14 Sch=sw[3]

#set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { SW[4] }];


#IO_L12N_T1_MRCC_14 Sch=sw[4]

#set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { SW[5] }];


#IO_L7N_T1_D10_14 Sch=sw[5]

#set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { SW[6] }];


#IO_L17N_T2_A13_D29_14 Sch=sw[6]

#set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { SW[7] }];


#IO_L5N_T0_D07_14 Sch=sw[7]

#set_property -dict { PACKAGE_PIN T8 IOSTANDARD LVCMOS18 } [get_ports { SW[8] }];


#IO_L24N_T3_34 Sch=sw[8]

#set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS18 } [get_ports { SW[9] }]; #IO_25_34


Sch=sw[9]

#set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { SW[10] }];


#IO_L15P_T2_DQS_RDWR_B_14 Sch=sw[10]

#set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { SW[11] }];


#IO_L23P_T3_A03_D19_14 Sch=sw[11]

#set_property -dict { PACKAGE_PIN H6 IOSTANDARD LVCMOS33 } [get_ports { SW[12] }];


#IO_L24P_T3_35 Sch=sw[12]

#set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { SW[13] }];


#IO_L20P_T3_A08_D24_14 Sch=sw[13]

#set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports { SW[14] }];


#IO_L19N_T3_A09_D25_VREF_14 Sch=sw[14]

#set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { SW[15] }];


#IO_L21P_T3_DQS_14 Sch=sw[15]

## LEDs

set_property -dict { PACKAGE_PIN W22 IOSTANDARD LVCMOS33 } [get_ports { f }];


#IO_L18P_T2_A24_15 Sch=led[0]
#set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { LED[1] }];
#IO_L24P_T3_RS1_15 Sch=led[1]

Waveform:

Schematic:

Synthesis:
Utilization:
Power route:
Fpga:
1 b. Verilog modeling and simulation of one bit fulladder
Truth Table –

a b cin sum cout

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

Verilog code:-
module Fulladd1(a,b,cin,sum,cout);
input a,b,cin;
output sum,cout;
assign sum=a^b^cin;
assign cout=(a&b)|(b&cin)|(cin&a);
endmodule

Test bench:-
module Fulladd1_tb;
reg a, b, cin;
wire sum, cout;
Fulladd1 fl(a,b,cin,sum,cout);
initial
begin
a = 0; b = 0 ;cin=0;
#2 a = 0 ; b = 0 ;cin=1;
#3 a = 0; b = 1; cin=1;
#4 a = 1; b = 1 ;cin=1;
end
endmodule

XDC:-
##Switches

set_property -dict { PACKAGE_PIN F22 IOSTANDARD LVCMOS33


} [get_ports { a }]; #IO_L24N_T3_RS0_15 Sch=sw[0]
set_property -dict { PACKAGE_PIN G22 IOSTANDARD LVCMOS33
} [get_ports { b }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1]
set_property -dict { PACKAGE_PIN H22 IOSTANDARD LVCMOS33
} [get_ports { cin }]; #IO_L6N_T0_D08_VREF_14 Sch=sw[2]

## LEDs

set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33


} [get_ports { sum }]; #IO_L18P_T2_A24_15 Sch=led[0]
set_property -dict { PACKAGE_PIN U19 IOSTANDARD LVCMOS33
} [get_ports { cout }]; #IO_L24P_T3_RS1_15 Sch=led[1]
FPGA:-

1c. Verilog modeling and FPGA implementation of four-bit


fulladder.
module fulladd1(a,b,cin,sum,cout);
input a,b,cin;
output sum,cout;
assign sum=a^b^cin;
assign cout=(a&b)|(b&cin)|(cin&a);
endmodule

module fa4(a,b,sum);
input [3:0]a,b;
output [4:0]sum;
wire w1,w2,w3;
fulladd1 f1(a[0],b[0],1'b0,sum[0],w1);
fulladd1 f2(a[1],b[1],w1,sum[1],w2);
fulladd1 f3(a[2],b[2],w2,sum[2],w3);
fulladd1 f4(a[3],b[3],w3,sum[3],sum[4]);
endmodule
Testbench:-
module fa4_tb();
reg [3:0]a,b;
wire [4:0]sum;
fa4 f1(a,b,sum);
initial
begin
a = 4'd4; b = 4'd6;
#20 a = 4'd3; b = 4'd2;
#20 a = 4'd11; b = 4'd13;
#20 a = 4'd14; b = 4'd12;
#20 $finish;
end
endmodule
XDC:-
##Switches
set_property -dict { PACKAGE_PIN F22 IOSTANDARD LVCMOS33 }
[get_ports { a[0] }]; #IO_L24N_T3_RS0_15 Sch=sw[0]
set_property -dict { PACKAGE_PIN G22 IOSTANDARD LVCMOS33 }
[get_ports { b[0] }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1]
set_property -dict { PACKAGE_PIN H22 IOSTANDARD LVCMOS33 }
[get_ports { a[1] }]; #IO_L6N_T0_D08_VREF_14 Sch=sw[2]
set_property -dict { PACKAGE_PIN F21 IOSTANDARD LVCMOS33 }
[get_ports { b[1] }]; #IO_L13N_T2_MRCC_14 Sch=sw[3]
set_property -dict { PACKAGE_PIN H19 IOSTANDARD LVCMOS33 }
[get_ports { a[2] }]; #IO_L12N_T1_MRCC_14 Sch=sw[4]
set_property -dict { PACKAGE_PIN H18 IOSTANDARD LVCMOS33 }
[get_ports { b[2] }]; #IO_L7N_T1_D10_14 Sch=sw[5]
set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 }
[get_ports { a[3] }]; #IO_L17N_T2_A13_D29_14 Sch=sw[6]
set_property -dict { PACKAGE_PIN M15 IOSTANDARD LVCMOS33 }
[get_ports { b[3] }]; #IO_L5N_T0_D07_14 Sch=sw[7]

## LEDs
set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 }
[get_ports { sum[0] }]; #IO_L18P_T2_A24_15 Sch=led[0]
set_property -dict { PACKAGE_PIN U19 IOSTANDARD LVCMOS33 }
[get_ports { sum[1] }]; #IO_L24P_T3_RS1_15 Sch=led[1]
set_property -dict { PACKAGE_PIN W22 IOSTANDARD LVCMOS33 }
[get_ports { sum[2] }]; #IO_L17N_T2_A25_15 Sch=led[2]
set_property -dict { PACKAGE_PIN V22 IOSTANDARD LVCMOS33 }
[get_ports { sum[3] }]; #IO_L8P_T1_D11_14 Sch=led[3]
set_property -dict { PACKAGE_PIN U21 IOSTANDARD LVCMOS33 }
[get_ports { sum[4] }]; #IO_L7P_T1_D09_14 Sch=led[4]
Implentation:-
2. a.Verilog modeling and FPGA Implementation of 4X1 multiplexer:-
Verilog code for mux41:
module mux41(I,S,Y);
input [0:3]I;
input [0:1]S;
output Y;
reg Y;
always @(I or S)
begin
case(S)
2'b00 : Y=I[0];
2'b01 : Y=I[1];
2'b10 : Y=I[2];
2'b11 : Y=I[3];
endcase
end
endmodule
testbench for mux41:
module mux41_tb();
reg [0:3]I;
reg [0:1]S;
wire Y;
mux41 mux(I,S,Y);
initial
begin
I[0:3]=1111;
S[0:1]=10;
#5
I[0:3]=1000;
S[0:1]=01;
#5
I[0:3]=1100;
S[0:1]=01;
#5
I[0:3]=0111;
S[0:1]=00;
end
endmodule
xdc for mux41:
##Switches
set_property -dict { PACKAGE_PIN F22 IOSTANDARD LVCMOS33 }
[get_ports { I[0] }]; #IO_L24N_T3_RS0_15 Sch=sw[0]
set_property -dict { PACKAGE_PIN G22 IOSTANDARD LVCMOS33 }
[get_ports { I[1] }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1]
set_property -dict { PACKAGE_PIN H22 IOSTANDARD LVCMOS33 }
[get_ports { I[2] }]; #IO_L6N_T0_D08_VREF_14 Sch=sw[2]
set_property -dict { PACKAGE_PIN F21 IOSTANDARD LVCMOS33 }
[get_ports { I[3] }]; #IO_L13N_T2_MRCC_14 Sch=sw[3]
set_property -dict { PACKAGE_PIN H19 IOSTANDARD LVCMOS33 }
[get_ports { S[0] }]; #IO_L12N_T1_MRCC_14 Sch=sw[4]
set_property -dict { PACKAGE_PIN H18 IOSTANDARD LVCMOS33 }
[get_ports { S[1] }]; #IO_L7N_T1_D10_14 Sch=sw[5]
#set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 }
[get_ports { SW[6] }]; #IO_L17N_T2_A13_D29_14 Sch=sw[6]
#set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 }
[get_ports { SW[7] }]; #IO_L5N_T0_D07_14 Sch=sw[7]
#set_property -dict { PACKAGE_PIN T8 IOSTANDARD LVCMOS18 }
[get_ports { SW[8] }]; #IO_L24N_T3_34 Sch=sw[8]
#set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS18 }
[get_ports { SW[9] }]; #IO_25_34 Sch=sw[9]
#set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 }
[get_ports { SW[10] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=sw[10]
#set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 }
[get_ports { SW[11] }]; #IO_L23P_T3_A03_D19_14 Sch=sw[11]
#set_property -dict { PACKAGE_PIN H6 IOSTANDARD LVCMOS33 }
[get_ports { SW[12] }]; #IO_L24P_T3_35 Sch=sw[12]
#set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 }
[get_ports { SW[13] }]; #IO_L20P_T3_A08_D24_14 Sch=sw[13]
#set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 }
[get_ports { SW[14] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=sw[14]
#set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 }
[get_ports { SW[15] }]; #IO_L21P_T3_DQS_14 Sch=sw[15]
## LEDs
set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 }
[get_ports { Y }]; #IO_L18P_T2_A24_15 Sch=led[0]

waveform:

Schematic:
Synthesis:

Utilization:

Ut2:
Ut3:

Ut4:

Ut5:
Ut6:

Power route:
Fpga output:

2b. Verilog modeling and simulation of 8X1 multiplexer

Verilog code:-

module mux81(ip, sel, op);

input [7:0] ip;

input [2:0] sel;

output op;

wire w1, w2;

mux41 mux_low(ip[3:0], sel[1:0], w1);

mux41 mux_high(ip[7:4], sel[1:0], w2);

mux21 mux_final(w1, w2, sel[2], op);

endmodule
module mux21(ip0, ip1, sel, op);

input ip0, ip1;

input sel;

output op;

assign op = sel ? ip1 : ip0;

endmodule

module mux41(ip, sel, op);

input [3:0] ip;

input [1:0] sel;

output op;

assign op = (sel == 2'b00) ? ip[0] :

(sel == 2'b01) ? ip[1] :

(sel == 2'b10) ? ip[2] : ip[3];

Endmodule

Test bench:-

module mux81_tb();

reg [7:0] ip;

reg [2:0] sel;

wire op;

mux81 uut (ip, sel, op);

initial begin
ip = 8'b10101010; sel = 3'b000;

#20; sel = 3'b001;

#20; sel = 3'b010;

#20; sel = 3'b011;

#20; sel = 3'b100;

#20; sel = 3'b101;

#20; sel = 3'b110;

#20; sel = 3'b111;

#20;

$finish;

end

initial

begin

$monitor("At time %0d, ip = %b, sel = %b, op = %b", $time, ip, sel, op);

end

endmodule

wave form:-
synthesis report:-

Power report:
3 a. Verilog modeling and FPGA Implementation of BCD to 7-Segment Decoder.

Verilog code:-

module seg7decoder (input [3:0] data, output reg [6:0] segments);

parameter BLANK = 7'b000_0000;

parameter ZERO = 7'b111_1110;

parameter ONE = 7'b011_0000;

parameter TWO = 7'b110_1101;

parameter THREE = 7'b111_1001;

parameter FOUR = 7'b011_0011;

parameter FIVE = 7'b101_1011;

parameter SIX = 7'b101_1111;

parameter SEVEN = 7'b111_0000;

parameter EIGHT = 7'b111_1111;

parameter NINE = 7'b111_1011;


always @(*) begin

case(data)

4'b0000: segments = ZERO;

4'b0001: segments = ONE;

4'b0010: segments = TWO;

4'b0011: segments = THREE;

4'b0100: segments = FOUR;

4'b0101: segments = FIVE;

4'b0110: segments = SIX;

4'b0111: segments = SEVEN;

4'b1000: segments = EIGHT;

4'b1001: segments = NINE;

default: segments = BLANK;

endcase

end

endmodule

testbench:-
module seg7decoder_tb;

reg [3:0] data; // BCD input

wire [6:0] segments; // 7-segment display output

// Instantiate the Unit Under Test (UUT)

seg7decoder uut (

.data(data),

.segments(segments)

);

initial begin
$monitor("BCD Input = %b, 7-Segment Output = %b", data, segments);

// Test all BCD values from 0 to 9

data = 4'b0000; #20;

data = 4'b0001; #20;

data = 4'b0010; #20;

data = 4'b0011; #20;

data = 4'b0100; #20;

data = 4'b0101; #20;

data = 4'b0110; #20;

data = 4'b0111; #20;

data = 4'b1000; #20;

data = 4'b1001; #20;

// Test default case (invalid input)

data = 4'b1010; #20;

data = 4'b1111; #20;

$finish;

end

endmodule

XDC:-
##Switches

set_property -dict { PACKAGE_PIN M15 IOSTANDARD LVCMOS33 } [get_ports { data[0] }];


#IO_L24N_T3_RS0_15 Sch=sw[0]

set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { data[1] }];


#IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1]

set_property -dict { PACKAGE_PIN H18 IOSTANDARD LVCMOS33 } [get_ports { data[2] }];


#IO_L6N_T0_D08_VREF_14 Sch=sw[2]
set_property -dict { PACKAGE_PIN H19 IOSTANDARD LVCMOS33 } [get_ports { data[3] }];
#IO_L13N_T2_MRCC_14 Sch=sw[3]

##7 segment display

set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { segments[0] }];


#IO_L4P_T0_35 Sch=seg[0] (segment a)

set_property -dict { PACKAGE_PIN U19 IOSTANDARD LVCMOS33 } [get_ports { segments[1] }];


#IO_L19P_T0_35 Sch=seg[1] (segment b)

set_property -dict { PACKAGE_PIN W22 IOSTANDARD LVCMOS33 } [get_ports { segments[2] }];


#IO_L18P_T1_35 Sch=seg[2] (segment c)

set_property -dict { PACKAGE_PIN V22 IOSTANDARD LVCMOS33 } [get_ports { segments[3] }];


#IO_L19P_T1_35 Sch=seg[3] (segment d)

set_property -dict { PACKAGE_PIN U21 IOSTANDARD LVCMOS33 } [get_ports { segments[4] }];


#IO_L16P_T2_35 Sch=seg[4] (segment e)

set_property -dict { PACKAGE_PIN U22 IOSTANDARD LVCMOS33 } [get_ports { segments[5] }];


#IO_L16N_T1_35 Sch=seg[5] (segment f)

set_property -dict { PACKAGE_PIN T21 IOSTANDARD LVCMOS33 } [get_ports { segments[6] }];


#IO_L14N_T2_35 Sch=seg[6] (segment g)

Waveform:-
Fpga output:
3) b.Verilog modeling and simulation of 3X8 Decoder with enable.
Verilog code for dec38:

module dec38(en,ip,op);

input en;

input [2:0]ip;

output[0:7] op;

assign op[0]=en &(~ip[2])&(~ip[1])&(~ip[0]);

assign op[1]=en &(~ip[2])&(~ip[1])&(ip[0]);

assign op[2]=en &(~ip[2])&(ip[1])&(~ip[0]);

assign op[3]=en &(~ip[2])&(ip[1])&(ip[0]);

assign op[4]=en &(ip[2])&(~ip[1])&(~ip[0]);

assign op[5]=en &(ip[2])&(~ip[1])&(ip[0]);

assign op[6]=en &(ip[2])&(ip[1])&(~ip[0]);

assign op[7]=en &(ip[2])&(ip[1])&(ip[0]);

endmodule

testbench:

module dec38_tb();

reg en;

reg [2:0] ip;

wire [0:7] op;

dec38 d1(en , ip, op);

initial

begin

en=1'b0;ip=3'd0;

#20 en=1'b0;ip=3'd0;

#20 en=1'b0;ip=3'd3;

#20 en=1'b1;ip=3'd0;

#20 en=1'b1;ip=3'd1;

#20 en=1'b1;ip=3'd2;
#20 en=1'b1;ip=3'd3;

#20 en=1'b1;ip=3'd4;

#20 en=1'b1;ip=3'd5;

#20 en=1'b1;ip=3'd6;

#20 en=1'b1;ip=3'd7;

//#20 $finish;

end

initial $monitor("en=%b ip=%b op=%b",en,ip,op);

endmodule

xdc:

##Switches

set_property -dict { PACKAGE_PIN F22 IOSTANDARD LVCMOS33 } [get_ports { en }];


#IO_L24N_T3_RS0_15 Sch=sw[0]

set_property -dict { PACKAGE_PIN G22 IOSTANDARD LVCMOS33 } [get_ports { ip[0] }];


#IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1]

set_property -dict { PACKAGE_PIN H22 IOSTANDARD LVCMOS33 } [get_ports { ip[1] }];


#IO_L6N_T0_D08_VREF_14 Sch=sw[2]

set_property -dict { PACKAGE_PIN F21 IOSTANDARD LVCMOS33 } [get_ports { ip[2] }];


#IO_L13N_T2_MRCC_14 Sch=sw[3]

#set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { SW[4] }];


#IO_L12N_T1_MRCC_14 Sch=sw[4]

#set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { SW[5] }];


#IO_L7N_T1_D10_14 Sch=sw[5]

#set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { SW[6] }];


#IO_L17N_T2_A13_D29_14 Sch=sw[6]

#set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { SW[7] }];


#IO_L5N_T0_D07_14 Sch=sw[7]

#set_property -dict { PACKAGE_PIN T8 IOSTANDARD LVCMOS18 } [get_ports { SW[8] }];


#IO_L24N_T3_34 Sch=sw[8]
#set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS18 } [get_ports { SW[9] }]; #IO_25_34
Sch=sw[9]

#set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { SW[10] }];


#IO_L15P_T2_DQS_RDWR_B_14 Sch=sw[10]

#set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { SW[11] }];


#IO_L23P_T3_A03_D19_14 Sch=sw[11]

#set_property -dict { PACKAGE_PIN H6 IOSTANDARD LVCMOS33 } [get_ports { SW[12] }];


#IO_L24P_T3_35 Sch=sw[12]

#set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { SW[13] }];


#IO_L20P_T3_A08_D24_14 Sch=sw[13]

#set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports { SW[14] }];


#IO_L19N_T3_A09_D25_VREF_14 Sch=sw[14]

#set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { SW[15] }];


#IO_L21P_T3_DQS_14 Sch=sw[15]

## LEDs

set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { op[0] }];


#IO_L18P_T2_A24_15 Sch=led[0]

set_property -dict { PACKAGE_PIN U19 IOSTANDARD LVCMOS33 } [get_ports { op[1] }];


#IO_L24P_T3_RS1_15 Sch=led[1]

set_property -dict { PACKAGE_PIN W22 IOSTANDARD LVCMOS33 } [get_ports { op[2] }];


#IO_L17N_T2_A25_15 Sch=led[2]

set_property -dict { PACKAGE_PIN V22 IOSTANDARD LVCMOS33 } [get_ports { op[3] }];


#IO_L8P_T1_D11_14 Sch=led[3]

set_property -dict { PACKAGE_PIN U21 IOSTANDARD LVCMOS33 } [get_ports { op[4] }];


#IO_L7P_T1_D09_14 Sch=led[4]

set_property -dict { PACKAGE_PIN U22 IOSTANDARD LVCMOS33 } [get_ports { op[5] }];


#IO_L18N_T2_A11_D27_14 Sch=led[5]

set_property -dict { PACKAGE_PIN T21 IOSTANDARD LVCMOS33 } [get_ports { op[6] }];


#IO_L17P_T2_A14_D30_14 Sch=led[6]

set_property -dict { PACKAGE_PIN T22 IOSTANDARD LVCMOS33 } [get_ports { op[7] }];


#IO_L18P_T2_A12_D28_14 Sch=led[7]
#set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { LED[8] }];
#IO_L16N_T2_A15_D31_14 Sch=led[8]

Waveforms:

Schematic:
Synthesis:

Power route:

Utilization:
Ut2:

Ut3:

Ut4:
Ut5:

Ut6:

fpga:
c. Verilog modeling and FPGA Implementation of 4-bit comparator
Verilog code:-
module comp(A0,B0,A1,B1,A2,B2,A3,B3,eq,lt,gt);

input A0,B0,A1,B1,A2,B2,A3,B3;

output eq,gt,lt;

assign x0=(A0&B0)|(~A0)&(~B0);

assign x1=(A1&B1)|(~A1)&(~B1);

assign x2=(A2&B2)|(~A2)&(~B2);

assign x3=(A3&B3)|(~A3)&(~B3);

assign eq=x0&x1&x2&x3;

assign gt=A3&(~B3)|x3&A2&(~B2)|x3&x2&A1&(~B1)|x3&x2&x1&A0&(~B0);

assign lt=(~A3)&B3|x3&(~A2)&B2|x3&x2&(~A1)&B1|x3&x2&x1&(~A0)&B0;

endmodule

testbench:-

module bits4comparator_tb;
reg A0, B0, A1, B1, A2, B2, A3, B3;

wire eq, gt, lt;

bits4comparator uut (

.A0(A0), .B0(B0),

.A1(A1), .B1(B1),

.A2(A2), .B2(B2),

.A3(A3), .B3(B3),

.eq(eq), .gt(gt), .lt(lt)

);

initial begin

{A3, A2, A1, A0} = 4'b0000;

{B3, B2, B1, B0} = 4'b0000;

#10;

{A3, A2, A1, A0} = 4'b1010;

{B3, B2, B1, B0} = 4'b0101;

#10;

{A3, A2, A1, A0} = 4'b0011;

{B3, B2, B1, B0} = 4'b1100;

#10;

{A3, A2, A1, A0} = 4'b1111;

{B3, B2, B1, B0} = 4'b1111;

#10;

{A3, A2, A1, A0} = 4'b1001;


{B3, B2, B1, B0} = 4'b0110;

#10;

$stop;

end

endmodule

XDC file:-
##Switches

set_property -dict { PACKAGE_PIN F22 IOSTANDARD LVCMOS33 } [get_ports { A0 }];


#IO_L24N_T3_RS0_15 Sch=sw[0]

set_property -dict { PACKAGE_PIN G22 IOSTANDARD LVCMOS33 } [get_ports { B0 }];


#IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1]

set_property -dict { PACKAGE_PIN H22 IOSTANDARD LVCMOS33 } [get_ports { A1 }];


#IO_L6N_T0_D08_VREF_14 Sch=sw[2]

set_property -dict { PACKAGE_PIN F21 IOSTANDARD LVCMOS33 } [get_ports { B1 }];


#IO_L13N_T2_MRCC_14 Sch=sw[3]

set_property -dict { PACKAGE_PIN H19 IOSTANDARD LVCMOS33 } [get_ports { A2 }];


#IO_L12N_T1_MRCC_14 Sch=sw[4]

set_property -dict { PACKAGE_PIN H18 IOSTANDARD LVCMOS33 } [get_ports { B2 }];


#IO_L7N_T1_D10_14 Sch=sw[5]

set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { A3 }];


#IO_L17N_T2_A13_D29_14 Sch=sw[6]

set_property -dict { PACKAGE_PIN M15 IOSTANDARD LVCMOS33 } [get_ports { B3 }];


#IO_L5N_T0_D07_14 Sch=sw[7]

## LEDs

set_property -dict { PACKAGE_PIN T22 IOSTANDARD LVCMOS33 } [get_ports { eq0 }];


#IO_L18P_T2_A24_15 Sch=led[0]

set_property -dict { PACKAGE_PIN T21 IOSTANDARD LVCMOS33 } [get_ports { gt1 }];


#IO_L24P_T3_RS1_15 Sch=led[1]

set_property -dict { PACKAGE_PIN U22 IOSTANDARD LVCMOS33 } [get_ports { lt2 }];


#IO_L17N_T2_A25_15 Sch=led[2]
RTL analsics:- scschematic:-
FPGA design:-

4 a.Verilog modeling and simulation of a D-Latch,D Flip Flop


Verilog code for dlatch:

module dlatch(d,clk,q);

input d,clk;

output q;

reg q;

always@(d or clk)

begin

q=d;

end

endmodule

testbench:

module dlatch_tb();

reg d,clk;

wire q;
dlatch d1(d,clk,q);

initial

//always #7 d=~d;

//always #20 clk=~clk;

begin

d=1'b0;

clk=1'b0;

#20

d=1'b1;

clk=1'b1;

#20

d=1'b0;

clk=1'b1;

#20

d=1'b1;

clk=1'b0;

#300 $finish;

end

endmodule

xdc:

## Clock signal

set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { clk }];


#IO_L12P_T1_MRCC_35 Sch=clk100mhz

#create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {CLK100MHZ}];

##Switches
set_property -dict { PACKAGE_PIN F22 IOSTANDARD LVCMOS33 } [get_ports { d }];
#IO_L24N_T3_RS0_15 Sch=sw[0]

#set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { d[1] }];


#IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1]

#set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { SW[2] }];


#IO_L6N_T0_D08_VREF_14 Sch=sw[2]

#set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { SW[3] }];


#IO_L13N_T2_MRCC_14 Sch=sw[3]

#set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { SW[4] }];


#IO_L12N_T1_MRCC_14 Sch=sw[4]

#set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { SW[5] }];


#IO_L7N_T1_D10_14 Sch=sw[5]

#set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { SW[6] }];


#IO_L17N_T2_A13_D29_14 Sch=sw[6]

#set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { SW[7] }];


#IO_L5N_T0_D07_14 Sch=sw[7]

#set_property -dict { PACKAGE_PIN T8 IOSTANDARD LVCMOS18 } [get_ports { SW[8] }];


#IO_L24N_T3_34 Sch=sw[8]

#set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS18 } [get_ports { SW[9] }]; #IO_25_34


Sch=sw[9]

#set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { SW[10] }];


#IO_L15P_T2_DQS_RDWR_B_14 Sch=sw[10]

#set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { SW[11] }];


#IO_L23P_T3_A03_D19_14 Sch=sw[11]

#set_property -dict { PACKAGE_PIN H6 IOSTANDARD LVCMOS33 } [get_ports { SW[12] }];


#IO_L24P_T3_35 Sch=sw[12]

#set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { SW[13] }];


#IO_L20P_T3_A08_D24_14 Sch=sw[13]

#set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports { SW[14] }];


#IO_L19N_T3_A09_D25_VREF_14 Sch=sw[14]

#set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { SW[15] }];


#IO_L21P_T3_DQS_14 Sch=sw[15]
## LEDs

set_property -dict { PACKAGE_PIN W22 IOSTANDARD LVCMOS33 } [get_ports { q }];


#IO_L18P_T2_A24_15 Sch=led[0]

#set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { LED[1] }];


#IO_L24P_T3_RS1_15 Sch=led[1]

#set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { LED[2] }];


#IO_L17N_T2_A25_15 Sch=led[2]

Waveform:

Schematic:

Power route:

Synthesis:
Utilization:
Fpga:
Verilog code for D Flip Flop:
module dff(d, clk, q);
input d, clk;
output q;
reg q;
always @(posedge clk)
begin
q = d;
end
endmodule
testbench:-
module dff_tb;
reg d, clk;
wire q;
dff d1(d,clk,q);
initial
//always ##7 clk=~clk;
//always #7 d=~d;
begin
d = 1'b0; clk = 1'b1;
#20 d = 1'b1; clk = 1'b0;
#20 d = 1'b1; clk = 1'b1;
#20 d = 1'b0; clk = 1'b1;
#300 $finish;
end

Waveform:-
Synthesis report
Power route:

4 b. Verilog modeling and simulation of a 4-bit register

Verilog code:-

module reg4(d,clk,en,rst,q);

input[3:0]d;
input clk,en,rst;

output reg[3:0]q;

always@(posedge clk or posedge rst)

begin

if(rst)

q=4'd0;

else if(en) q=d;

end

endmodule

Testbench:-

module reg4_tb();

reg [3:0]d;

reg clk,en,rst;

wire [3:0]q;

reg4 r1(d,clk,en,rst,q);

always #20 clk=~clk;

initial

begin
clk=1'b0; en=1'b0; d=4'd10;

#20 rst=1'b0;

#20 d=4'd5;

#20 d=4'd6;

#20 en=1'b1; d=4'd7;

#20 d=4'd3;

#20 en=1'b0; d=4'd8;

#20 en=1'b1; d=4'd2;

#20 d=4'd11;

#11 rst=1'b1;

#20 $finish;

end

endmodule

waveform:-

Schematic:-
Synthesis report:-

Power report:-
5.a.Verilog modeling and simulation of counters

Counter 4 bit with enable:-

Verilog code:-

module count4_cen(clk,rst,cen,q);

input clk,rst,cen;

output[3:0]q;

reg[3:0]count;

always@(posedge clk or posedge rst)

begin

if(rst) count=4'd0;

else if(cen)

begin
if(count<=4'd8) count<=4'd1;

else count=count+4'd1;

end

end

assign q=count;

endmodule

testbench:-

module count4_cen_tb();

reg clk,rst,cen;

wire[3:0]count;

count4_cen c1(clk,rst,cen,count);

always #10 clk=~clk;

initial

begin

clk=1'b0;rst=1'b1;cen=1'b1;

#20 rst=1'b0;

#200 cen=1'b0;

#100 cen=1'b1;
#200 rst=1'b1;

#60 rst=1'b0;

#100 $finish;

end

endmodule

waveform:-
Synthesis Report:-

Power report:-
5 b.Verilog,modeling and FPGA implementation of a 4-bit counter

Verilog code:-

module count4(clk,rst,q);

input clk,rst;

output[3:0]q;

reg[3:0]count;

always@(posedge clk or posedge rst)

begin

if(rst) count=4'd0;

else count=count+4'd1;

end

assign q=count;

endmodule
test bench:-

module count4_tb();

reg clk,rst;

wire[3:0]count;

count4 c1(clk,rst,count);

always #10 clk=~clk;

initial

begin

clk=1'b0;rst=1'b1;

#20 rst=1'b0;

#200 rst=1'b1;

#60 rst=1'b0;

#100 $finish;

end

endmodule

Waveform:-
Power report
module count4_cen(clk,rst,cen,q);
input clk,rst,cen;
output[3:0]q;
reg[3:0]count;
always@(posedge clk or posedge rst)
begin
if(rst) count<=4'd0;
else if(cen)
begin
if(count<=4'd8) count<=4'd0;
else count<=count+4'd1;
end
end
assign q = count;
endmodule

## Clock signal
set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 }
[get_ports {clk }]; #IO_L12P_T1_MRCC_35 Sch=clk100mhz
create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5}
[get_ports {clk}];

## Reset Signal
set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 }
[get_ports { rst }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1]
## Count Enable Signal (cen)
set_property -dict { PACKAGE_PIN H18 IOSTANDARD LVCMOS33 }
[get_ports { cen }]; #IO_L6N_T0_D08_VREF_14 Sch=sw[2]

## Output Pins for 4-bit Counter (q)


set_property -dict { PACKAGE_PIN T22 IOSTANDARD LVCMOS33 }
[get_ports { q[0] }]; #IO_L18P_T2_A24_15 Sch=led[0]
set_property -dict { PACKAGE_PIN T21 IOSTANDARD LVCMOS33 }
[get_ports { q[1] }]; #IO_L24P_T3_RS1_15 Sch=led[1]
set_property -dict { PACKAGE_PIN U22 IOSTANDARD LVCMOS33 }
[get_ports { q[2] }]; #IO_L17N_T2_A25_15 Sch=led[2]
set_property -dict { PACKAGE_PIN U21 IOSTANDARD LVCMOS33 }
[get_ports { q[3] }]; #IO_L8P_T1_D11_14 Sch=led[3]
Q) detecting 111 sequence using moore state machine

Verilog code:-

module moorem(ip,clk,op,rst);
input ip,clk,rst;
output op;
reg op;
parameter S0=0, S1=1, S2=2, S3=3;
reg [1:0] cs,ns;
always@ (posedge clk or posedge rst)
begin
if(rst)
cs=S0;
else cs=ns;
end
always@ (cs)
case(cs)
S0:begin
op=0;
if(ip) ns=S1; else ns=S0;
end
S1: begin
op=0;
if(ip) ns=S2; else ns=S0;
end
S2: begin
op=0;
if(ip) ns=S3; else ns=S0;
end
S3:begin
op=1;
if(ip) ns=S3; else ns=S0 ;
end
default: ns=S0 ;
endcase
endmodule

test bench:-
module moorem_tb;
reg ip,clk,rst;
wire op;
moorem m1(ip,clk,op,rst);
initial
begin
ip=1;
#4
ip=1;
#2
ip=0;
#3
ip=1;
#2
ip=1;
#2
ip=1;
end
always
begin
if(clk)
#2 clk=1'b0;
else #2 clk=1'b1;
end
initial
begin
rst=1;
#5
rst=0;
end
endmodule
Udc:-
Verilog code:-

module udc4(clk,rst,cen,upd,q);

input clk,rst,cen,upd;

output[3:0]q;

reg[3:0]count;

always@(posedge clk or posedge rst)

begin

if(rst) count=4'd0;

else if(cen)

begin

if(upd) count<=count+4'd1;

else count=count-4'd1;

end

end

assign q=count;

endmodule

test bench:-
module udc4_tb();
reg clk,rst,cen,upd;

wire[3:0]count;

udc4 c1(clk,rst,cen,upd,count);

always #10 clk=~clk;

initial

begin

clk=1'b0;rst=1'b1;cen=1'b1;upd=1'b1;

#20 rst=1'b0;

#200 upd=1'b0;

#200 cen=1'b0;

#100 cen=1'b1;

#100 upd=1'b1;

#200 rst=1'b1;

#60 rst=1'b0;

#100 $finish;

end

endmodule

XDC:-
## Clock Signal

set_property PACKAGE_PIN M15 [get_ports clk]

set_property IOSTANDARD LVCMOS33 [get_ports clk]

## Reset Signal

set_property PACKAGE_PIN H17 [get_ports rst]

set_property IOSTANDARD LVCMOS33 [get_ports rst]

## Count Enable Signal (cen)


set_property PACKAGE_PIN H18 [get_ports cen]

set_property IOSTANDARD LVCMOS33 [get_ports cen]

## Up/Down Signal (upd)

set_property PACKAGE_PIN H19 [get_ports upd]

set_property IOSTANDARD LVCMOS33 [get_ports upd]

## Output Pins for 4-bit Counter (q)

set_property PACKAGE_PIN T22 [get_ports {q[0]}]

set_property IOSTANDARD LVCMOS33 [get_ports {q[0]}]

set_property PACKAGE_PIN T21 [get_ports {q[1]}]

set_property IOSTANDARD LVCMOS33 [get_ports {q[1]}]

set_property PACKAGE_PIN U22 [get_ports {q[2]}]

set_property IOSTANDARD LVCMOS33 [get_ports {q[2]}]

set_property PACKAGE_PIN U21 [get_ports {q[3]}]

set_property IOSTANDARD LVCMOS33 [get_ports {q[3]}]


6. a.Verilog modeling and FPGA implementation of Ring counter and Johnson
Counter

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