Student Submission in Experiment No.

Course Code: CPE 016 Program: BSCPE

Course Title: Introduction to HDL Date Performed: 9/30/24
Section: CPE31S1 Date Submitted: 10/5/24
Name: Carale, Alyzza Instructor: Engr. Menchie Rosales
Mantaring, Rylle Airon
1. Objective(s):
The activity aims to demonstrate the procedures on how to simulate the concurrent process statement.
2. Intended Learning Outcomes (ILOs):
The students shall be able to:
2.1 Test the step-by-step procedure in running the use of concurrent process statement VHDL
codes.

3. Resources:
Computer System with internet access

4. Procedure:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity signedunsigned12 is
end entity;

architecture sim of signedunsigned12 is

signal unscnt : unsigned(7 downto 0) := (others
=>'0'); signal sigcnt : signed(7 downto 0) := (others
=>'0');

signal uns4 : unsigned(3 downto 0) := "1000";

signal sig4 : signed(3 downto 0) := "1000";

signal uns8 : unsigned(7 downto 0) := (others

=>'0'); signal sig8 : signed(7 downto 0) := (others
=>'0');

begin
process is
begin
wait for 10 ns;
--wrapping counter
unscnt <= unscnt +1;
sigcnt <= sigcnt +1;
 --adding signals
uns8 <= uns8 + uns4;
sig8 <= sig8 + sig4;
end process;
end architecture;

2. What happened? Edit the code just like

below: -- Code your testbench here
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;

entity signedunsigned12 is
end signedunsigned12;

architecture behav2 of signedunsigned12 is

signal unscnt: unsigned(7 downto
0):=(others=>'0'); signal sigcnt: signed(7 downto
0):=(others=>'0');

signal uns4 : unsigned(3 downto 0) := "1000";

signal sig4 : signed(3 downto 0) := "1000";

signal uns8 : unsigned(7 downto 0) := (others =>'0');

signal sig8 : signed(7 downto 0) := (others =>'0');

begin
process is
begin
wait for 10 ns;
--wrapping counter
unscnt <= unscnt +1;
sigcnt <= sigcnt +1;
wait for 10ns;
--adding signals
uns8 <= uns8 + uns4;
sig8 <= sig8 + sig4;
wait for 10 ns;
wait;
--wrapping counter
--unscnt <= unscnt +1;
--sigcnt <= sigcnt +1;
--adding signals
--uns8 <= uns8 + uns4;
--sig8 <= sig8 + sig4;
end process;
 end behav2;
3. What is the difference between the codes? Did it run?
It should look like this:

EXPLANATION: This code shows the difference between signed and unsigned values. We
declared here signed and unsigned signals which are sigcnt, sig4 and si8, and unscnt, uns4
and uns8, respectively. Both the uns4 and sig4 starts at 0 and is incremented by 1 as you can
see in the process.

0 8 16 32 ……. Signed identify 1 as negative while unsigned normally adding numbers.

Then 1000 equals 8 in decimal.

4. Copy the following codes to the testbench area in EDA Playground: Debug and run.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity T13_ConcurrentProcsTb is
end entity;

architecture sim of T13_ConcurrentProcsTb is

signal Uns : unsigned(5 downto 0) := (others => '0'); --Uns is unsigned variable which
was initialized to zero
--The statement "Others => '0'" is a feature of the VHDL when the coder want to defined several
items in an array with the same value.
signal Mul1 : unsigned(7 downto 0);
signal Mul2 : unsigned(7 downto 0);
signal Mul3 : unsigned(7 downto 0);
begin
process is
begin
wait for 10 ns;
Uns <= Uns + 1; --increment by 1 every 10 ns
wait for 10 ns;
wait;
end process;
--Process multiplying Uns by 4
process is
begin
Mul1 <= Uns & "00"; --the Uns 6 bits was added two zeros to have 8 bits
wait on Uns; --the program will wait here until the 6-bit signal changes
--when this happens it will wake up
end process;
--Equivalent process using sensitivity list
process(Uns) is

begin
Mul2 <= Uns & "00"; --the Uns 6 bits was added two zeros to have 8 bits

end process;
--Equivalent process using a concurrent statement and is the same as the other process with
wait statement
Mul3 <= Uns & "00";
end architecture;

5. You can see a similar output like in Fig. 5.1.

Figure 5.1 Working Collapsed Signal Variable

Learnings:
In multiplying the unsigned numbers by 4 you can use “& ”00”. Something like when you add
1 plus 00 becomes “100” which is 4. This is what you called bit shifting as shown on the next
figure
 0010 => 1000
0011 => 1100
And so on…
As noticed, the program process used a sensitivity list and another process way of writing a
process but the output is still the same. However, there will be an error if the sensitivity list
process has a wait statement.
The concurrent process is simply an assignment to a signal with an architecture part of the VHDL
file but outside the process like “Mul3 <= Uns & “00”. This concurrent signal is equivalent to the
process and sensitivity list.
6. For Exercise No. 8-1, what if the bits will shift to the right? What will you do?
Clue: you may or not change the following:
7 downto 0
Uns <= Uns + 1;

12. subtype NATURAL is integer range 0 to integer'high;

5. Activity (Write your answer here what is asked for each Exercise/s in Activity section)
5.1 By referring to step number 5 above. After running it without errors, paste the screenshot of
the codes and its output Waveform.
5.2 Discuss each process from no. 1 and no. 4 codes. Where is the multiplier circuit? Why it
became a multiplier and why it became a shifting of binary values.

6. Questions: (Write your answer here what is asked for each Exercise/s in Questions section)

Where is the multiplier circuit? Why it became a multiplier and why it became a shifting of binary values.
(from Activity)
The multiplier circuit is represented by the line of code that appends "00" to the Uns signal, specifically in
the process: Mul1 <= Uns & "00";
This operation performs a bit-shifting to the left by two positions, which is equivalent to multiplying the
unsigned value by 4. In binary arithmetic, shifting bits to the left by n positions results in multiplying the
original value by 2^n. In this case, adding "00" shifts the binary value by two places, which corresponds
to multiplying it by 4. This is because shifting the binary value 0010 (which is 2 in decimal) to the left
becomes 1000, which is 8 in decimal, showing the effect of multiplying by 4.
The code became a multiplier because in binary, shifting to the left increases the value by powers of two,
which is mathematically equivalent to multiplication. Conversely, if we had shifted the bits to the right, it
would perform division instead of multiplication.

Differentiate the codes from the first waveform output and the last waveform output. What makes it
different?
The difference between the first waveform output and the last waveform output lies in the process timing
and the specific way the signals are updated. In the first output, both the signed and unsigned counters
(sigcnt and unscnt) increment simultaneously every 10 ns, and the signal addition operations (adding
uns4 to uns8 and sig4 to sig8) occur in the same process. This results in the wrapping counters updating
together and showing consistent behavior for signed and unsigned operations.
In contrast, the second code introduces additional wait statements, causing a delay between the
updates. In this version, after incrementing the counters, there’s a 10 ns pause before the addition
operations are executed. The added wait statement creates a more staggered timing for the operations,
which results in different signal behaviors being reflected in the waveform.
This difference in timing creates variations in the waveform outputs, as the signals update at different
intervals. The key distinction is the separation of operations over time in the second code, compared to
the first where everything happens in a tighter sequence.

7. VHDL codes with design and test bench (paste here the screenshot of the created VHDL
codes for each Exercise/s)
Note: Do not forget to include one sentence explanation for each and write the title for each figure
FIGURE 1
 FIGURE 2

Explanation: The Two Figure Above shows the usage of Concurrent Process in VHDL Figure one shows
that the signals uses wrapping counter while the other one uses Multiplying by 4ns.

8. Output (paste here the screenshot of the output waveform or EPWave)

Note: Do not forget to include one sentence explanation for each and write the title for each figure
FIGURE 1

FIGURE 2
 9. Analysis and Reflection: (Individually write your name with your paragraph)

Carale, Alyzza
➔ This experiment allowed me to better understand the behavior of concurrent processes in VHDL
and the way signed and unsigned signals are handled during operations. By using bit-shifting, I
observed how multiplying unsigned values by four can be simplified through appending "00" to the
binary value, which results in a shift. The processes written in various formats, including using a
sensitivity list and a concurrent assignment, were insightful because even though the format
differed, the outcome was identical. However, the sensitivity list cannot contain a wait statement,
which is a crucial distinction. This exercise reinforced how concurrency in VHDL allows for multiple
processes to occur simultaneously, which is vital for efficient hardware design. Additionally,
working with the unsigned and signed data types provided me with a deeper understanding of how
binary arithmetic functions. I now feel more confident in applying these concepts to more complex
hardware designs, especially when dealing with signal processing.

Mantaring, Rylle Airon

➔ In summary, concurrent processing is an effective tool in contemporary computing, but in order to
fully realise its advantages, its application necessitates careful evaluation of possible drawbacks.
Concurrency may significantly increase a system's scalability and performance when used
properly, especially in settings where parallel execution and multitasking are crucial

10. Assessment: (refer to the given rubric)