Paavai Engineering College Department of ECE

UNIT –III
MICROPROCESSORS

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CONTENTS
S. No. Name of the Content Page No.
Technical Terms 3.3
3.1 Introduction to Microprocessor 3.6
3.2 Bus 3.6
3.2.1 3.2.1 Address bus 3.6
3.6
3.2.2 3.2.2 Data bus

3.2.3 Control bus 3.6

3.3 Connecting Microprocessor to I/O devices 3.7

3.4 Introduction to 8085 3.9
3.4.1 Pin Configuration 3.9
3.5 8085 Architecture 3.11
3.6 Addressing Modes & Interrupts 3.15
3.7 Instruction Sets 3.17
3.8 Introduction to 8086 3.20
3.9 8086 Architecture 3.20

3.10 Addressing mode 3.26

3.11 Instruction Set 3.11

3.12 Assembler Directives Interrupts 3.45
Question Bank 3.59
Web links 3.60

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TECHNICAL TERMS

Technical Literal
S.No Technical Meaning Digester
Terms Meaning
It is a kind
microprocessor, any of a type
of integrated
of miniature electronic device
circuit can
that contains https://www.bri
interpret and
the arithmetic, logic, and tannica.com/tec
1 Microprocessor execute program
control circuitry necessary to hnology/microp
instructions as
perform the functions of a rocessor
well as handle
digital computer’s central
arithmetic
processing unit.
operations.
Architecture is a set of rules
https://www.tut
Architecture is and methods that describe the
orialspoint.com
the design of functionality, organization,
2 Architecture /what-is-
microprocessors and implementation of
computer-
. computer systems.
architecture

The term
addressing The addressing mode
modes refers to specifies a rule for https://www.ge
Addressing the way in interpreting or modifying the eksforgeeks.org
3
modes which the address field of the instruction /addressing-
operand of an before the operand is actually modes/
instruction is executed.
specified.

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The native language of the

computer is referred as
https://www.pc
A statement of instruction set. It must be
mag.com/encyc
4 Instruction Set programming presented to the computer as
lopedia/term/in
language binary-coded machine
struction
instructions that are specific to
that CPU family.
Assembler is a program for
converting instructions
An assembler is https://www.ge
written in low-level assembly
a program that eksforgeeks.org
code into relocatable machine
converts /introduction-
5 Assembler code and generating along
the assembly of-
information for the loader. It
language into assembler/?ref=
takes the basic commands and
machine code . gcse
operations from assembly
code
An interrupt is a condition
Interrupt is an that halts the microprocessor https://www.ge
event or signal temporarily to work on a eksforgeeks.org
6 Interrupt that request to different task and then return /interrupts-in-
attention of to its previous task. This halt 8086-
CPU. allows peripheral devices to microprocessor/
access the microprocessor.
ISR is a Whenever an interrupt occurs
https://www.ge
program that the processor completes the
Interrupt eksforgeeks.org
tells the execution of the current
7 Service /interrupts-in-
processor what instruction and starts the
Routines 8086-
to do when the execution of an Interrupt
microprocessor/
interrupt occurs. Service Routine (ISR)

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Operand is a part of an
The quantity on instruction /directive that http://en.wikipe
8 Operand which the represents a value on which dia
operation to be theinstruction acts. .org/wiki/Asse
done. mbly_language
A person who An assembler is a program
assembles a which is used to translate
Assembler machine or its assembly language mnemonics http://en.wikipe
9
parts. to the correct binary code for dia
each instruction. .org/wiki/assem
ble
It is a computer program that
converts the programs written
Compiler in high level language to http://en.wikipe
10
machine language. dia
.org/wiki/compi
ler

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3.1 Introduction to Microprocessor

Due to advancements in microelectronics technology, it became possible to put ALU and
Control Unit on a single IC chip. This IC chip is called Microprocessor. The Microprocessor is
considered a major revolution in the field of computers. It has also been made possible to integrate
ALU, ControlUnit and Memory on a single chip. This IC chip is called Microcomputer.

3.2 BUS

A bus is a Collection of Wires. A bus is defined as a path over which digital information is
transferred from any of the several sources to any of the several destinations. It can be dielectric
medium or a set of physical wires carrying the signal. A microprocessor chip has thus an address
bus, a data bus and a control bus.
3.2.1 Address Bus

The address bus is unidirectional since address locations are sent by microprocessor to
memory and I/O devices.
3.2.2 Data Bus

The data bus is bidirectional as the microprocessor accepts as well as sends data

3.2.3 Control Bus

The control bus falls into the following two categories:

(a) Control signals like Read from Memory or I/O or Write to memory or I/O are output
bymicroprocessor to memory or I/O devices.
(b) Control signals like Interrupt Request, DMA request, Reset, Halt, etc are sent to
microprocessor by I/O devices.
Thus the control bus is bi-directional. However, unlike the data bus, any particular line will
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have information flow in one direction only.

3.3 Connecting Microprocessor with Input/Output DevicesI/O Mapped I/O interface

Figure.3.1 Input/Output DevicesI/O Mapped I/O interface

In the figure 3.1 shown the connection between microprocessor, I/O devices and memory.
The I/O devices are identified by port numbers, and memory locations are identified by addresses.
The memory read/write operations and I/O read/Write operations are performed by different
software instructions. Whether the read/ write operations are being performed on memory or I/O or
in other words whether the information on address and data lines is meant for a memory location or
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an I/O device – the identification is done by separate signals. Thus, when read from an I/O device
instruction is executed, the I/O signal is ON and the address on the address bus is decoded as the
port number and an I/O device is selected. In case of read/write form memory, the MEMORY signal
is ON and a particular location of memory is selected. In figure 1 the port number of devices 1,2,3
and 4 are 00, 01, 02 and 03 respectively. Because of separate memory and I/O signals, there is no
confusion between device address and memory address. This is called I/O mapped I/O interface
since I/O devices are treated separately from memory.
Memory mapped I/O interface

Figure.3.2 Memory mapped I/O interface

Let us now see the figure 2, which is identical to figure 1 except that the signals I/O and
MEMORY are not present. Now when a read memory instruction is executed, there is no
MEMORY signal to indicate that the address bus contains the memory location address. If this
memory location address is the same as that of a port number of an I/O device, an I/O device will
also get selected together with the memory read operation being performed. Thus there will be
confusion between memory location and I/O device having the same address and port number. In
Figure 2 when one wishes to read from device 1 (port no 00) memory location 00 will also get
selected. However if we sacrifice some memory location for the sake of I/O devices, this problem
would not arise. It means that the I/O addresses ( port number) and the memory addresses will not
be the same. In figure 2 if the memory starts form address 04 onwards, then there would not be any

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problem.
3.4 INTRODUCTION TO 8085
8085 is an 8-bit microprocessor as it operates on 8 bits at a time and is created with N-MOS
technology. This microprocessor exhibits some unique characteristics and this is the reason it still
holds popularity among the microprocessors. 8085 is pronounced as "eighty-eighty-five"
microprocessor. It is an 8-bit microprocessor designed by Intel in 1977 using NMOS
technology.
It has the following configuration −
• 8-bit data bus
• 16-bit address bus, which can address upto 64KB
• A 16-bit program counter
• A 16-bit stack pointer
• Six 8-bit registers arranged in pairs: BC, DE, HL
• Requires +5V supply to operate at 3.2 MHZ single phase clock
It is used in washing machines, microwave ovens, mobile phones, etc.
3.4.1 8085 Pin Configuration

The following image depicts the pin diagram of 8085 Microprocessor –

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Figure.3.3 Pin configuration of 8085

The pins of a 8085 microprocessor can be classified into seven groups −
Address bus
A15-A8, it carries the most significant 8-bits of memory/IO address.
Data bus
AD7-AD0, it carries the least significant 8-bit address and data bus.
Control and status signals
These signals are used to identify the nature of operation. There are 3 control signal and 3
status signals.
Three control signals are RD, WR & ALE.
• RD − This signal indicates that the selected IO or memory device is to be read and is
ready for accepting data available on the data bus.
• WR − This signal indicates that the data on the data bus is to be written into a selected
memory or IO location.
• ALE − It is a positive going pulse generated when a new operation is started by the
microprocessor. When the pulse goes high, it indicates address. When the pulse goes down it
indicates data.
Three status signals are IO/M, S0 & S1.
IO/M
This signal is used to differentiate between IO and Memory operations, i.e. when it is high
indicates IO operation and when it is low then it indicates memory operation.
S1 & S0
These signals are used to identify the type of current operation.
Power supply
There are 2 power supply signals − VCC & VSS. VCC indicates +5v power supply and VSS
indicates ground signal.
Clock signals
There are 3 clock signals, i.e. X1, X2, CLK OUT.

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• X1, X2 − A crystal (RC, LC N/W) is connected at these two pins and is used to set
frequency of the internal clock generator. This frequency is internally divided by 2.
• CLK OUT − This signal is used as the system clock for devices connected with the
microprocessor.
Interrupts & externally initiated signals
Interrupts are the signals generated by external devices to request the microprocessor to
perform a task. There are 5 interrupt signals, i.e. TRAP, RST 7.5, RST 6.5, RST 5.5, and INTR. We
will discuss interrupts in detail in interrupts section.
• INTA − It is an interrupt acknowledgment signal.
• RESET IN − This signal is used to reset the microprocessor by setting the program
counter to zero.
• RESET OUT − This signal is used to reset all the connected devices when the
microprocessor is reset.
• READY − This signal indicates that the device is ready to send or receive data. If
READY is low, then the CPU has to wait for READY to go high.
• HOLD − This signal indicates that another master is requesting the use of the address
and data buses.
• HLDA (HOLD Acknowledge) − It indicates that the CPU has received the HOLD
request and it will relinquish the bus in the next clock cycle. HLDA is set to low after the HOLD
signal is removed.
Serial I/O signals
There are 2 serial signals, i.e. SID and SOD and these signals are used for serial
communication.
• SOD (Serial output data line) − The output SOD is set/reset as specified by the SIM
instruction.
• SID (Serial input data line) − The data on this line is loaded into accumulator
whenever a RIM instruction is executed.

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3.5 8085-ARCHITECTURE

Fig.3.4 8085 Architecture

8085 Microprocessor – Functional Units
Accumulator
It is an 8-bit register used to perform arithmetic, logical, I/O & LOAD/STORE operations. It
is connected to internal data bus & ALU.
Arithmetic and logic unit
As the name suggests, it performs arithmetic and logical operations like Addition,
Subtraction, AND, OR, etc. on 8-bit data.

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General purpose register

There are 6 general purpose registers in 8085 processor, i.e. B, C, D, E, H & L. Each register
can hold 8-bit data.
These registers can work in pair to hold 16-bit data and their pairing combination is like B-C,
D-E & H-L.
Program counter
It is a 16-bit register used to store the memory address location of the next instruction to be
executed. Microprocessor increments the program whenever an instruction is being executed, so
that the program counter points to the memory address of the next instruction that is going to be
executed.
Stack pointer
It is also a 16-bit register works like stack, which is always incremented/decremented by 2
during push & pop operations.
Temporary register
It is an 8-bit register, which holds the temporary data of arithmetic and logical operations.
Flag register
It is an 8-bit register having five 1-bit flip-flops, which holds either 0 or 1 depending upon the
result stored in the accumulator.
These are the set of 5 flip-flops −
• Sign (S)
• Zero (Z)
• Auxiliary Carry (AC)
• Parity (P)
• Carry (C)
Its bit position is shown in the following table −

D D D D D D D D
7 6 5 4 3 2 1 0

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C
S Z C P
Y

Instruction register and decoder

It is an 8-bit register. When an instruction is fetched from memory then it is stored in the
Instruction register. Instruction decoder decodes the information present in the Instruction register.
Timing and control unit
It provides timing and control signal to the microprocessor to perform operations. Following
are the timing and control signals, which control external and internal circuits −
• Control Signals: READY, RD’, WR’, ALE
• Status Signals: S0, S1, IO/M’
• DMA Signals: HOLD, HLDA
• RESET Signals: RESET IN, RESET OUT
Interrupt control
As the name suggests it controls the interrupts during a process. When a microprocessor is
executing a main program and whenever an interrupt occurs, the microprocessor shifts the control
from the main program to process the incoming request. After the request is completed, the control
goes back to the main program.
There are 5 interrupt signals in 8085 microprocessor: INTR, RST 7.5, RST 6.5, RST 5.5,
TRAP.

Serial Input/output control

It controls the serial data communication by using these two instructions: SID (Serial input
data) and SOD (Serial output data).
Address buffer and address-data buffer
The content stored in the stack pointer and program counter is loaded into the address buffer
and address-data buffer to communicate with the CPU. The memory and I/O chips are connected to
these buses; the CPU can exchange the desired data with the memory and I/O chips.

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Address bus and data bus

Data bus carries the data to be stored. It is bidirectional, whereas address bus carries the
location to where it should be stored and it is unidirectional. It is used to transfer the data & Address
I/O devices.
3.6 8085 Addressing Modes & Interrupts
Addressing Modes in 8085
These are the instructions used to transfer the data from one register to another register, from
the memory to the register, and from the register to the memory without any alteration in the
content. Addressing modes in 8085 is classified into 5 groups −
Immediate addressing mode
In this mode, the 8/16-bit data is specified in the instruction itself as one of its operand. For
example: MVI K, 20F: means 20F is copied into register K.
Register addressing mode
In this mode, the data is copied from one register to another. For example: MOV K, B:
means data in register B is copied to register K.
Direct addressing mode
In this mode, the data is directly copied from the given address to the register. For
example: LDB 5000K: means the data at address 5000K is copied to register B.
Indirect addressing mode
In this mode, the data is transferred from one register to another by using the address pointed
by the register. For example: MOV K, B: means data is transferred from the memory address
pointed by the register to the register K.
Implied addressing mode
This mode doesn’t require any operand; the data is specified by the opcode itself. For
example: CMP.
Interrupts in 8085
Interrupts are the signals generated by the external devices to request the microprocessor to
perform a task. There are 5 interrupt signals, i.e. TRAP, RST 7.5, RST 6.5, RST 5.5, and INTR.
Interrupt are classified into following groups based on their parameter −
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• Vector interrupt − In this type of interrupt, the interrupt address is known to the
processor. For example: RST7.5, RST6.5, RST5.5, TRAP.
• Non-Vector interrupt − In this type of interrupt, the interrupt address is not known to
the processor so, the interrupt address needs to be sent externally by the device to perform
interrupts. For example: INTR.
• Maskable interrupt − In this type of interrupt, we can disable the interrupt by writing
some instructions into the program. For example: RST7.5, RST6.5, RST5.5.
• Non-Maskable interrupt − In this type of interrupt, we cannot disable the interrupt
by writing some instructions into the program. For example: TRAP.
• Software interrupt − In this type of interrupt, the programmer has to add the
instructions into the program to execute the interrupt. There are 8 software interrupts in 8085, i.e.
RST0, RST1, RST2, RST3, RST4, RST5, RST6, and RST7.
• Hardware interrupt − There are 5 interrupt pins in 8085 used as hardware interrupts,
i.e. TRAP, RST7.5, RST6.5, RST5.5, INTA.
Note − NTA is not an interrupt, it is used by the microprocessor for sending
acknowledgement. TRAP has the highest priority, then RST7.5 and so on.
Interrupt Service Routine (ISR)
A small program or a routine that when executed, services the corresponding interrupting
source is called an ISR.
TRAP
It is a non-maskable interrupt, having the highest priority among all interrupts. Bydefault, it is
enabled until it gets acknowledged. In case of failure, it executes as ISR and sends the data to
backup memory. This interrupt transfers the control to the location 0024H.
RST7.5
It is a maskable interrupt, having the second highest priority among all interrupts. When this
interrupt is executed, the processor saves the content of the PC register into the stack and branches
to 003CH address.

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RST 6.5
It is a maskable interrupt, having the third highest priority among all interrupts. When this
interrupt is executed, the processor saves the content of the PC register into the stack and branches
to 0034H address.
RST 5.5
It is a maskable interrupt. When this interrupt is executed, the processor saves the content of
the PC register into the stack and branches to 002CH address.
INTR
It is a maskable interrupt, having the lowest priority among all interrupts. It can be disabled
by resetting the microprocessor.
When INTR signal goes high, the following events can occur −
• The microprocessor checks the status of INTR signal during the execution of each
instruction.
• When the INTR signal is high, then the microprocessor completes its current
instruction and sends active low interrupt acknowledge signal.
• When instructions are received, then the microprocessor saves the address of the next
instruction on stack and executes the received instruction.

3.7 8085 Instruction Sets

S.No. Instruction & Description

Control Instructions
Following is the table showing the list of Control instructions
1
with their meanings.

Logical Instructions
Following is the table showing the list of Logical instructions
2
with their meanings.

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Branching Instructions
Following is the table showing the list of Branching
3
instructions with their meanings.

Arithmetic Instructions
Following is the table showing the list of Arithmetic
4
instructions with their meanings.

Data Transfer Instructions

Following is the table showing the list of Data-transfer
5
instructions with their meanings.

Instruction sets are instruction codes to perform some task. It is classified into five categories.
8085 – Simple Programs
Now, let us take a look at some program demonstrations using the above instructions −
Adding Two 8-bit Numbers
Write a program to add data at 3005H & 3006H memory location and store the result at
3007H memory location.
Problem demo −
(3005H) = 14H
(3006H) = 89H
Result −
14H + 89H = 9DH
The program code can be written like this −
LXI H 3005H : "HL points 3005H"
MOV A, M : "Getting first operand"
INX H : "HL points 3006H"
ADD M : "Add second operand"
INX H : "HL points 3007H"

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MOV M, A : "Store result at 3007H"

HLT : "Exit program"
Exchanging the Memory Locations
Write a program to exchange the data at 5000M& 6000M memory location.
LDA 5000M : "Getting the contents at5000M location into accumulator"
MOV B, A : "Save the contents into B register"
LDA 6000M : "Getting the contents at 6000M location into accumulator"
STA 5000M : "Store the contents of accumulator at address 5000M"
MOV A, B : "Get the saved contents back into A register"
STA 6000M : "Store the contents of accumulator at address 6000M"
Arrange Numbers in an Ascending Order
Write a program to arrange first 10 numbers from memory address 3000H in an ascending
order.
MVI B, 09 :"Initialize counter"
START :"LXI H, 3000H: Initialize memory pointer"
MVI C, 09H :"Initialize counter 2"
BACK: MOV A, M :"Get the number"
INX H :"Increment memory pointer"
CMP M :"Compare number with next number"
JC SKIP :"If less, don’t interchange"
JZ SKIP :"If equal, don’t interchange"
MOV D, M
MOV M, A
DCX H
MOV M, D
INX H :"Interchange two numbers"
SKIP:DCR C :"Decrement counter 2"
JNZ BACK :"If not zero, repeat"

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DCR B :"Decrement counter 1"

JNZ START
HLT :"Terminate program execution"

3.8 INTRODUCTION TO 8086

It is a semiconductor device consisting of electronic logic circuits manufactured by using
either a Large scale (LSI) or Very Large Scale (VLSI) Integration Technique.
It includes the ALU, register arrays and control circuits on a single chip. The microprocessor
has a set of instructions, designed internally, to manipulate data and communicate with peripherals.
The 16-bit Microprocessor families are designed primarily to complete with microcomputers
and are oriented towards high-level languages. They have powerful instruction sets and capable of
addressing mega bytes of memory. The era of 16-bit Microprocessors began in 1974 with the
introduction of PACE chip by National Semiconductor. The Texas Instruments TMS9900 was
introduced in the year 1976. The Intel 8086 commercially available in the year 1978, Zilog Z800 in
the year 1979, The Motorola MC68000 in the year 1980.
The 16-bit Microprocessors are available in different pin packages. Ex: Intel 8086/8088 40
pin package Zilog Z8001 40 pin package, Digital equipment LSI-II 40 pin package, Motorola
MC68000 64 pin package National Semiconductor NS16000 48 pin package.
The primary objectives of this 16-bit Microprocessor can be summarized as follows.
1. Increase memory addressing capability
2. Increase execution speed
3. Provide a powerful instruction set
4. Facilitate programming in high-level languages.
3.9 8086 INTERNAL ARCHITECTURE
The 8086 CPU is divided into two independent functional parts, the Bus interface unit (BIU)
and execution unit (EU).
The Bus Interface Unit contains Bus Interface Logic, Segment registers, Memory
addressing logic and a Six byte instruction object code queue. The BIU sends out address, fetches
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the instructions from memory, read data from ports and memory, and writes the data to ports and
memory.
The execution unit: contains the Data and Address registers, the Arithmetic and Logic Unit,
the Control Unit and flags. tells the BIU where to fetch instructions or data from, decodes
instructions and executes instruction. The EU contains control circuitry which directs internal
operations. A decoder in the EU translates instructions fetched from memory into a series of actions
which the EU carries out. The EU is has a 16-bit ALU which can add, subtract, AND, OR, XOR,
increment.

Figure3.5 Internal Architecture of 8086 Microprocessor

Features of 8086 Microprocessor
1) 8086 has 16-bit ALU; this means 16-bit numbers are directly processed by 8086.
2) It has 16-bit data bus, so it can read data or write data to memory or I/O ports either 16
Bitsor 8 bits at a time.
3) It has 20 address lines, so it can address up to 220 i.e. 1048576 = 1Mbytes of memory
(Words

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i.e. 16 bit numbers are stored in consecutive memory locations).

Due to the 1Mbytes memory size multiprogramming is made feasible as well as several
Multiprogramming features have been incorporated in 8086 design.
4) 8086 includes few features, which enhance multiprocessing capability (it can be used
with mathcoprocessors like 8087, I/O processor 8089 etc.
5)
6) Operates on +5v supply and single phase (single line) clock frequency (Clock is
7) 8086 comes with different versions. 8086 runs at 5 MHz, 8086-2 runs at 8 MHz, 8086-
1 runsat 10 MHz.
8) It comes in 40-pin configuration with HMOS technology having around 20,000
transistors inits circuitry.
9) It has multiplexed address and data bus like 8085 due to which the pin count is
Reducedconsiderably.
10) Higher T h r o u g h p u t ( Speed). This is achieved by a concept Called Pipelining.
Instruction Queue
To increase the execution speed, BIU fetches as many as six instruction bytes ahead to time
from memory. The prefetched instruction bytes are held for the EU in a first in first out group of
registers called a instruction queue. When the EU is ready for its next instruction, it simply
reads the instruction from this instruction queue. This is much faster than sending out an address to
the system memory and to send back the next instruction byte. Fetching the next instruction while
thecurrent instruction executes is called pipelining.
Segment Registers
The BIU contains four 16-bit segment registers. They are: the extra segment (ES) register, the
code segment (CS) register, the data segment (DS) register and the stack segment (SS) register.
The segment registers are used to hold the upper 16 bits of the starting address for each of the
segments. The part of a segment starting address stored in a segment register is often called the
segment base.
1. Code Segment (CS): The CS register is used for addressing a memory location in the
Code Segment of the memory, where the executable program is stored.
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2. Data Segment (DS): The DS contains most data used by program. Data are
accessed in the Data Segment by an offset address or the content of other register that holds the
offset address.
3. Stack Segment (SS): SS defined a section of memory to store addresses and data
while asubprogram executes.
4. Extra Segment (ES): ES is additional data segment that is used by some of the string
to hold theextra destination data.
Instruction Pointer (IP)

In the BIU, the next register, below the segment register is instruction pointer The instruction
pointer (IP) holds the 16-bit address of the next code byte within this codesegment.

Figure 3.6 Memory Segments of 8086

The Execution Unit

The execution unit (EU) tells the BIU where to fetch instructions or data from,
decodes instructions, and executes instructions.

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The functional parts of the execution unit are control circuitry or system, instruction decoder,
and Arithmetic logic unit (ALU). Control circuitry to perform various internal operations. A
decoder in the EU translates instructions fetched from memory to generate different internal or
external control signals that required performing the operation. The EU has a 16-bit ALU, which
can perform arithmetic operations such as add, subtract etc. and logical operations such as AND,
OR, XOR, increment, decrement etc.
Flag Register
A 16-bit flag register is a flip-flop which indicates some condition produced by the execution
of an instruction or controls certain operations of the EU. They are modified automatically by CPU
after mathematical operations. It has 9 flags and they are divided into two categories:
1. Conditional Flags
2. Control Flags
Conditional Flags
Conditional flags represent result of last arithmetic or logical instructions.
Carry Flag (CF): This flag will be set to one if the arithmetic operation produces the carry in
MSB position. It is also used in multiple-precision arithmetic.
Auxiliary Flag (AF): If an operation performed in ALU generates a carry/barrow from lower
nibble (i.e. D0 – D3) to upper nibble (i.e. D4 – D7), the AF flag is set i.e. carry given by D3 bit to
D4 is AF flag. This is not a general-purpose flag; it is used internally by the processor to perform
Binary to BCD conversion.
Parity Flag (PF): This flag is used to indicate the parity of result. If lower order 8-bits of the
result contains even number of 1‟s, the Parity Flag is set to one and for odd number of 1‟s, the
Parity Flag is reset i.e. zero.
Zero Flag (ZF): It is set to one; if the result of arithmetic or logical operation is zero else it is
reset. Sign Flag (SF): In sign magnitude format the sign of number is indicated by MSB bit. If the
result ofoperation is negative, sign flag is set to one.
Overflow Flag (OF): It occurs when signed numbers are added or subtracted. An OF
indicates thatthe result has exceeded the capacity of machine.
Control Flags
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Control flags are intentionally set or reset to control certain operations of the processor with
specific instructions put in the program from the user. Control flags are as follows:
1. Trap Flag (TP): It is used for single step control. It allows user to execute one
instruction of a program at a time for debugging. When trap flag is set, program can be run in single
step mode.
2. Interrupt Flag (IF): It is an interrupt enable/disable flag, i.e. used to allow/prohibit
the interruption of a program. If it is set, the maskable interrupt is enabled and if it is reset, the
interruptis disabled.
3. Direction Flag (DF): It is used in string operation. If it is set, string bytes are accessed
from higher memory address to lower memory address. When it is reset, the string bytes are
accessed from lower memory address to higher memory address.

Figure 3.7 Flag Register of 8086

CF: Contains carry out of MSB of result PF: Indicates if result has even parity AF: Contains
carry out of bit 3 in AL ZF: Indicates if result equals zero
SF: Indicates if result is negative
OF: Indicates that an overflow occurred in resultIF: Enable/Disables interrupts
DF: Control pointer updates during string operations TF: provides single step capability for
debugging General Purpose Registers
The EU has eight general purpose registers labeled AH, AL, BH, BL, CH, CL, DH, and DL.
These registers can be used individually for temporary storage of 8-bit data. The AL register is also
called the accumulator. Certain pairs of these general purpose registers can be used together to
store 16-bit data. The valid register pairs are AH and AL, BH and BL, CH and CL and DH and DL.
These register pairs is referred to the AX, BX, CX, and DX resp.
1. AX Register: For 16-bit operations, AX is called the accumulator register that stores
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operands for arithmetic operations.

2. BX Register: This register is mainly used as a base register. It holds the starting base
location of a memory region within a data segment.
3. CX Register: It is defined as a counter. It is primarily used in loop instruction to store
loopcounter.
4. DX Register: DX register is used to contain I/O port address for I/O instruction.
5. Stack Pointer Register
The stack pointer (SP) register contains the 16-bit offset from the start of the segment to the
location where a word was most recently stored is called the top of stack.
Pointers and index registers.
The pointers contain within the particular segments. The pointers IP, BP, SP usually contain
offsetswithin the code, data and stack segments respectively
Stack Pointer (SP) is a 16-bit register pointing to program stack in stack segment.
Base Pointer (BP) is a 16-bit register pointing to data in stack segment. BP register is usually
used forbased, based indexed or register indirect addressing.
Source Index (SI) is a 16-bit register. SI is used for indexed, based indexed and register
indirectaddressing, as well as a source data addresses in string manipulation instructions.
Destination Index (DI) is a 16-bit register. DI is used for indexed, based indexed and register
indirectaddressing, as well as a destination data address in string manipulation instructions.
3.10 ADDRESSING MODES
The 8086 has 12 addressing modes can be classified into five groups.
• Addressing modes for accessing immediate and register data (register and immediate
modes).
• Addressing modes for accessing data in memory (memory modes)
• Addressing modes for accessing I/O ports (I/O modes)
• Relative addressing mode
• Implied addressing mode
Immediate addressing mode:
In this mode, 8 or 16 bit data can be specified as part of the instruction - OP Code Immediate
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OperandExample 1: MOV CL, 03 H:Moves the 8 bit data 03 H into CL Example 2:

MOV DX, 0525 H: Moves the 16 bit data 0525 H into DX
In the above two examples, the source operand is in immediate mode and the destination
operand is inregister mode.
A constant such as ―VALUE‖ can be defined by the assembler EQUATE directive such as
VALUE EQU35H
Example: MOV BH, VALUE Used to load 35 H into BH
Register addressing mode:
The operand to be accessed is specified as residing in an internal register of 8086.
Table 1.1 below shows internal registers, anyone can be used as a source or destination
operand, however onlythe data registers can be accessed as either a byte or word.

Example 1: MOV DX (Destination Register) , CX (Source Register) Which moves 16 bit

content of CSinto DX.
Example 2: MOV CL, DL
Moves 8 bit contents of DL into CL MOV BX,CH is an illegal instruction.

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* The register sizes must be the same.

Direct addressing mode:
The instruction Opcode is followed by an affective address, this effective address is directly
used as the 16 bit offset of the storage location of the operand from the location specified by the

current
The 20 bit physical address of the operand in memory is normally obtained as PA =DS: EA.
But by using a segment override prefix (SOP) in the instruction, any of the four segment registers
can be referenced,

Fig 3.8 Physical address generation of 8086

The Execution Unit (EU) has direct access to all registers and data for register and immediate
operands.However the EU cannot directly access the memory operands.
It must use the BIU, in order to access memory operands.
In the direct addressing mode, the 16 bit effective address (EA) is taken directly from the
displacement fieldof the instruction.

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Example 1: MOV CX, START

If the 16 bit value assigned to the offset START by the programmer using an assembler
pseudo instruction such as DW is 0040 and [DS] = 3050. Then BIU generates the 20 bit physical
address 30540 H.
The content of 30540 is moved to CL The content of 30541 is moved to CH
Example 2: MOV CH,START
If [DS] = 3050 and START = 0040 8 bit content of memory location 30540 is moved to CH.
Example 3: MOV START, BX
With [DS] = 3050, the value of START is 0040.Physical address: 30540
MOV instruction moves (BL) and (BH) to locations 30540 and 30541 respectively.
Register indirect addressing mode:
The EA is specified in either pointer (BX) register or an index (SI or DI) register. The 20 bit
physical address is computed using DS and EA.
Example: MOV [DI], BX register indirect
If [DS] = 5004, [DI] = 0020, [Bx] = 2456 PA=50060.
The content of BX(2456) is moved to memory locations 50060 H and 50061 H.

when memory is accessed PA is computed from BX and DS when the stack is accessed
PA is computedfrom BP and SS.
Example: MOV AL, START[BX] or
MOV AL, [START +
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BX] based mode

EA: [START] + [BX]
PA: [DS] + [EA]
The 8 bit content of this memory location is moved to AL.
String addressing mode:
The string instructions automatically assume SI to point to the first byte or word of the source
operand and DI to point to the first byte or word of the destination operand. The contents of SI and
DI are automatically incremented (by clearing DF to 0 by CLD instruction) to point to the next byte
or word.
Example: MOV S BYTE
If [DF] = 0, [DS] = 2000 H, [SI] = 0500, [ES] = 4000, [DI] = 0300
Source address: 20500, assume it contains 38PA: [DS] + [SI]
Destination address: [ES] + [DI] = 40300, assume it contains 45

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I/O mode (direct):

Port number is an 8 bit immediate operand. Example:OUT 05 H, AL
Outputs [AL] to 8 bit port 05 H
I/O mode (indirect):
The port number is taken from DX.Example 1: IN AL, DX If [DX] = 5040
8 bit content by port 5040 is moved into AL.Example 2: IN AX, DX
Inputs 8 bit content of ports 5040 and 5041 into AL and AH respectively.
Relative addressing mode:
Example: JNC START
If CY=O, then PC is loaded with current PC contents plus 8 bit signed value of START,
otherwise the nextinstruction is executed.
Implied addressing mode:
Instruction using this mode have no operands. Example: CLC which clears carry flag to zero.

3.11 INSTRUCTION SET OF 8086

The 8086 instructions are categorized into the following main types.
1. Data Copy / Transfer Instructions

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2. Arithmetic and Logical Instructions

3. Shift and Rotate Instructions
4. Loop Instructions
6. String Instructions
7. Flag Manipulation Instructions
8. Machine Control Instructions
Data Copy / Transfer Instructions:
MOV:
This instruction copies a word or a byte of data from some source to a destination.
The destination can be a register or a memory location. The source can be a register, a
memory location, oran immediate number.
MOV AX, BX MOV AX, 5000H MOV AX, [SI] MOV AX, [2000H] MOV AX, 50H[BX]
MOV [734AH], BX MOV DS, CX MOV CL, [357AH]
Direct loading of the segment registers with immediate data is not permitted.
PUSH: Push to Stack
This instruction pushes the contents of the specified register/memory location on to the stack.
The stackpointer is decremented by 2, after each execution of the instruction.
E.g. PUSH AX
• PUSH DS
• PUSH [5000H]
POP: Pop from Stack
This instruction when executed, loads the specified register/memory location with the
contents of the memory location of which the address is formed using the current stack segment and
stack pointer.
by 2 Eg. POP AX POPDS
POP [5000H]

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Fig 3.10 Push into and Popping Register Content from Stack MemoryXCHG: Exchange
byte or word
This instruction exchange the contents of the specified source and destination operands Eg.
XCHG [5000H], AX
XCHG BX, AX
XLAT:
Translate byte using look-up table Eg.LEA BX, TABLE1
MOV AL, 04HXLAT

Input and output port transfer instructions:IN:

Eg. IN AL,03H INAX,DX OUT:
Copy a byte or word from accumulator specified port. Eg.OUT 03H, AL
OUT DX, AX
LEA:
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Load effective address of operand in specified register. [reg]offset portion of address in DS

Eg. LEA reg, offset
LDS:
Load DS register and other specified register from memory. [reg][mem]
[DS] [mem + 2]
Eg. LDS reg, mem
LES:
Load ES register and other specified register from memory. [reg][mem]
[ES] [mem + 2]
Eg. LES reg, mem
Flag transfer instructions:
LAHF:
Load (copy to) AH with the low byte the flag register. [AH][ Flags low byte]
Eg. LAHF
SAHF:
Store (copy) AH register to low byte of flag register. [Flagslow byte] [AH]
Eg. SAHF
Copy flag register to top of stack. [SP][SP] – 2
[[SP]] [Flags] Eg.PUSHF POPF:
Copy word at top of stack to flag register.[Flags] [[SP]]
[SP] [SP] + 2
Arithmetic Instructions:
The 8086 provides many arithmetic operations: addition, subtraction, negation, multiplication
and comparingtwo values.
ADD:
The add instruction adds the contents of the source operand to the destination operand. Eg.
ADDAX, 0100H
ADD AX, BX ADDAX, [SI] ADD AX, [5000H]
ADD [5000H],0100H ADD
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0100H
ADC: Add with Carry
This instruction performs the same operation as ADD instruction, but adds the carry flag to
the result. Eg.ADC
0100H ADC AX, BX ADC AX, [SI]ADC AX, [5000]

SUB: Subtract
The subtract instruction subtracts the source operand from the destination operand and the
result is left inthe destination operand.
Eg. SUB AX, 0100HSUB AX, BX
SUB AX, [5000H] SUB[5000H], 0100H
SBB: Subtract with Borrow
The subtract with borrow instruction subtracts the source operand and the borrow flag (CF)
which mayreflect the result of the previous calculations, from the destination operand
Eg. SBB AX, 0100HSBB AX, BX
SBB AX, [5000H] SBB[5000H], 0100H
INC: Increment
This instruction increases the contents of the specified Register or memory location by 1.
Immediate datacannot be operand of this instruction.
Eg. INC AX INC [BX] INC[5000H]
DEC: Decrement
The decrement instruction subtracts 1 from the contents of the specified register or memory
location. Eg.DEC AX
DEC [5000H]
The negate instruction forms 2‘s complement of the specified destination in the instruction.
The destination can be a register or a memory location. This instruction can be implemented by
inverting each bit and adding 1 to it.
Eg. NEG AL
AL = 0011 0101 35H Replace number in AL with its 2‘s complement AL =1100 1011 = CBH
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CMP: Compare
This instruction compares the source operand, which may be a register or an immediate
data or a memorylocation, with a destination operand that may be a register or a memory location
Eg. CMP BX, 0100HCMP AX,
0100H CMP [5000H],
0100H CMP BX, [SI]CMP BX, CX
MUL:Unsigned Multiplication Byte or Word
This instruction multiplies an unsigned byte or word by the contents of AL. Eg. MUL BH;
(AX) (AL) x(BH)
MUL CX; (DX)(AX) (AX) x (CX)
MUL WORD PTR [SI]; (DX)(AX) (AX) x ([SI])
IMUL:Signed Multiplication
This instruction multiplies a signed byte in source operand by a signed byte in AL or a
signed word insource operand by a signed word in AX.
Eg. IMUL BH IMUL CXIMUL [SI]

CBW: Convert Signed Byte to Word to be sign extension of AL. Eg.CBW

AX= 0000 0000 1001 1000 Convert signed byte in AL signed word in AX. Result in AX =
1111 1111 1001 1000
CWD: Convert Signed Word to Double Word
This instruction copies the sign of a byte in AL to all the bits in AH. AH is then said to be
sign extension ofAL.
Eg. CWD
Convert signed word in AX to signed double word in DX:AX DX= 1111 1111 1111 1111
Result in AX = 1111 0000 1100 0001
DIV: Unsigned division
This instruction is used to divide an unsigned word by a byte or to divide an unsigned double
word by aword.
Eg. DIV CL; Word in AX / byte in CL; Quotient in AL, remainder in AH
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DIV CX; Double word in DX and AX / word; in CX, and Quotient in AX; remainder in DX
AAA: ASCII Adjust After Addition
The AAA instruction is executed after an ADD instruction that adds two ASCII coded
operand to give abyte of result in AL. The AAA instruction converts the resulting contents of Al to
a unpacked decimal digits.
Eg. ADD CL, DL; [CL] = 32H = ASCII for 2; [DL] = 35H = ASCII for 5;
Result [CL] = 67H
MOV AL, CL; Move ASCII result into AL since; AAA adjust only [AL] AAA; [AL]=07,
unpacked BCD for 7
AAS: ASCII Adjust AL after Subtraction
This instruction corrects the result in AL register after subtracting two unpacked ASCII
operands. The result is in unpacked decimal format. The procedure is similar to AAA instruction
except for the subtraction of 06 from AL.
AAM: ASCII Adjust after Multiplication
unpacked BCD format. Eg.MOV AL, 04; AL =04
MOV BL ,09; BL =09 MUL BL;AX = AL*BL; AX=24H AAM; AH = 03, AL=06

AAD: ASCII Adjust before Division

This instruction converts two unpacked BCD digits in AH and AL to the equivalent binary
number in AL. This adjustment must be made before dividing the two unpacked BCD digits in AX
by an unpacked BCD byte. In the instruction sequence, this instruction appears Before DIV
instruction.
Eg. AX 05 08
AAD result in AL 00 3A 58D = 3A H in AL
The result of AAD execution will give the hexadecimal number 3A in AL and 00 in AH
where 3A is thehexadecimal Equivalent of 58 (decimal).
DAA: Decimal Adjust Accumulator
This instruction is used to convert the result of the addition of two packed BCD numbers to a
valid BCDnumber. The result has to be only in AL.
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Eg. AL = 53 CL = 29
ADD AL, CL; AL (AL) + (CL); AL 53 + 29; AL 7C DAA;AL 7C + 06 (as C>9); AL 82
DAS: Decimal Adjust after Subtraction
This instruction converts the result of the subtraction of two packed BCD numbers to a valid
BCD number.The subtraction has to be in AL only.
Eg. AL = 75, BH = 46
SUB AL, BH; AL 2 F = (AL) - (BH) ; AF = 1 DAS;AL 2 9 (as F>9, F - 6 = 9)
Logical instructionsAND: Logical AND
This instruction bit by bit ANDs the source operand that may be an immediate register or a
memory location to the destination operand that may a register or a memory location. The result is
stored in the destination operand.
Eg. AND AX,0008H ANDAX,BX
OR: Logical OR
This instruction bit by bit ORs the source operand that may be an immediate, register or a
memory location to the destination operand that may a register or a memory location. The result is
stored in the destination operand.
Eg. OR AX,0008H ORAX,BX
NOT: Logical Invert
This instruction complements the contents of an operand register or a memory location, bit by
bit. Eg.NOT AX
NOT [5000H]
OR: Logical Exclusive OR
This instruction bit by bit XORs the source operand that may be an immediate, register
or a memory location to the destination operand that may a register or a memory location. The
result is stored in the destination operand.
Eg. XOR AX,0098H XORAX,BX
TEST: Logical Compare Instruction
The TEST instruction performs a bit by bit logical AND operation on the two operands. The
result of this ANDing operation is not available for further use, but flags are affected.
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Eg. TEST AX, BX TEST[0500], 06H

Shift and Rotate Instructions
SAL and SHL are two mnemonics for the same instruction. This instruction shifts each bit in
the specified destination to the left and 0 is stored at LSB position. The MSB is shifted into the
carry flag. The destination can be a byte or a word. It can be in a register or in a memory location.
The number of shifts is indicated by count.
Eg. SAL CX, 1 SALAX, CL
SHR: SHR destination, count
This instruction shifts each bit in the specified destination to the right and 0 is stored at MSB
position. TheLSB is shifted into the carry flag. The destination can be a byte or a word.
It can be a register or in a memory location. The number of shifts is indicated by count. Eg.
SHR CX, 1
MOV CL, 05H SHRAX, CL
SAR: SAR destination, count
This instruction shifts each bit in the specified destination some number of bit positions to the
right. As a bit is shifted out of the MSB position, a copy of the old MSB is put in the MSB position.
The LSB will be shifted into CF.
Eg. SAR BL, 1 MOVCL, 04H SAR DX, CL

ROL Instruction: ROL destination, count

This instruction rotates all bits in a specified byte or word to the left some number of bit
positions. MSB isplaced as a new LSB and a new CF.
Eg. ROL CX, 1 MOVCL, 03H ROL BL, CL
ROR Instruction: ROR destination, count
This instruction rotates all bits in a specified byte or word to the right some number of bit
positions. LSB isplaced as a new MSB and a new CF.
MOV CL, 03H RORBL, CL
RCL Instruction: RCL destination, count
This instruction rotates all bits in a specified byte or word some number of bit positions to the
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left alongwith the carry flag. MSB is placed as a new carry and previous carry is place as new LSB.
Eg. RCL CX, 1 MOVCL, 04H RCL AL, CL
RCR Instruction: RCR destination, count
This instruction rotates all bits in a specified byte or word some number of bit positions to the
right along with the carry flag. LSB is placed as a new carry and previous carry is place as new
MSB.Eg. RCR CX, 1
MOV CL, 04H RCRAL, CL
ROR Instruction: ROR destination, count
This instruction rotates all bits in a specified byte or word to the right some number of bit
positions. LSB isplaced as a new MSB and a new CF.
Eg. ROR CX, 1 MOVCL, 03H ROR BL, CL
RCL Instruction: RCL destination, count
This instruction rotates all bits in a specified byte or word some number of bit positions to the
left alongwith the carry flag. MSB is placed as a new carry and previous carry is place as new LSB.
Eg. RCL CX, 1 MOVCL, 04H RCL AL, CL
RCR Instruction: RCR destination, count
This instruction rotates all bits in a specified byte or word some number of bit positions to the
right
along with the carry flag. LSB is placed as a new carry and previous carry is place as new
MSB.
MOV CL, 04H RCRAL, CL
Loop Instructions: Unconditional LOOP Instructions LOOP: LOOPUnconditionally
This instruction executes the part of the program from the Label or address specified in the
instruction upto the LOOP instruction CX number of times. At each iteration, CX is decremented
automatically and JUMP IF NOT ZERO structure.
Example: MOV CX, 0004HConditional LOOP Instructions LOOPZ / LOOPE Label
Loop through a sequence of instructions from label while ZF=1 and CX=0.
LOOPNZ / LOOPENE Label
Loop through a sequence of instructions from label while ZF=1 and CX=0.
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Branch Instructions:
Branch Instructions transfers the flow of execution of the program to a new address specified
in the instruction directly or indirectly. When this type of instruction is executed, the CS and IP
registers get loaded with new values of CS and IP corresponding to the location to be transferred.
The Branch Instructions are classified into two types
1. Unconditional Branch Instructions.
2. Conditional Branch Instructions.
Unconditional Branch Instructions:
Unconditional control transfer instructions, the execution control is transferred to the
specified location independent of any status or condition. The CS and IP are unconditionally
modified to the new CS and IP.
CALL: Unconditional Call
This instruction is used to call a Subroutine (Procedure) from a main program.
types of procedure depending upon whether it is available in the same segment or in another
segment.
i. Near CALL i.e., ±32K displacement.
ii. For CALL i.e., anywhere outside the segment.
On execution this instruction stores the incremented IP & CS onto the stack and loads the CS
& IP registers with segment and offset addresses of the procedure to be called.
RET: Return from the Procedure.
At the end of the procedure, the RET instruction must be executed. When it is executed, the
previously stored content of IP and CS along with Flags are retrieved into the CS, IP and Flag
registers from the stack and execution of the main program continues further.
INT N: Interrupt Type N.
In the interrupt structure of 8086, 256 interrupts are defined corresponding to the types from
00H to FFH. When INT N instruction is executed, the type byte N is multiplied by 4 and the
contents of IP and CS of the interrupt service routine will be taken from memory block in 0000
segment.

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INTO: Interrupt on Overflow

This instruction is executed, when the overflow flag OF is set. This is equivalent to a Type 4
Interrupt instruction.
JMP: Unconditional Jump
This instruction unconditionally transfers the control of execution to the specified address
using an 8- bit or 16-bit displacement. No Flags are affected by this instruction.
IRET: Return from ISR
When it is executed, the values of IP, CS and Flags are retrieved from the stack to continue
the execution ofthe main program.
MOV BX, 7526H
Label 1 MOV AX, CODEOR BX, AX
LOOP Label 1
Conditional Branch Instructions
specified relatively in the instruction, provided the condition implicit in the Opcode is
satisfied. Otherwiseexecution continues sequentially.
JZ/JE Label
Transfer execution control to address ‗Label‘, if ZF=1.
JNZ/JNE Label
Transfer execution control to address ‗Label‘, if ZF=0
JS Label
Transfer execution control to address ‗Label‘, if SF=1.
JNS Label
Transfer execution control to address ‗Label‘, if SF=0.
JO Label
Transfer e xecution control to address ‗Label‘, if OF=1. 14
JNO Label
Transfer execution control to address ‗Label‘, if OF=0.
JNP Label
Transfer execution control to address ‗Label‘, if PF=0.
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JP Label
Transfer execution control to address ‗Label‘, if PF=1.
JB Label
Transfer execution control to address ‗Label‘, if CF=1.
JNB Label
Transfer execution control to address ‗Label‘, if CF=0.
JCXZ Label
Transfer execution control to address ‗Label‘, if CX=0
String Manipulation Instructions
A series of data byte or word available in memory at consecutive locations, to be referred as
Byte String orWord String. A String of characters may be located in consecutive memory locations,
supports a set of more powerful instructions for string manipulations for referring to a string,
two parameters are required.
I. Starting and End Address of the String.
II. II. Length of the String.
The length of the string is usually stored as count in the CX register. The incrementing or
decrementing of the pointer, in string instructions, depends upon the Direction Flag (DF) Status. If it
is a Byte string operation, the index registers are updated by one. On the other hand, if it is a word
string operation, the index registers are updated by two.
REP: Repeat Instruction Prefix
This instruction is used as a prefix to other instructions, the instruction to which the REP
prefix is provided, is executed repeatedly until the CX register becomes zero (at each iteration CX is
automatically decremented by one).
i. REPE / REPZ - repeat operation while equal / zero.
ii. REPNE / REPNZ - repeat operation while not equal / not zero. These are used for
CMPS, SCAS instructions only, as instruction prefixes.
MOVSB / MOVSW: Move String Byte or String Word
Suppose a string of bytes stored in a set of consecutive memory locations is to be moved to
another set of destination locations. The starting byte of source string is located in the memory
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location whose address may be computed using SI (Source Index) and DS (Data Segment) contents.
The starting address of the destination locations where this string has to be relocated is given by DI
(Destination Index) and ES (Extra Segment) contents.
CMPS: Compare String Byte or String Word
The CMPS instruction can be used to compare two strings of byte or words. The length of the
string must be stored in the register CX. If both the byte or word strings are equal, zero Flag is set.
The REP instruction Prefix is used to repeat the operation till CX (counter) becomes zero or
the condition specified by the REP Prefix is False.
SCAN: Scan String Byte or String Word
This instruction scans a string of bytes or words for an operand byte or word specified in the
register AL or AX. The String is pointed to by ES: DI register pair. Whenever a match to the
specified operand is found in the string, execution stops and the zero F lag is set. If no match is
found, the zero flag is reset.
LODS: Load String Byte or String Word
The LODS instruction loads the AL / AX register by the content of a string pointed to by DS:
SI register pair. The SI is modified automatically depending upon DF, If it is a byte transfer
(LODSB), the SI is modified by one and if it is a word transfer (LODSW), the SI is modified by
two. No other Flags are affected by this instruction.
STOS: Store String Byte or String Word
The STOS instruction Stores the AL / AX register contents to a location in the string pointer
by ES: DI register pair. The DI is modified accordingly, No Flags are affected by this instruction.
The direction Flag controls the String instruction execution, The source index SI and
Destination Index DI are modified after each iteration automatically. If DF=1, then the execution
follows auto decrement mode, SI and DI are decremented automatically after each iteration. If
DF=0, then the execution follows auto increment mode. In this mode, SI and DI are incremented
automatically after each iteration.
Flag Manipulation and a Processor Control Instructions
These instructions control the functioning of the available hardware inside the processor chip.
Theseinstructions are categorized into two types:
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1. Flag Manipulation instructions.

2. Machine Control instructions.
Flag Manipulation instructions
The Flag manipulation instructions directly modify some of the Flags of 8086.
i. CLC – Clear Carry Flag.
ii. CMC – Complement Carry Flag.
iii. STC – Set Carry Flag.
iv. CLD – Clear Direction Flag.
v. STD – Set Direction Flag.
vi. CLI – Clear Interrupt Flag.
vii. STI – Set Interrupt Flag.
The Machine control instructions control the bus usage and execution
i. WAIT – Wait for Test input pin to go low.
ii. HLT – Halt the process.
iii. NOP – No operation.
iv. ESC – Escape to external device like NDP
v. LOCK – Bus lock instruction prefix.

3.12 ASSEMBLER DIRECTIVES:

Assembler directives help the assembler to correctly understand the assembly language
programs to prepare the codes. Another type of hint which helps the assembler to assign a particular
constant with a label or initialize particular memory locations or labels with constants is called an
operator. Rather, the operators perform the arithmetic and logical tasks unlike directives that just
direct the assembler to correctly interpret the program to code it appropriately. The following
directives are commonly used in the assembly language programming practice using Microsoft
Macro Assembler (MASM) or Turbo Assembler (TASM).
DB: Define Byte
The DB directive is used to reserve byte or bytes of memory locations in the available
memory. While preparing the EXE file, this directive directs the assembler to allocate the specified
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number of memory bytes to the said data type that may be a constant, variable, string, etc. Another
option of this directive also initializes the reserved memory bytes with the ASCII codes of the
characters specified as a string. The following examples show how the DB directive is used for
different purposes.
Example:
LIST DB 0lH, 02H, 03H, 04H
This statement directs the assembler to reserve four memory locations for a list named
LISTand initialize them with the above specified four values.
MESSAGE DB 'GOOD MORNING'
This makes the assembler reserve the number of bytes of memory equal to the number of
characters in the string named MESSAGE and initialize those locations by the ASCII equivalent of
these characters.
Some examples are given to explain this directive. Examples
WORDS DW 1234H, 4567H, 78ABH, 045CH
This makes the assembler reserve four words in memory (8 bytes), and initialize the words
with the specified values in the statements. During initialisation, the lower bytes are stored at the
lower memory addresses, while the upper bytes are stored at the higher addresses.
Another option of the DW directive is explained with the DUP operator. WDATA DW
5 DUP (6666H)
This statement reserves five words, i.e. 10-bytes of memory for a word label WDATA and
initializes all the word locations with 6666H.
DQ: Define Quad word This directive is used to direct the assembler to reserve 4words (8
bytes) of memory for the specified variable and may initialize it with the specified values.
DT: Define Ten Bytes. The DT directive directs the assembler to define the specified
variable requiring la- bytes for its storage and initialize the 10bytes with the specified values. The
directive may be used in case of variables facing heavy numerical calculations, generally processed
by numerical processors.
ASSUME: Assume Logical Segment Name The ASSUME directive is used to inform the
assembler, the names of the logical segments to be assumed for different segments used in the
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program. In the assembly language program, each segment is given a name. For example, the code
segment may be given the name CODE, data segment may be given the name DATA etc. The
statement ASSUME CS: CODE directs the assembler that the machine codes are available in a
segment named CODE, and hence the CS register is to be loaded with the address (segment) allotted
by the operating system for the label CODE, while loading. Similarly, ASSUME DS: DATA
indicates to the assembler that the data items related to the program, are available in a logical
segment named DATA, and the DS register is to be initialized by the segment address value decided
by the operating system for the data segment, while loading. It then considers the segment DATA as
a default data segment for each memory operation, related to the data and the segment CODE
as a must at the starting of each assembly language program,
END: END of Program The END directive marks the end of an assembly language
program. When the assembler comes across this END directive, it ignores the source lines available
later on. Hence, it should be ensured that the END statement should be the last statement in the file
and should not appear in between. No useful program statement should lie in the file, after the END
statement ENDP: END of Procedure. In assembly language programming, the subroutines are
called procedures. Thus, procedures may be independent program modules which return particular
results or values to the calling programs. The ENDP directive is used to indicate the end of a
procedure. A procedure is usually assigned a name, i.e. label. To mark the end of a particular
procedure, the name of the procedure, i.e. label may appear as a prefix with the directive ENDP. The
statements, appearing in the same module but after the ENDP directive, are neglected from that
procedure. The structure given below explains the use of ENDP.
PROCEDURE STAR
STAR ENDP
ENDS: END of Segment This directive marks the end of a logical segment. The logical
segments are assigned with the names using the ASSUME directive. The names appear with the
ENDS directive as prefixes to mark the end of those particular segments.
Whatever are the contents of the segments, they should appear in the program before ENDS.
Any statement appearing after ENDS will be neglected from the segment. The structure
shown below explains the fact more clearly.
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DATA SEGMENT
.
.
.
DATA ENDS ASSUME CS: CODE,
CODE ENDS END
The above structure represents a simple program containing two segments named DATA and
CODE. The data related to the program must lie between the DATA SEGMENT and DATA ENDS
statements. Similarly, all the executable instructions must lie between CODE SEGMENT and
CODE ENDS statements. EVEN: Align on Even Memory Address The assembler, while starting
the assembling procedure of any program, initializes a location counter and goes on updating it, as
the assembly proceeds. It goes on assigning the available addresses, i.e. the contents of the location
counter, sequentially to the program variables, constants and modules as per their requirements, in
the sequence in which they appear in the program. The EVEN directive updates the location counter
to the next even address if the current location counter contents are not even, and assigns the
following routine or variable or constant to that address. The structure given below explains the
directive.
EVEN PROCEDURE ROOT
.
.
.
ROOT ENDP
The above structure shows a procedure ROOT that is to be aligned at an even address. The
assembler will start assembling the main program calling ROOT. When the assembler comes across
the directive EVEN, it checks the contents of the location counter. If it is odd, it is updated to the
next even value and then the ROOT procedure is assigned to that address, i.e. the updated contents
of the location counter. If the content of the location counter is already even, then the ROOT
procedure will be assigned with the same address. This will result in the generation of wrong codes.
If the EQU directive is used to assign the value with a label that can be used in place of each
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recurrence of that constant, only one change in the show the syntax.Example
LABEL EQU 0500H ADDITION EQU ADD
The first statement assigns the constant 500H with the label LABEL, while the second
statement assignsanother label ADDITION with mnemonic ADD.
EXTRN: External and PUBLIC: Public The directive EXTRN informs the assembler that
the names, procedures and labels declared after this directive have already been defined in some
other assembly language modules. While in the other module, where the names, procedures and
labels actually appear, they must be declared public, using the PUBLIC directive. If one wants to
call a procedure FACTORIAL appearing in MODULE 1 from MODULE 2; in MODULE1, it must
be declared PUBLIC using the statement PUBLIC FACTORIAL and in module 2, it must be
declared external using the declaration EXTRN FACTORIAL. The statement of declaration
EXTRN must be accompanied by the SEGMENT and ENDS directives of the MODULE 1, before
it is called in MOBULE 2.
Thus the MODULE 1 and MODULE 2 must have the following declarations. MODULEl
SEGMENT
PUBLIC FACTORIAL FAR MODULEl ENDS MODULE2 SEGMENT EXTRN
FACTORIAL FAR MODULE2 ENDS
GROUP: Group the Related segment The directive is used to form logical groups of
segments with similar purpose or type. This directive is used to inform the assembler to form a
logical group of the following segment names. The assembler passes information to the
linker/loader to form the code such that the group declared segments or operands must lie within a
64Kbyte memory segment. Thus all such segments and labels can be addressed using the same
segment base.
PROGRAM GROUP CODE, DATA, STACK
CODE, DATA and STACK segment must lie within a 64kbyte memory segment that is
named as PROGRAM. Now, for the ASSUME statement, one can use the label PROGRAM rather
than CODE, DATA and STACK as shown.
ASSUME CS: PROGRAM, DS: PROGRAM, SS: PROGRAM.
LABEL: Label
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counter.
At the start of the assembly process, the assembler initializes a location counter to keep track
of memory locations assigned to the program. As the program assembly proceeds, the
contents of the location counter are updated. During the assembly process, whenever the
assembler comes across the LABEL directive, it assigns the declared label with the current
contents of the location counter. The type of the label must be specified, i.e. whether it is a
NEAR or a FAR label, BYTE or WORD label, etc. A LABEL directivemay be used to make a
FAR jump as shown below. A FAR jump cannot be made at a normal label with a colon. The
label CONTINUE can be used for a FAR jump, if the program contains the following
statement. CONTINUE LABEL FAR
The LABEL directive can be used to refer to the data segment along with the data type, byte
or word asshown.
DATA SEGMENT
DB 50H DUP (?) DATALASTLABEL BYTE FAR
DATA ENDS
After reserving 50H locations for DATAS, the next location will be assigned a label
DATALAST and itstype will be byte and far.
LENGTH: Byte Length of a Label
This directive is not available in MASM.
This is used to refer to the length of a data array or a string. MOV CX,LENGTH ARRAY
This statement, when assembled, will substitute the length of the array ARRAY in bytes, in
the instruction.
hat module. At a later time, some other module may declare a particular data type LOCAL,
which is previously declared LOCAL by another module or modules. Thus the same label may
serve different purposes for different modules of a program. With a single declaration statement, a
number of variables can be declared local, as shown.
LOCAL a, b, DATA, ARRAY, ROUTINE
NAME: Logical Name of a Module the NAME directive is used to assign a name to an
assembly language program module. The module may now be referred to by its declared name.
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The names, if selected to be suggestive, may point out the functions of the different modules and
hence may help in the documentation. OFFSET: Offset of a Label When the assembler comes
across the OFFSET operator along with a label, it first computes the 16-bit displacement (also
called as offset interchangeably) of the particular label, and replaces the string 'OFFSET
LABEL' by the computed displacement. This operator is used with arrays, strings, labels and
procedures to decide their offsets in their default segments. The segment may also bedecided by
another operator of similar type, viz., SEG. Its most common use is in the case of the indirect,
indexed, based indexed or other addressing techniques of similar types, used to refer to the
memoryindirectly. The examples of this operator are as follows:
Example:
CODE SEGMENT MOV SI, OFFSET LIST CODE ENDS

DATA SEGMENT LISTDB 10H DATA ENDS

ORG: Origin
The ORG directive directs the assembler to start the memory allotment for the particular
segment, block or code from the declared address in the ORG statement while starting the assembly
process for a module, the assembler initializes a location counter to keep track of the allotted
addresses for the module. If the ORG statement is not written in the program, the location counter
is initialized to module, then the code will start from 200H address in code segment) In other words,
the location counter will get initialized to the address 0200H instead of 0000H. Thus, the code for
different modules and segments can be located in the available memory as required by the
programmer. The ORG directive can even be used with data segments similarly.
PROC: Procedure
The PROC directive marks the start of a named procedure in the statement. Also, the types
NEAR or FAR specify the type of the procedure, i.e whether it is to be called by the main program
located within 64K of physical memory or not. For example, the statement RESULT PROC NEAR
marks the start of a routine RESULT, which is to be called by a program located in the Same
segment of memory. The FAR directive is used for the procedures to be called by the programs
located in different segments of memory. The example statements are as follows:
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Example
RESULT PROC NEARROUTINE PROC FAR
PTR: Pointer
The pointer operator is used to declare the type of a label, variable or memory operand. The
operator PTR is prefixed by either BYTE or WORD. If the prefix is BYTE, then the particular label,
variable or memory operand is treated as an 8-bit quantity, while if WORD is the prefix, then it is
treated as a 16- bit quantity. In other words, the PTR operator is used to specify the data type -byte
or word. The examples of the PTR operator are as follows:
Example:
MOV AL, BYTE PTR [SI]; Moves content of memory location addressed by SI (8-bit) to AL
INC BYTE PTR [BX]; Increments byte contents of memory location addressed by BX MOV BX,
WORD PTR [2000H]; Moves 16-bit content of memory location 2000H to BX, i.e. [2000H] to BL
[2001 H] to BH INC WORD PTR [3000H] - Increments word contents of memory location 3000H
considering contents of 3000H (lower byte) and 3001 H (higher byte) as a 16-bit number.
In case of JMP instructions, the PTR operator is used to specify the type of the jump, i.e. near
or far, as explained in the examples given below.
JMP WORD PTR [BX] -NEAR
Jump
PUBLIC As already discussed, the PUBLIC directive is used along with the EXTRN
directive. This informs the assembler that the labels, variables, constants, or procedures declared
PUBLIC may be accessed by other assembly modules to form their codes, but while using the
PUBLIC declared labels, variables, constants or procedures the user must declare them externals
using the EXTRN directive. On the other hand, the data types declared EXTRN in a module of the
program, may be declared PUBLIC in at least anyone of the other modules of the same program.
SEG: Segment of a Label
The SEG operator is used to decide the segment address of the label, variable, or procedure
and substitutes the segment base address in place of ‗SEG label‘. The example given below explain
the use of SEG operator.
Example
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MOV AX, SEG ARRAY; This statement moves the segment address
MOV DS, AX; of ARRAY in which it is appearing, to register AX and then to DS.
SEGMENT: Logical Segment
The SEGMENT directive marks the starting of a logical segment. The started segment is also
assigned a name, i.e. label, by this statement. The SEGMENT and ENDS directive must bracket
each logical segment of a program. In some cases, the segment may be assigned a type like PUBLIC
(i.e. can be used by other modules of the program while linking) or GLOBAL (can be accessed by
any other modules). The program structure given below explains the use of the SEGMENT
directive.
EXE . CODE SEGMENT GLOBAL; Start of segment named EXE.CODE, that can be
accessed by anyother module.
EXE . CODE ENDS; END of EXE.CODE logical segment.
SHORT
The SHORT operator indicates to the assembler that only one byte is required to code the
displacement fora jump (i.e. displacement is within -128 to +127 bytes from the address of the byte
next to the jump opcode). This method of specifying the jump address saves the memory.
Otherwise, the assembler may reserve two bytes for the displacement. The syntax of the statement is
as given below.
TYPE
The TYPE operator directs the assembler to decide the data type of the specified label and
replaces the 'TYPE label' by the decided data type. For the word type variable, the data type is 2, for
double word type, it is 4, and for byte type, it is 1. Suppose, the STRING is a word array. The
instruction MOV AX, TYPE STRING moves the value 0002H in AX.
GLOBAL
The labels, variables, constants or procedures declared GLOBAL may be used by other
modules of the program. Once a variable is declared GLOBAL, it can be used by any module in the
program. The following statement declares the procedure ROUTINE as a global label.
ROUTINE PROC GLOBAL

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ASSEMBLY LANGUAGE PROGRAMMING

ALP for addition of two 8-bit numbers ALP for Subtraction of two 8-bit
DATA SEGMENT numbers
VAR1 DB 85H DATA SEGMENT
VAR2 DB 32H VAR1 DB 53H
RES DB? VAR2 DB 2AH
DATA ENDS RES DB?
ASSUME CS:CODE, DS:DATA DATA ENDS
CODE SEGMENT ASSUME CS:CODE,DS:DATA
START: MOV AX, DATA CODE SEGMENT
MOV DS, AX START: MOV AX,DATA
MOV AL, VAR1 MOV DS,AX
MOV BL, VAR2 MOV AL,VAR1
ADD AL, BL MOV BL,VAR2
MOV RES, AL SUB AL,BL
MOV AH, 4CH MOV RES,AL
INT 21H MOV AH,4CH
CODE ENDS INT 21H
ALP for Multiplication of two 8-bit numbers
DATA SEGMENT VAR1 DB 0EDH VAR2DB 99H RES DW?
DATA ENDS
ASSUME CS: CODE, DS:DATACODE SEGMENT
START: MOV AX, DATA MOVDS, AX
MOV AL, VAR1 MOV BL, VAR2 MUL BL MOV RES, AX MOV AH, 4CH INT 21H
CODE ENDS END START
Classification of Interrupts
In general the interrupts can be classified in the following three ways:
1. Hardware and software interrupts
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2. Vectored and Non Vectored interrupt:

3. Maskable and Non Maskable interrupts.
The interrupts initiated by external hardware by sending an appropriate signal to the interrupt
pin of the processor is called hardware interrupt. The 8086 processor has two interrupt pins INTR
and NMI. The interrupts initiated by applying appropriate signal to these pins are called hardware
interrupts of 8086.
The software interrupts are program instructions. These instructions are inserted at desired
locations in a program. While running a program, if software interrupt instruction is encountered
then the processor initiates an interrupt. The 8086 processor has 256 types of software interrupts.
The software interrupt instruction is INT n, where n is the type number in the range 0 to 255.
When an interrupt signal is accepted by the processor, if the program control automatically
branches to a specific address (called vector address) then the interrupt is called vectored interrupt.
The automatic branching to vector address is predefined by the manufacturer of processors. (In
these vector addresses the interrupt service subroutines (ISR) are stored). In non-vectored interrupts
the interrupting device should supply the address of the ISR to be executed in response to the
interrupt. All the 8086 interrupts are vectored interrupts. The vector address for an 8086 interrupt is
obtained from a vector table implemented in the first 1kb memory space (00000h to 03FFFh).
The processor has the facility for accepting or rejecting hardware interrupts. Programming
the processor to reject an interrupt is referred to as masking or disabling and programming the
processor to accept an interrupt is referred to as unmasking or enabling. In 8086 the interrupt flag
(IF) can be set to one to unmask or enable all hardware interrupts and IF is cleared to zero to mask
or disable a hardware interrupts except NMI.
The interrupts whose request can be either accepted or rejected by the processor are called
maskable interrupts. The interrupts whose request has to be definitely accepted (or cannot be
rejected) by the processor are called non-maskable interrupts. Whenever a request is made by
non-maskable
interrupt, the processor has to definitely accept that request and service that interrupt by
suspending
its current program and executing an ISR. In 8086 processor all the
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 Paavai Engineering College Department of ECE

hardware

interrupts initiated through INTR pin are maskable by clearing interrupt flag (IF). The
interrupt initiated through NMI pin and all software interrupts are non-maskable.
Sources of Interrupts in 8086
An interrupt in 8086 can come from one of the following three sources.
1. One source is from an external signal applied to NMI or INTR input pin of the
processor. The interrupts initiated by applying appropriate signals to these input pins are called
hardware interrupts.
2. A second source of an interrupt is execution of the interrupt instruction "INT n", where
n is the type number. The interrupts initiated by "INT n" instructions are called software interrupts.
3. The third source of an interrupt is from some condition produced in the 8086 by the
execution ofan instruction. An example of this type of interrupt is divide by zero interrupt. Program
execution will be automatically interrupted if you attempt to divide an operand by zero. Such
conditional interrupts are also known as exceptions.
Interrupts of 8086
The 8086 microprocessor has 256 types of interrupts. INTEL has assigned a type number to
each interrupt. The type numbers are in the range of 0 to 255. The 8086 processor has dual facility
of initiating these 256 interrupts. The interrupts can be initiated either by executing "INT n"
instruction where n is the type number or the interrupt can be initiated by sending an appropriate
signal to INTR input pin of the processor.
For the interrupts initiated by software instruction" INT n ", the type number is specified by
the instruction itself. When the interrupt is initiated through INTR pin, then the processor runs an
interrupt acknowledge cycle to get the type number. (i.e., the interrupting device should supply the
type number through D0- D7 lines when the processor requests for the same through interrupt
acknowledge cycle).

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Fig. 3.10 Organization of Interrupt vector table in 8086

Only the first five types have explicit definitions; the other types may be used by interrupt
instructions or external interrupts. From the figure it is seen that the type associated with a division
error interrupt is 0. Therefore, if a division by 0 is attempted, the processor will push the current
contents of the PSW, CS and IP into the stack, fill the IP and CS registers from the addresses 00000
to 00003, and continue executing at the address indicated by the new contents of IP and CS. A
division error interrupt occurs any time a DIV or IDIV instruction is executed with the quotient
exceeding the range, regardless of the IF (Interrupt flag) and TF (Trap flag) status. The type 1
interrupt is the single-step interrupt (Trap interrupt) and is the only interrupt controlled by the TF
flag. If the TF flag is enabled, then an interrupt will occur at the end of the next instruction that will
cause a branch to the location indicated by the contents of 00004H to 00007H.The single step
interrupt is used primarily for debugging which gives the programmer a snapshot of his program
after each instruction is executed
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Paavai Engineering College Department of ECE

IRET is used to return from an interrupt service routine. It is similar to the RET instruction
except that it pops the original contents of the PSW from the stack as well as the return address. The
INT instruction has one of the forms INT or INT Type The INT instruction is also often used as a
debugging aid in cases where single stepping provides more detail than is wanted.
By inserting INT instructions at key points, called breakpoints. Within a program a
programmer can use an interrupt routine to provide messages and other information at these points.
Hence the 1 byte INT instruction (Type 3 interrupt) is also referred to as breakpoint interrupt.The
INTO instruction has type 4 and causes an interrupt if and only if the OF flag is set to 1. It is often
placed just after an arithmetic instruction so that special processing will be done if the instruction
causes an overflow. Unlike a divide-by-zero fault, an overflow condition does not cause an interrupt
automatically; the interrupt must be explicitly specified by the INTO instruction. The remaining
interrupt types correspond to interrupts instructions imbedded in the interrupt program or to external
interrupts.

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Paavai Engineering College Department of ECE

QUESTION BANK
PART A
1.
2. What is microprocessor? What is the difference between a MP and CPU?
3. What is bus?
4. Why the program counter and stack pointer are registers of 16 bit?
5. What is meant by pipelined architecture?
6. Give the power supply & clock frequency of 8085?
7. List the 16 – bit registers of 8085 microprocessor.
8. Mention the purpose of SID and SOD lines.
9. What is the function of IO/M signal in the 8085?
10. What is an Operand?
11. What are the functional units available in 8086 architecture?
12. What is the size of the address and data bus of 8086 microprocessor?
13. List the flags of 8086?
14. What are the different segment registers available in 8086 ?
15. How is physical address generated in 8086?
16. List the flag manipulation instructions?
17. How many interrupts are available in an 8086? How are they classified?
18. What are the maskable and non maskable interrupts in 8086?

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Paavai Engineering College Department of ECE

Part - B
1. Explain the architecture of 8085 Microprocessor in detail?
2. Explain the instruction set of 8086 Microprocessor in detail?
3. Explain the addressing modes of 8086 Microprocessor in detail?
4. Explain the architecture of 8086 Microprocessor in detail?
5. Explain about memory mapped Input/Output and I/O mapped I/O.
6. Explain with a neat diagram signals of 8086.
7. Explain the basic configurations of microprocessor 8086.
8. Explain about Interrupts and its service routine in detail?

WEB LINKS:
1. www.nptel.ac.in/downloads/106108100
2. freevideolectures.com › Electronics › IIT Kharagpur
3. onlinevideolecture.com/?course_id=385
4. http://freevideolectures.com/course/3018/Microprocessors-and-Microcontrollers/31
5. http://freevideolectures.com/Course/3018/Microprocessors-and-Microcontrollers#
6. https://www.youtube.com/watch?v=p9wxyIx-j-c

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