Scribd
Upload
42 views4 pages

Half Adder Structural Model

Uploaded by

rashmi
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
42 views4 pages

Half Adder Structural Model

Uploaded by

rashmi
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
You are on page 1/ 4

Half Adder Structural model Test Bench coding

library IEEE; library IEEE;


use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_1164.ALL;

entity and2 is entity hlfaddr_tb is


Port ( l : in BIT; end hlfaddr_tb;
m : in BIT;
n : out BIT); architecture dataflow of hlfaddr_tb is
end and2; signal a:BIT:='0';
architecture behavioral of and2 is signal b:BIT:='0';
begin signal sum:BIT;
n <= l and m; signal carry:BIT;
end behavioral;
begin
entity xor2 is uut : entity work.halfadder_vhdl
Port ( x : in BIT; port map(a=>a,
y : in BIT; b=>b,
z : out BIT); sum=>sum,
end xor2; carry=>carry);
architecture dataflow of xor2 is
begin process is
z <= x xor y; begin
end dataflow; a<='0';
b<='0';
entity halfadder_str is wait for 10ns;
Port ( a : in BIT; a<='0';
b : in BIT; b<='1';
sum : out BIT; wait for 10ns;
carry : out BIT); a<='1';
end halfadder_str; b<='0';
wait for 10ns;
architecture structural of halfadder_str is a<='1';
component xor2 b<='1';
port (x,y : in BIT; z: out BIT); wait for 10ns;
end component; end process;
component and2 end dataflow;
port (l,m: in BIT ; n: out BIT);
end component;

begin
x1: xor2 port map (a,b,sum);
a1: and2 port map (a,b,carry);
end structural;
Full Adder Structural model Test Bench coding
library IEEE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use IEEE.std_logic_1164.all;
entity HA is entity adder_process_tb is
Port ( A,B : in STD_LOGIC; end entity;
S,C : out STD_LOGIC); architecture tb of adder_ff_process_tb is
end HA; component FAdder is
architecture dataflow of HA is Port ( FA, FB, FC : in STD_LOGIC;
begin FS, FCA : out STD_LOGIC);
S <= A XOR B; end component;
C <= A AND B; signal FA, FB, FC, FS, FCA : STD_LOGIC;
end dataflow; begin
uut : FAdder port map(
entity ORGATE is FA =>FA, FB =>FB,
Port ( X,Y : in STD_LOGIC; FC => FC, FS => FS, FCA => FCA);
Z : out STD_LOGIC); stim : process
end ORGATE; begin
architecture dataflow of ORGATE is FA <= '0';
begin FB <= '0';
Z <= X OR Y; FC <= '0';
end dataflow; wait for 10 ns;
assert ((FS = '0') and (FCA = '0'))
entity FAdder is report "test failed for input combination 000"
severity error;
Port ( FA, FB, FC : in STD_LOGIC;
FS, FCA : out STD_LOGIC);
FA <= '0';
end FAdder;
FB <= '0';
FC <= '1';
architecture structural of FAdder is
wait for 10 ns;
component HA is assert ((FS = '1') and (FCA = '0'))
Port ( A,B : in STD_LOGIC; report "test failed for input combination 001"
severity error;
S,C : out STD_LOGIC);
end component;
FA <= '0';
component ORGATE is
FB <= '1';
Port ( X,Y: in STD_LOGIC;
FC <= '0';
Z: out STD_LOGIC);
wait for 10 ns;
end component;
assert ((FS = '1') and (FCA = '0'))
SIGNAL S0,S1,S2:STD_LOGIC;
report "test failed for input combination 010"
begin
severity error;
U1:HA PORT
MAP(A=>FA,B=>FB,S=>S0,C=>S1);
FA <= '0';
U2:HA PORT
MAP(A=>S0,B=>FC,S=>FS,C=>S2); FB <= '1';
U3:ORGATE PORT FC <= '1';
MAP(X=>S2,Y=>S1,Z=>FCA);
wait for 10 ns;
end structural;
assert ((FS = '0') and (FCA = '1'))
report "test failed for input combination 011"
severity error;

FA <= '1';
FB <= '0';
FC <= '0';
wait for 10 ns;
assert ((FS = '1') and (FCA = '0'))
report "test failed for input combination 100"
severity error;

FA <= '1';
FB <= '0';
FC <= '1';
wait for 10 ns;
assert ((FS = '0') and (FCA = '1'))
report "test failed for input combination 101"
severity error;

FA <= '1';
FB <= '1';
FC <= '0';
wait for 10 ns;
assert ((FS = '0') and (FCA = '1'))
report "test failed for input combination 110"
severity error;

FA <= '1';
FB <= '1';
FC <= '1';
wait for 10 ns;
assert ((FS = '1') and (FCA = '1'))
report "test failed for input combination 111"
severity error;
wait;

end process;
end tb;

You might also like