Low-Power Integrated Circuit Design Section 2: Nanometer Transistors and Their Models

Acknowledgement
This lecture note is from Low Power Design
Essentials by

1 Ali Afzali-Kusha [email protected]

Low-Power Integrated Circuit Design Section 2: Nanometer Transistors and Their Models

Objective and Outline

• The behavior of the MOS transistor, when scaled into the sub-100
nm regime, is having a large impact on 1) how and 2) where power
is consumed in the integrated circuits.
• Hence, any discussion on low-power design should start with 1) a
good understanding of the nano MOS transistor, and 2) an
analysis of its future trends.
• In addition, the availability of adequate models, for both 1) manual
and 2) computer-aided analysis, are essential.
• Results in this and in the coming sections are based on the Predictive
MOS models, developed by UCB and the University of Arizona, as
well as industrial models spanning from 180nm down to 45nm.
• Whenever possible, MATLAB code is made available on the web site
of the book.

2 Ali Afzali-Kusha [email protected]

Low-Power Integrated Circuit Design Section 2: Nanometer Transistors and Their Models

Objective and Outline

1. Nanometer transistor behavior and models
The section starts with a discussion of the nanometer transistor
and its behavior.
2. Sub-threshold currents and leakage
Special attention is devoted to the leakage behavior of the
transistor.
3. Variability
The increasing influence of variability is analyzed.
4. Device and technology innovations
At the end of the section, we evaluate some innovative devices that
are emerging from the research labs and discuss their potential
impact on low-power design technology.

3 Ali Afzali-Kusha [email protected]

Low-Power Integrated Circuit Design Section 2: Nanometer Transistors and Their Models

Nanometer Transistors and Their Models

• The reduced dimensions make the devices also prone to reliability
failures (problems) such as 1) soft errors (single-event upsets) and
2) time-dependent degradation.
• Their impact is more pronounced in low power designs where the
operational signal-to-noise margins of the circuits is reduced.
• Effects such as 1) variation in performance and 2) unreliability are
more apparent under these conditions (reduced dimensions and
low power (low voltage)).
• It is fair to say that today’s low-power design is closely interwoven
with design for variability or reliability.
• Transistors with 1) higher mobility, 2) steeper sub-threshold slopes,
3) better threshold control, and 4) lower off-currents are
attractive.

4 Ali Afzali-Kusha [email protected]

Low-Power Integrated Circuit Design Section 2: Nanometer Transistors and Their Models

Nanometer Transistors and Their Models

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Low-Power Integrated Circuit Design Section 2: Nanometer Transistors and Their Models

The Sub-100 nm Transistor

From an operational perspective, the main characteristics of
the sub-100 nm MOS transistors can be summarized as follows:
1) a linear dependence exists between gate (and drain)
voltage and drain current (in the strong-inversion region);
2) threshold voltage is a function of channel length and
operational drain voltages; and
3) leakage (both subthreshold and gate) plays a major role.

Each of these issues is discussed in more detail in the following

slides.

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Low-Power Integrated Circuit Design Section 2: Nanometer Transistors and Their Models

The Sub-100 nm Transistor

(Control has come back in independent gate FinFET)

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Low-Power Integrated Circuit Design Section 2: Nanometer Transistors and Their Models

ID versus VDS for 65 nm Bulk NMOS Transistor

• The linear relationship between ID and VGS in the saturation
region is a result of the well-known velocity saturation effect,
which started to impact CMOS transistors around the 250
nm technology generation.
• The main impact is a reduced current drive for a given gate
voltage.
• Simple models of the past are inaccurate.
• We introduce some simplified transistor models of varying
complexity and accuracy.
• Another important effect to be observed from the curves is the
decrease in output resistance (pronounced ID-VD
dependence) of the device in saturation.

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Low-Power Integrated Circuit Design Section 2: Nanometer Transistors and Their Models

ID versus VDS for 65 nm Bulk NMOS Transistor

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Low-Power Integrated Circuit Design Section 2: Nanometer Transistors and Their Models

Drain Current Under Velocity Saturation

• Probably the most accurate model was introduced by Taur
and Ning in 1998.
• One important parameter in this model is the critical
electrical field EC, which determines the onset of velocity
saturation.
• The problem with this model is its highly non-linear nature,
which makes it hard to use in optimization programs (and
hand analysis); for instance, EC itself is a function of VGS.
• Hence, some further simplification is desirable.
• We need above-threshold I-V model for the performance modeling and the
subthreshold region model which is used for the leakage power modeling
where there is no need for the performance modeling in this region.
• In the above threshold region, the dynamic power does not depend of the
current while performance modeling is needed.

10 Ali Afzali-Kusha [email protected]

Low-Power Integrated Circuit Design Section 2: Nanometer Transistors and Their Models

Drain Current Under Velocity Saturation

VDSat has a relation
with 1) EC (function
of VGS) and 2) L.

Saturation voltage

vSat Velocity saturation

11 Ali Afzali-Kusha [email protected]

Low-Power Integrated Circuit Design Section 2: Nanometer Transistors and Their Models

Models for Sub-100 nm CMOS Transistors

• The ‘‘unified model’’ of the MOS transistor was introduced in
[Rabaey'03].
• A single non-linear equation suffices to describe the transistor in the
saturation and linear regions.
• The main simplification in this model is the assumption that velocity
saturation (vSat) occurs at a fixed voltage VDSat independent of the
value of VGS.
• The main advantages of the model are its elegance and simplicity.
• A total of only five parameters are needed to describe the transistor:
k', VTH, VDSat, λ, and g.
• Each of these can be empirically derived using curve-fitting with
respect to the actual device plots.
• Observe that these parameters are purely empirical, and have no or
little relation to traditional physical device parameters such as the
channel-length modulation.
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Low-Power Integrated Circuit Design Section 2: Nanometer Transistors and Their Models

Models for Sub-100 nm CMOS Transistors

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Low-Power Integrated Circuit Design Section 2: Nanometer Transistors and Their Models

Models for Sub-100 nm CMOS Transistors

• Simplicity comes at a cost:
• Comparing the I–V curves produced by the model to those of the
actual devices (BSIM-4 SPICE model), a large discrepancy
can be observed for intermediate values of VDS (around VDSat).
• When using the model for the derivation of propagation delays
(performance) of a CMOS gate, accuracy in this section of the
overall operation region is not that crucial.
• What is most important is that the values of current at the
highest values of VDS (varies) and VGS are predicted correctly
– as these predominantly determine the charge and discharge
times of the output capacitor.
• Hence, the propagation delay error is only a couple of
percents, which is only a small penalty for a major reduction in
model complexity.
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Low-Power Integrated Circuit Design Section 2: Nanometer Transistors and Their Models

Models for Sub-100 nm CMOS Transistors

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Low-Power Integrated Circuit Design Section 2: Nanometer Transistors and Their Models

Alpha Power Law Model

• Even simpler is the alpha model, introduced by Sakurai and Newton
in 1990, which does not even attempt to approximate the actual I–V
curves.
• The values of  and VTH are purely empirical, chosen such that the
propagation delay of a digital gate, approximated by
ܸ݇஽஽
‫ݐ‬௣ =
ܸ஽஽ − ்ܸு a
best resembles the propagation delay curves obtained from
simulation.
• Curve-fitting techniques such as the minimum-mean square
(MMS) are used.
• Be aware that these do not yield unique solutions and that it is up to
the modeler to find the ones with the best fit.
• Owing to its simplicity, the alpha model is the corner stone of the
optimization framework discussed in later sections.
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Low-Power Integrated Circuit Design Section 2: Nanometer Transistors and Their Models

Alpha Power Law Model

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Low-Power Integrated Circuit Design Section 2: Nanometer Transistors and Their Models

Output Resistance
• Reducing the transistor dimensions also lowers the output
resistance of the device in saturation.
• This translates into reduced noise margins for digital gates
(concerns low-power design).
• Three principles are underlying this phenomenon:
(1) channel-length modulation (CLM) – which was also present
in long-channel devices
(2) drain induced barrier lowering (DIBL) – and
(3) SCBE (Substrate Current Body Effect).
• DIBL is a deep-submicron effect and is related to a reduction of the
threshold voltage as a function of the drain voltage.
• DIBL primarily impacts 1) leakage (ܸ‫ = ܵܩ‬0), yet its effect on 2)
output resistance (ܸீௌ > ்ܸு ) is quite sizable as well.
• SCBE (Substrate Current Body Effect) only kicks in at voltages
higher than the typical operation regime, and its impact is hence
not that important.
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Low-Power Integrated Circuit Design Section 2: Nanometer Transistors and Their Models

Output Resistance

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Low-Power Integrated Circuit Design Section 2: Nanometer Transistors and Their Models

Thresholds and Sub-Threshold Current

• With the continuing reduction of the supply voltages, scaling of the
threshold voltage is a necessity as well.
• Defining the actual threshold voltage of a transistor is not simple, as many
factors play and measurements may not be that straightforward.
• The ‘‘physics’’ definition of the threshold voltage is the value of VGS that
causes strong inversion to occur underneath the gate.
• This is however impossible to measure (no access to inversion charge).
1. An often-used empirical approach is to derive VTH from the ID–VGS
plot (in the saturation region) by linearly extrapolating the current in the
saturation region (see plot).
The cross-point with the zero-axis is then defined as VTH (also called VTHZ).
2. Another approach is the ‘‘constant-current’’ (CC) technique, which
defines the threshold voltage as the point where the drain–source current
drops below a fixed value (ID0), scaled appropriately with respect to the
(W/L) ratio of the transistor.
• The choice of ID0 is however quite arbitrary.
• Hence, we use the extrapolation technique, unless otherwise mentioned.
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Low-Power Integrated Circuit Design Section 2: Nanometer Transistors and Their Models

Thresholds and Sub-Threshold Current

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Low-Power Integrated Circuit Design Section 2: Nanometer Transistors and Their Models

Forward and Reverse Body Bias

• The VTH is influenced by a number of operational parameters.
• The foremost is the body-bias (back-bias effect), where the fourth terminal
of the transistor (the bulk or well voltage) serves as an extra control knob.
• The relationship between VTH and VSB requires one extra device parameter,
the body-effect parameter γ.
• Observe that body-biasing can be used either to increase (reverse bias) or to
decrease (forward bias) the threshold voltage.
• The forward-biasing effect is limited, as the source–bulk diode must
remain in reverse-bias conditions (that is VBS < 0.6 V).
• If not, the current is directly injected into the body from the source,
effectively killing the gain of the transistor.
• For the 130 nm technology, a 1V change (-0.5 < VBS < +0.5) in VSB changes
the threshold voltage by approximately 0.2V.
• The beauty of the body-biasing effect is that it allows for a dynamic
adjustment of the threshold voltage during operation, thus allowing for the
compensation of 1) process variations or 2) a dynamic trade-off between
performance and leakage.
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Low-Power Integrated Circuit Design Section 2: Nanometer Transistors and Their Models

Forward and Reverse Body Bias

130 nm

Used in sleep mode where

subthreshold current which is
Used in active mode where
almost exponentially proportional
normally strong inversion current
to VTH should be minimized.
which is almost linearly
proportional to VTH is used.

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Low-Power Integrated Circuit Design Section 2: Nanometer Transistors and Their Models

Evolution of Threshold Control

• Regrettably, scaling of device technology is gradually eroding
the body biasing effect.
• With the doping levels in the channel increasing, changes in
the bias voltage have little effect on the onset of strong
inversion.
• Emerging technologies, such as fully-depleted SOI (in which
the body of the transistor is floating), even do away
completely with the body biasing (no body available in these
technologies).
• This development is quite unfortunate, as this takes away one
of the few parameters a designer can use to actively control
leakage effects.
• But DG-FinFET again offers the control (by providing two
gates).
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Low-Power Integrated Circuit Design Section 2: Nanometer Transistors and Their Models

Evolution of Threshold Control

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Low-Power Integrated Circuit Design Section 2: Nanometer Transistors and Their Models

Impact of Channel Length on Threshold Voltages

• Channel length is another parameter that influences the threshold voltage.
• For very short channels, the depletion regions of the drain (and source)
junctions themselves deplete a sizable fraction of the channel.
• Turning the transistor on becomes easier, thus causing a reduction in the
threshold voltage.
• To offset this effect, device engineers add some extra ‘‘halo implants’’,
which cause the threshold to peak around the nominal value of the
channel length.
• While this is beneficial in general, it also increases the sensitivity of the
threshold voltage with respect to channel-length variations (see the
characteristic for the halo implant on the next slide)
• For instance, it may happen that the channel lengths of a particular wafer
batch are consistently below the nominal value
 This causes the thresholds to be substantially below the expected
value, leading to faster, but leakier chips.

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Low-Power Integrated Circuit Design Section 2: Nanometer Transistors and Their Models

Impact of Channel Length on Threshold Voltages

Vth With halo implants
Long-channel threshold

More sensitivity
(More DIBL)
Lmin L

(for small values of VDS)

Partial depletion of channel due to

source and drain junctions larger in
short-channel devices
Simulated VTH for the parameters of a 90? nm technology

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Low-Power Integrated Circuit Design Section 2: Nanometer Transistors and Their Models

Impact of Channel Length on Threshold Voltages

• Designers vying (competing) for large threshold values with
relatively small variations often size their transistors above
the nominal channel length.
• This obviously comes at a penalty in area.
• The impact can be quite substantial.
• In a 90 nm technology, leakage currents can be reduced by
an order of magnitude by staying away from the minimum
channel lengths.
• Just a 10% increase already reaps (gathers) major benefits.
• This observation has not escaped the attention of designers of
leakage sensitive modules, such as SRAM memories.

28 Ali Afzali-Kusha [email protected]

Low-Power Integrated Circuit Design Section 2: Nanometer Transistors and Their Models

Impact of Channel Length on Threshold Voltages

90 nm

5%

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Low-Power Integrated Circuit Design Section 2: Nanometer Transistors and Their Models

Drain-Induced Barrier Lowering (DIBL)

• Drain voltage is another variable that has a sizable impact on
the threshold voltage.
• The DIBL effect was already mentioned in the context of the
output resistance of short-channel devices.
• As the drain voltage increases, the depletion region of the
junction between the drain and the channel increases in size and
extends under the gate, effectively lowering the threshold
voltage (this is a hugely simplified explanation, but it catches
the main tenet (principle)).  Not correct. It is the
explanation for CLM.
• The most negative feature of DIBL effect is that it turns the
threshold voltage into a signal-dependent variable.
• For all practical purposes, it is fair to assume that VDS changes
VTH threshold linearly, with λd being the proportionality factor.
30 Ali Afzali-Kusha [email protected]
Low-Power Integrated Circuit Design Section 2: Nanometer Transistors and Their Models

Drain-Induced Barrier Lowering (DIBL)

Barrier

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Low-Power Integrated Circuit Design Section 2: Nanometer Transistors and Their Models

MOS Transistor Leakage Components

• An ideal MOS transistor (at least from a digital perspective) 1)
should not have any currents flowing into the bulk (or well), 2)
should not conduct any current between drain and source when
off, and 3) should have an infinite gate resistance.
• Leakage currents, flowing through the reverse-biased source–bulk
and drain–bulk pn junctions, have always been present.
• Yet, the levels are so small that their effects could generally be
ignored, except in circuitry that relies on charge storage such as
DRAMs and dynamic logic.
• The scaling of the minimum feature sizes has introduced some
other leakage effects that are far more influential and exceed
junction leakage currents by 3–5 orders of magnitude.
• Most important are the 1) sub-threshold drain–source and 2) the
gate leakage effects, which we will discuss in more detail.

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Low-Power Integrated Circuit Design Section 2: Nanometer Transistors and Their Models

MOS Transistor Leakage Components

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Low-Power Integrated Circuit Design Section 2: Nanometer Transistors and Their Models

Sub-threshold Leakage
• When the gate voltage of a transistor is lowered below the threshold voltage
‘‘sub-threshold regime’’ (or weak inversion), the transistor does not turn
off sharply.
• The drain–source current becomes an exponential function of VGS.
• The exponential means the MOS transistor behaves as a bipolar device (npn
for an NMOS) with its base coupled to the gate through a capacitive
divider (base voltage for assumed BJT comes from fraction of VGS).
• We know that for an ideal bipolar transistor, the base current relates to the
base–emitter voltage as
α
where k is the Boltzmann constant and T the absolute temperature.
• The so-called thermal voltage (kT/q) equals approximately 26mV at the
room temperature.
• For an ideal bipolar transistor, every increase in VBE by 60mV [= 26mV
× ln(10) = 262.3 = 60mV] increases the collector current by a factor of 10!

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Low-Power Integrated Circuit Design Section 2: Nanometer Transistors and Their Models

Sub-threshold Leakage
• The exponential is somewhat deteriorated by the capacitive coupling
between gate and channel (base)  Not all the gate voltage is coupled to
the channel.
• Hence, the sub-threshold current is best modeled as

where n is the slope factor (due to coupling) ranging around 1.4-1.5 for
modern technologies.
• For the current to drop by one order of magnitude in the sub-threshold
region, the reduction in VGS needed is not of 60 mV, but more like 70–100
mV.
• Sub-threshold currents became an issue with the introduction of the 180 nm
technology node.

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Low-Power Integrated Circuit Design Section 2: Nanometer Transistors and Their Models

Sub-threshold Leakage

swing

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Low-Power Integrated Circuit Design Section 2: Nanometer Transistors and Their Models

Impact of Reduced Threshold Voltages on Leakage

• If the threshold voltage is set, for example, at 0.4V, the leakage
current drops by five (0.4V/80mV/decade) orders of magnitude
between VGS = VTH and VGS = 0 (assuming a subthreshold swing of
approximately 80 mV/decade).
• Assume now that the threshold voltage is scaled to 0.1V
(0.1V/80mV/decade) to maintain performance under reduced
supply voltage conditions.
• The leakage current at VGS = 0 for this low-threshold transistor will be
approximately four orders of magnitude higher than that for the
high-threshold device.

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Low-Power Integrated Circuit Design Section 2: Nanometer Transistors and Their Models

Impact of Reduced Threshold Voltages on Leakage

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Low-Power Integrated Circuit Design Section 2: Nanometer Transistors and Their Models

Sub-threshold Current

60 mV

39 mV

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Low-Power Integrated Circuit Design Section 2: Nanometer Transistors and Their Models

Sub-threshold Current - Revisited

• The simple model of the previous slide does not cover two effects
that dynamically modulate the threshold voltage of the transistor: 1)
DIBL and 2) body biasing.
• While the effects influence the strong-inversion operational mode
of the transistor (as discussed earlier), their impact is felt far more
in the sub-threshold mode owing to the exponential relation
between drain current and threshold voltage.
• The current model is easily adjusted to include these effects with the
addition of two parameters: 1) λD and 2) γD.

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Low-Power Integrated Circuit Design Section 2: Nanometer Transistors and Their Models

Sub-threshold Current - Revisited

Actual voltages
and VTH0 as a device parameter
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Low-Power Integrated Circuit Design Section 2: Nanometer Transistors and Their Models

Sub-threshold Current as a Function of VDS

λd/S  mV/dec for VDS.

1/S  mV/dec for VGS (VTH0)

A huge impact on the sub-

threshold leakage of the
nanometer CMOS transistor.

At the same time, it offers the

innovative designer an extra
parameter to play with.

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Low-Power Integrated Circuit Design Section 2: Nanometer Transistors and Their Models

Gate-Induced Drain Leakage (GIDL)

• In addition, the current flowing through the drain in the off-state
is influenced by the ‘‘gate-induced drain leakage’’ (GIDL)
effect.
• While one would expect the drain current to drop continuously
when reducing VG below VTH for a given drain voltage VD, the
inverse is actually true.
• Especially at negative values of VG, an increase in drain
current is observed.
• This is the result of a combination of effects such as 1) band-to-
band tunneling and 2) trap-assisted tunneling.
• A high value of the electric field under the gate/drain
overlap region [as occurring for low values of VG (0V or lower)
and high VD] causes 1) deep depletion and 2) an effective
thinning of the depletion width of the drain–well junction.
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Low-Power Integrated Circuit Design Section 2: Nanometer Transistors and Their Models

Gate-Induced Drain Leakage (GIDL)

• This effectively leads to 1) electron–hole pair creation and
hence 2) an accompanying drain-to-bulk (and not drain-to-
source) current.
• The effect is proportional to the applied value of VDG.
• The impact of GIDL is mostly felt in the off-state of the
transistor with VGS = 0.
• The upward bending of the drain current curve causes an
effective increase of the leakage current.
• It should be noted that the GIDL effect is substantially larger in
NMOS than in PMOS transistors (by about two orders of
magnitude).
• Also observe that the impact of GIDL is quite small for typical
supply voltages, which are at 1.2V or lower.

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Low-Power Integrated Circuit Design Section 2: Nanometer Transistors and Their Models

Gate-Induced Drain Leakage (GIDL)

 Excess drain current is observed, when gate
voltage is moved below VTH, and moves to
negative values (for NMOS)
 More outspoken for larger values of VDS (or
GIDL ~ VDG)

• Negative VG (turns drain n+ to p) is coupled to the channel side of

the drain inducing a large negative voltage applied to the body 
More reverse bias for the body-drain pn junction.

 High electrical field between G and D causes

tunneling and generation of electron-hole pairs
 Causes current to flow between drain and bulk
 Involves many effects such as band-to-band
direct tunneling and trap-assisted tunneling

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Low-Power Integrated Circuit Design Section 2: Nanometer Transistors and Their Models

Combining All Drain-Leakage Effects

• Most important from a leakage perspective is the current at
VGS = 0 V.
• For low values of VDS, the drain current is set by 1) the sub-
threshold current for the nominal VTH (as well as 2) the
drain–well junction leakage current, which is ignorable).
• When raising VDS, DIBL reduces VTH and causes a substantial
increase in leakage current.
• For instance, increasing VDS from 0.1 to 1.0V causes the drain
current to increase by a factor of almost 8.
• The GIDL effect can clearly be observed for values of VGS
smaller than –0.1 V.
• However, even for VDS at a very high value of 2.5 V, the
impact at VGS = 0 is still ignorable  GIDL hence plays a
minor role in most of today’s designs.
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Low-Power Integrated Circuit Design Section 2: Nanometer Transistors and Their Models

Combining All Drain-Leakage Effects

• It is worth contemplating (considering) the overall picture that
emerges from this.
• For a minimum-sized device in a low-leakage technology with
a VTH around 0.35 V, the drain leakage hovers (moves) around
1 nA at room temperature.
• This amounts to a total leakage current of approximately
0.1A for a design with a hundred million gates.
• This value 1) increases substantially at higher temperatures
(which is the standard operating condition), 2) increases
linearly with the device width, and 3) rises exponentially
with a reduction in threshold voltage.
• Designs with standby leakage currents of multiple Amperes
are hence very plausible and real, unless care is taken to
stop the bleeding.
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Low-Power Integrated Circuit Design Section 2: Nanometer Transistors and Their Models

Combining All Drain-Leakage Effects

90 nm NMOS transistor

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Low-Power Integrated Circuit Design Section 2: Nanometer Transistors and Their Models

Gate Leakage
• Gate leakage got importance once technology scaled below
the 100 nm level.
• One of the attractive properties of the MOS transistor has
always been its very high (if not infinite) input resistance.
• In contrast, a finite base current is inherent to the structure of
the bipolar transistor, making the device unattractive for
usage in complex digital designs.
• To maintain the current drive of the transistor while scaling
its horizontal dimensions, general scaling theory prescribes
that the gate oxide (SiO2) thickness is scaled as well.
• Once however the oxide thickness becomes of the order of
just a few molecules, some significant obstacles emerge.

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Low-Power Integrated Circuit Design Section 2: Nanometer Transistors and Their Models

Gate Leakage
• The very thin oxides also cause a reduction in the gate
resistance of the transistor, as current starts to leak through the
dielectric.
• This trend is clearly illustrated in the chart, which shows the
evolution of the gate thickness and the gate leakage over
various technology generations at Intel.
• From 180nm to 90 nm, the gate leakage current increased by
more than four orders of magnitude.
• Observe also that gate leakage increases strongly with
temperature.
• Unlike sub-threshold currents, which primarily cause an
increase in standby power, gate currents threaten some
fundamental concepts used in the design of MOS digital
circuits.
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Low-Power Integrated Circuit Design Section 2: Nanometer Transistors and Their Models

Gate Leakage

The cross section SEM picture of a 65nm MOS transistor with an oxide thickness of 1.2 nm.

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Low-Power Integrated Circuit Design Section 2: Nanometer Transistors and Their Models

Gate-Leakage Mechanisms
• Gate leakage finds its source in two different mechanisms: 1)
Fowler–Nordheim (FN) tunneling, and 2) direct oxide
tunneling.
• FN tunneling is an effect that has been effectively used in the
design of non-volatile memories, and is already quite
substantial for oxide thickness larger than 6 nm.
• Its onset requires high electric field strengths, though.
• With reducing oxide thicknesses, tunneling starts to occur at
far lower field strengths. 
The dominant effect under these conditions is direct-oxide
tunneling..

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Low-Power Integrated Circuit Design Section 2: Nanometer Transistors and Their Models

Gate-Leakage Mechanisms

Occurring at lower electric

filed when the oxide is thin

Only F-N tunneling

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Low-Power Integrated Circuit Design Section 2: Nanometer Transistors and Their Models

Direct-Oxide Tunneling Currents

• The leakage current is shown to vary exponentially with respect to
both of the 1) applied voltage and the 2) SiO2 thickness.
• This trend clearly threatens further scaling of MOS technology.
• A 1) first approach to address the challenge is to stop or slow down
the scaling of the oxide thickness, while continuing the scaling of
the other critical device dimensions.
• This negatively impacts the I) obtainable current density and
reduces the II) performance benefit that typically comes with
technology scaling.
• Yet, even considering these negative implications, this is exactly
what most semiconductor companies did when moving from 90 to
the 65 nm node (see slide # 51).
• This was a temporary therapy, accompanying the mastering of some
2) quite substantial device innovations such as 1) high-k gate
dielectrics and 2) high-mobility transistors.

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Low-Power Integrated Circuit Design Section 2: Nanometer Transistors and Their Models

Direct-Oxide Tunneling Currents

VDD trend shows the supply voltage
corresponding to that technology.

Temperature dependence
is not shown.

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Low-Power Integrated Circuit Design Section 2: Nanometer Transistors and Their Models

High-k Gate Dielectrics

• The MOS transistor current is proportional to the process
transconductance parameter k' = μCg = μεox/Tg.
• To increase k' through scaling, one must either find a way 1) to increase
the mobility of the carriers or 2) increase the gate capacitance (per unit
area).
• The former requires a fundamental change in the device structure (to be
discussed later).
• Scaling Tg running out of steam.
• Look for gate dielectrics with a higher permittivity – the so-called high-k
dielectrics which keeps the gate leakage under control.
• Device technologists have introduced a metric to measure the
effectiveness of novel dielectrics: the ‘‘equivalent oxide thickness’’ or
EOT, which equals Tg × εox/εg.
• Introducing new gate materials is however not a trivial process change, and
requires a complete redesign of the gate stack.
• In fact, most dielectric materials under consideration today require a metal
gate electrode, replacing the traditional polysilicon gate.
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High-k Gate Dielectrics

• Incorporating major changes of this type (redesign of gate stack) into a
high-yield manufacturing process takes 1) time and 2) substantial
investments.
• This explains why the introduction of high-k dielectrics into production
processes was postponed a number of times.
• Major semiconductor companies such as IBM and Intel have now adopted
hafnium oxide (HfO2) as the dielectric material of choice for their 45 nm
and 32 nm CMOS processes in combination with a metal gate electrode.
• The relative permittivity of HfO2 equals 15–30, compared to 3.9 for SiO2.
• This is equivalent to between two and three generations of technology
scaling, and should help to address gate leakage at least for a while.
• The resulting drop in gate leakage current for the Intel 45nm processor is
apparent.

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Low-Power Integrated Circuit Design Section 2: Nanometer Transistors and Their Models

High-k Gate Dielectrics

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Low-Power Integrated Circuit Design Section 2: Nanometer Transistors and Their Models

High-k Dielectrics

The advantages of high-k

gate dielectrics are faster
transistors and/or reduced
gate leakage.

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Low-Power Integrated Circuit Design Section 2: Nanometer Transistors and Their Models

Gate Leakage Current Density Limit Versus Simulated Gate Leakage

• The expected evolution of 1) gate leakage and 2) gate materials is best
summarized by the chart extracted from ITRS (2005).
• By analyzing the maximum allowable leakage current density (obviously,
this number is disputable – what is allowable depends upon the
application domain), it was concluded that the step to high-k dielectrics is
necessary by around 2009 (the 45 nm technology node).
• Combined with some other device innovations such as FD-SOI and dual-
gate (more about these later in this Section) which reduces another source of
leakage, this may allow for the EOT to scale to around 0.7nm (!), while
keeping the gate leakage current density at approximately 100 A/cm2 (or 1
μA/μm2 (108/108 μA/μm2)) ( see next slide).

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Low-Power Integrated Circuit Design Section 2: Nanometer Transistors and Their Models

Gate Leakage Current Density Limit Versus Simulated Gate Leakage

1) Totally three curves are

shown.
2) Leakage curves are shown
for both limit and what is
expected (simulated) from
technology of planar bulk
and SiON, …
3) EOT is also shown for planar
bulk, UTB FD, and DG.

Expected Jg

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Low-Power Integrated Circuit Design Section 2: Nanometer Transistors and Their Models

Temperature Sensitivity
• In general, it can be assumed that the on current of a transistor reduces
(slightly) with an increase in temperature.
• The 1) decrease in the threshold voltage is not sufficient to 2) offset the
decrease in carrier mobility.  Ion reduction
• The threshold reduction on the other hand has an exponential impact on
the leakage current.
• Hence, higher temperatures are detrimental for the Ion versus Ioff ratio as
demonstrated for a 90 nm NMOS transistor.
• Increasing the temperature from 0 to 100°C reduces the ratio by almost 25.
• This is mostly due to the increase in leakage current (by a factor of 22), but
also to slight decrease in on-current (10%).

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Low-Power Integrated Circuit Design Section 2: Nanometer Transistors and Their Models

Temperature Sensitivity

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Low-Power Integrated Circuit Design Section 2: Nanometer Transistors and Their Models

Variability
• It has always been the case that transistor parameters such as the 1)
geometric dimensions or 2) the threshold voltage are not deterministic.
• When sampled 1) between wafers, 2) within a wafer, or even 3) over a die,
each of these parameters exhibits a statistical nature.
• In the past, the projection of the parameter distributions onto the
performance space yielded quite a narrow distribution.
• Because, when the supply voltage is 3V and the threshold is at 0.5 V, a
25mV variation in the threshold has only a small impact on 1) the
performance and 2) leakage of the digital module.
• However, when the supply voltage is at 1V and the threshold at 0.3 V, the
same variation has a much larger impact.
• So, in past generation processors it was sufficient to evaluate a design over
its worst-case corners (FF, SS, FS, SF) in addition to the nominal operation
point to determine the yield distributions.
• Today, this is not sufficient, as the performance distributions have
become much wider, and a pure worst-case analysis leads to wasteful
design and does not give a good yield perspective (pessimistic one) either.
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Low-Power Integrated Circuit Design Section 2: Nanometer Transistors and Their Models

Variability

models is correct

Temporal and spatial conditions

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Low-Power Integrated Circuit Design Section 2: Nanometer Transistors and Their Models

Variability Impacts Leakage

• While variations influence the high-performance design regime,
their impact is far more pronounced in the low-power design arena.
• First of all, the prediction of leakage currents becomes hard.
• This is illustrated very well in the performance–leakage distribution
plot (for 130 nm technology).
• When sampled over a large number of dies (and wafers), gate
performance varies over 30%, while the leakage current
fluctuates by a factor of 5.
• Observe that the leakiest designs are also the ones with the highest
performance (this should be no surprise).
• In general, low-power designs operate at 1) lower supply voltages,
2) lower VDD/VTH, and () 3) smaller signal-to-noise ratios; these
conditions tend to amplify the importance of parameter variations.

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Low-Power Integrated Circuit Design Section 2: Nanometer Transistors and Their Models

Variability Impacts Leakage

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Low-Power Integrated Circuit Design Section 2: Nanometer Transistors and Their Models

Variability Sources
• Process variations (time = 0) are not the only cause behind the variability.
• It actually originates from a broad set of causes with very different
temporal characteristics.
• In a broad sense, we can classify them into 1) physical (, 1a)
manufacturing (time = 0 and time >> 0),) 2) environmental (, and 2a)
operational) categories (time > 0).
• The 1a) manufacturing variations – that is, fluctuations in 1) device and 2)
interconnect parameters caused by the manufacturing process – are
dominant in today’s designs.
• (Physical) With device dimensions approaching the molecular scale,
statistical quantum-mechanical effects start to play a role, as the ‘‘law of
large numbers (used for current models)’’ starts to be less applicable.
• 2) Environmental and operational conditions are closely related.
• While operating a circuit, some parameters such as 1- the supply voltage,
2- the operating temperature, and 3- the coupling capacitance may
change dynamically as a result of 1. environmental conditions or 2. the
activity profile of the design.
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Variability Sources
(Physics/Manufacturing/Wear-out)

model invalidity

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Low-Power Integrated Circuit Design Section 2: Nanometer Transistors and Their Models

Variability Sources and Their Time Scales

• The most important statistical parameters of concern are 1) the temporal
and 2) spatial correlations.
• If a parameter has a strong spatial correlation (i.e., all devices in the
neighborhood show the same trend), a solution such as global tuning (f(r) ≈
cte.) proves to be effective.
• The same is true in the time domain.
• Very strong temporal correlations (i.e., a device parameter is totally
predictable or may not even change over time) can again be addressed by
onetime or slow adaptation (f(t) ≈ cte.).
• In this slide, we have classified different sources of variations from a
temporal perspective.
• At the slow extreme of the spectrum are manufacturing variations, which
last for the lifetime of the product.
• Almost similar from a lifetime perspective, but entirely different in
nature, are variations caused by wear-out, which manifest themselves
only after a very long time of operation (typically years).

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Low-Power Integrated Circuit Design Section 2: Nanometer Transistors and Their Models

Variability Sources and Their Time Scales

• Examples of such sources are 1) electro-migration, 2) hot-electron
degradation, and 3) negative and positive bias temperature instability
(NBTI/PBTI).
• Next on the time scale are slow 1) operational or 2) environmental
conditions.
• The temperature gradients on a die vary slowly (in the range of 10-3s), and
changes are typically the result of alterations in the operation mode of the
system.
• An example of such is putting a module to sleep or standby mode after a
time of intensive computation.
• Other variations happen at a much faster time scale such as the 1) clock
period or even 2) a single signal transition.
• Their very dynamic nature does not leave room for adaptive
cancellation, and circuit techniques such as shielding (problem
elimination from the beginning) are the only way to eliminate their
impact.

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Low-Power Integrated Circuit Design Section 2: Nanometer Transistors and Their Models

Variability Sources and Their Time Scales

Coming from outside

of the chip/circuit

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Low-Power Integrated Circuit Design Section 2: Nanometer Transistors and Their Models

Process Variations
• Process and manufacturing variations are probably of the most concern.
• The evolutionary trend is clear: virtually all technology parameters such as
transistor 1) length, 2) width, 3) oxide thickness, and 4) interconnect
resistivity show an increasing variability over time (as measured by the
ratio of standard deviation over the mean value).
• Although each of these parameters is important on its own, the resulting
impact on the threshold voltage is what counts most from a digital-
design perspective.
• As shown in the table, the threshold variability is rising from 4.7% to 16%
while evolving from 250nm to 45nm CMOS technologies.
• One may assume that this variation primarily results from the increasing
deviations in channel length, since the VTH is quite sensitive to variations
in L around the critical dimension (remember the halo implants).

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Low-Power Integrated Circuit Design Section 2: Nanometer Transistors and Their Models

Process Variations

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Low-Power Integrated Circuit Design Section 2: Nanometer Transistors and Their Models

Threshold Variations Most Important for Power

• Since the 1) lengths of neighboring transistors tend to be similarly affected
by deviations in the manufacturing process, one would assume that the
threshold voltages of closely spaced transistors should be strongly
correlated.
• This conclusion holds especially for > 100nm technology nodes, where
strong systematic trends in thresholds of local neighborhoods can be
observed (mainly due to the channel length variation).
• However, the observation becomes less true with continued scaling, when
deviations in another device parameter, 2) channel doping, start to become
an issue.
• As shown in the graph, the number of dopant atoms, which is a discrete
number, drops below 100 for transistor dimensions smaller than 100 nm.
• The exact number of dopants in the channel is a random variable, and can
change from transistor to transistor.
• While these variations tend to be mostly systematic today, we may expect
larger random components in the future.

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Low-Power Integrated Circuit Design Section 2: Nanometer Transistors and Their Models

Threshold Variations Most Important for Power

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Low-Power Integrated Circuit Design Section 2: Nanometer Transistors and Their Models

Device and Technology Innovations

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Low-Power Integrated Circuit Design Section 2: Nanometer Transistors and Their Models

Device and Technology Innovations

Easier Fabrication

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Low-Power Integrated Circuit Design Section 2: Nanometer Transistors and Their Models

Strained Silicon
• The concept of strained silicon was introduced by IBM to
increase the mobility in traditional CMOS transistors.
• From the 65 nm generation onward, it is used almost
universally by all semiconductor manufacturers.
• The generic idea is to create a layer of silicon (typically in the
transistor channel), in which the silicon atoms are stretched (or
strained) beyond their normal inter-atomic distance.
• A generic way to create strain is to put a layer of silicon over
a substrate of silicon germanium (SiGe).
• As the atoms in the silicon layer align with the atoms in the
silicon–germanium layer, where the atoms are further apart,
the links between the silicon atoms become stretched – thereby
leading to strained silicon.

79 Ali Afzali-Kusha [email protected]

Low-Power Integrated Circuit Design Section 2: Nanometer Transistors and Their Models

Strained Silicon
• Moving the atoms further apart reduces the atomic forces that interfere
with the movement of electrons through the transistors, resulting in higher
mobility (simplistic justification).
• The practical realization may differ between manufacturers.
• Intel  For NMOS transistors, to stretch the silicon lattice, Intel deposits
a film of silicon nitride over the whole transistor at a high temperature.
• Because silicon nitride contracts less than silicon as it cools, it locks the
silicon lattice beneath it in place with a wider spacing than it would
normally adopt.
• This improves electron conduction by 10%.
• For PMOS transistors, the silicon is compressed.
• This is accomplished by carving trenches along opposite ends of the
channel.
• These are filled with silicon germanium, which has a larger lattice size
than silicon alone and so compresses the regions nearby.
• This improves hole conduction by 25%.
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Low-Power Integrated Circuit Design Section 2: Nanometer Transistors and Their Models

Strained Silicon

The strategy employed by Intel.

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Low-Power Integrated Circuit Design Section 2: Nanometer Transistors and Their Models

Strained Silicon
• The higher mobility may be used to increase the performance
with the same VDD/VTH ratio.
• From a power perspective, a better approach is to use the
higher mobility to obtain the same performance with either a
higher threshold voltage (reducing leakage), or with a lower
VDD/VTH ratio, as is illustrated in next slide.

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Low-Power Integrated Circuit Design Section 2: Nanometer Transistors and Their Models

Strained Silicon

A given leakage A given leakage

A given drive
A given drive

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Low-Power Integrated Circuit Design Section 2: Nanometer Transistors and Their Models

Beyond Straining
• Straining is only one first step toward higher mobility.
• Materials such as Ge and GaAs are known to have an intrinsic
mobility that is substantially above what Si can offer.
• Researchers at various locations are exploring the potential of
so-called hetero-devices that combine Si with other materials
such as Ge, offering the potential of carriers that are 10 times
as mobile, while still relying on traditional Si technology.
• An example of such a device is the Si-Ge-Si hetero-structure
developed at Stanford (this is only one example of the many
structures being investigated).
• While these high-mobility devices will need quite some time
before making it to the production line (if ever), they offer a
clear glimpse at the potential for further improvement.

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Low-Power Integrated Circuit Design Section 2: Nanometer Transistors and Their Models

Beyond Straining

LTO: Low Temperature Oxide

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Low-Power Integrated Circuit Design Section 2: Nanometer Transistors and Their Models

Silicon-on-Insulator (SOI)
• Silicon-on-Insulator (SOI) is a used by AMD and Intel for the 45nm
and beyond technologies.
• An SOI MOS transistor differs from a ‘‘bulk’’ device in that the
channel is formed in a thin layer of silicon deposited above an
electrical insulator, typically silicon dioxide (small series
capacitance).
• Advantages:
1) As drain and source diffusions extend all the way down to the
insulator layer (series capacitances), their junction capacitances
are substantially reduced, which translates directly into power
savings.
2) The higher sub-threshold swing factor (approaching the ideal
60mV/decade), reducing leakage (S = KT/q.ln10.(1+Cd/Ci)).
3) The sensitivity to soft errors is reduced owing to the smaller
collection efficiency, leading to a more reliable transistor.

86 Ali Afzali-Kusha [email protected]

Low-Power Integrated Circuit Design Section 2: Nanometer Transistors and Their Models

Silicon-on-Insulator (SOI)
• Disadvantages:
1) The addition of the SiO2 layer and the thin silicon layer
increases the cost of the substrate material, and may
impact the yield as well.
2) In addition, some secondary effects should be noted.
 The SOI transistor is essentially a three-terminal device
without a bulk (or body) contact, and a ‘‘body’’ that is
floating.
I. This effectively eliminates body biasing as a threshold
control technique.
II. The floating transistor body also introduces some
interesting (ironically speaking) features such as
hysteresis and state-dependency.

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Low-Power Integrated Circuit Design Section 2: Nanometer Transistors and Their Models

Silicon-on-Insulator (SOI)
• Device engineers differentiate between two types of SOI transistors:
1) Partially-Depleted (PD-SOI) and 2) Fully-Depleted (FD-SOI).
• In the latter, the silicon layer is so thin that it is completely depleted
under nominal transistor operation, which means that the
depletion/inversion layer under the gate extends all the way to the
insulator.
• FD-SOI has the advantage of suppressing some of the floating body
effects, and an ideal sub-threshold slope which is theoretically
achievable (depletion layer capacitance is minimized).
• From a variation perspective, the threshold voltage becomes
independent of the doping in the channel, effectively eliminating a
source of random variations (as discussed in Slide: 75).
• FD-SOI requires the depositing of extremely thin silicon layers (3–
5 times thinner than the gate length!).

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Silicon-on-Insulator (SOI)

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Low-Power Integrated Circuit Design Section 2: Nanometer Transistors and Their Models

Example: Double-Gated Fully Depleted SOI

• The FD-SOI device architecture can be further extended with
an extra feature that reinstates threshold control through a
fourth terminal.
• A buried gate below the SiO2 insulator layer helps to control
the charge in the channel, and thus also the threshold voltage.
• As shown in these graphs, the buried-gate concept pretty
much reinstates the idea of body biasing as a viable design
option.
• The reduced impact of random doping variations on the
threshold voltage, as is typical in FD-SOI, is also illustrated.

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Low-Power Integrated Circuit Design Section 2: Nanometer Transistors and Their Models

Example: Double-Gated Fully Depleted SOI

Hitachi

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Low-Power Integrated Circuit Design Section 2: Nanometer Transistors and Their Models

FinFETs – An Entirely New Device Architecture

• The FinFET (called a trigate transistor by Intel) is an entirely different (SOI)
transistor structure that actually offers some properties similar to the ones
offered by the device presented in the previous slide.
• The term FinFET (FD with undoped silicon fin (and some doped extension if it
is bulk FinFET)) was coined by researchers at the University of California at
Berkeley to describe a non-planar, double-gated transistor built on an SOI
substrate.
• The distinguishing characteristic of the FinFET is that the controlling gate is
wrapped around a thin silicon ‘‘fin’’, which forms the body of the device.
• The dimensions of the fin determine the effective channel length of the device.
• The device structure enabled the scaling of the channel length to values that
were hard, if not impossible, to accomplish in traditional planar devices.
• Operational transistors with channel lengths of 7 nm have been demonstrated.
• In addition to a suppression of deep submicron effects, a crucial advantage of
the device is again increased control, as the gate wraps (almost) completely
around the channel  Commercialized @22, 16, 14, 10, 7, and 5nm.

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Low-Power Integrated Circuit Design Section 2: Nanometer Transistors and Their Models

FinFETs – An Entirely New Device Architecture

• TSMC 7 nm fab ramping in 2018, 5 nm in 2019, 3 nm Fab in 2021-2022:

(https://www.nextbigfuture.com/2017/10/tsmc-7-nanometer-fab-ramping-in-
2018-5-nm-in-2019-3-nm-fab-in-2021-2022.html)

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Low-Power Integrated Circuit Design Section 2: Nanometer Transistors and Their Models

BackGated FinFET
• This increased two-dimensional control can be exploited in a
number of ways.
• In the dual-gated device, the fact that the gate is controlling the
channel from both sides (as well as the top) leads to increased
process transconductance.
• Another option is to remove the top part of the gate, leading to the
back-gated transistor.
• In this structure, one of the gates acts as the standard control gate,
whereas the other is used to manipulate the threshold voltage.
• In a sense, this device offers similar functionality as the buried-
gate FD-SOI transistor discussed earlier.
• Controlling the work functions of the two gates through the
selection of appropriate type and quantity of the dopants helps to
maximize the 1) range and 2) sensitivity of the control knobs.

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Low-Power Integrated Circuit Design Section 2: Nanometer Transistors and Their Models

BackGated FinFET

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Low-Power Integrated Circuit Design Section 2: Nanometer Transistors and Their Models

New Transistors: FinFETs

• The fact that the FinFET and its cousins are dramatically
different devices compared to your standard bulk MOS
transistor is best-illustrated with these pictures from Berkeley
and Intel.
• The process steps that set and control the physical dimensions
are entirely different.
• Although this creates new opportunities, it also brings
challenges, as the process steps involved are vastly different.
• Also the adoption of such a different structure impacts
variability, as critical dimensions and device parameters.

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Low-Power Integrated Circuit Design Section 2: Nanometer Transistors and Their Models

New Transistors: FinFETs

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Low-Power Integrated Circuit Design Section 2: Nanometer Transistors and Their Models

Some Futuristic Devices

• It is worth pointing out that the devices described here
represent by no means the complete spectrum of new
transistors and switching devices that are currently being
explored.
• In fact, the number of options that are emerging from the
research labs these days is quite extraordinary, and the
excitement is palpable.
• 1) Most of these will probably die with a whimper, 2) while
other ones are still decades out in terms of true applicability.
• Carbon-nanotube (CNT) transistors seemed to present some
true potential, but it did not.
• When looking from a power angle, some device structures
emerging from the research labs merit some special attention.

98 Ali Afzali-Kusha [email protected]

Low-Power Integrated Circuit Design Section 2: Nanometer Transistors and Their Models

Some Futuristic Devices

• The I-MOS transistor uses substantially different mechanisms, such as
impact ionization, to produce a transistor with a sub-threshold slope
substantially below 60 mV/decade (see next slide).
• This opens the door for a switch with close-to-ideal characteristics.
• The availability of such a device would allow operation at supply voltages
that are substantially lower than what we can allow today.
• Another entirely new device would allow for an almost complete elimination
of leakage current in standby mode:
• Using MEMS (Micro-electromechanical systems) technology, the
suspended-gate MOSFET (SG-MOS) physically moves the actual gate
up and down depending upon the applied gate voltage.
• In the down-position, this device resembles a traditional transistor.
• Moving the gate into the up-position is physically equivalent to mechanically
turning off the switch, effectively squelching all leakage current.
• The availability of such a device would come extremely handy in the design
of low-standby power components.

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Low-Power Integrated Circuit Design Section 2: Nanometer Transistors and Their Models

Some Futuristic Devices

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Low-Power Integrated Circuit Design Section 2: Nanometer Transistors and Their Models

Summary
• For the circuit designer, there are some important takeaways
from this section.
• Scaling into the nanometer regime has some profound
impact on the behavior of the CMOS transistor, both in the
ON and in the OFF modes.
• Simple models that capture the behavior of the transistor in
both modes are available, and will help us in later sections to
build effective analysis and optimization frameworks.
• A profound awareness of the device characteristics and the
ability to adapt to its varying properties will prove to be
essential tenets in low-power design in the nanometer era.

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Summary

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