Sequential Circuits

Sequential logic circuits are systems where the output depends on both the current inputs and the
history of past inputs. These circuits have memory elements that store the previous state. Sequential
circuits require a clock signal to control the timing of state changes. Since the output depends on the
past inputs, this Sequential Circuit also has a memory element.

Components of Sequential Circuits

1. Latches: Latches are simpler memory elements compared to flip-flops. They store a single bit
of data and change their state as long as the control signal (enable) is active.
2. Flip-flops: Flip-flops are basic memory elements in sequential circuits that store a single bit
of data (0 or 1). They have two stable states and can be triggered by a clock signal.
Types of Flip-Flops:
(a) SR (Set-Reset) Flip-Flop: Has two inputs, Set (S) and Reset (R). The output is set to 1 when
S is active and reset to 0 when R is active.
(b) D (Data or Delay) Flip-Flop: Has a single data input (D). The output follows the input at
the clock edge (rising or falling).
(c) JK Flip-Flop: Similar to the SR flip-flop but with J and K inputs. It toggles the output when
both J and K are active.
(d) T (Toggle) Flip-Flop: Toggles the output state on each clock pulse when the input (T) is
active.
3. Counters: Counters are sequential circuits that go through a predefined sequence of states
in response to clock pulses.
4. Registers: Groups of flip-flops storing multiple bits of data, used for temporary data storage
and processing.
5. Finite State Machines: FSMs are computational models consisting of a finite number of
states, transitions between states, and actions based on inputs and the current state. FSM is
the abstract model for describing sequential circuits.
Types of FSMs:
(a) Mealy Machine: Output depends on the current state and input.
(b) Moore Machine: Output depends only on the current state.

Irrespective of the FSM model, the behaviour of the machine can be represented in three different
ways:

i. State Transition Diagram

ii. State Table
iii. State Equations
6. Memory units (RAM and ROM)

Types of Sequential Circuits

There are two types of Sequential Circuits

1) Synchronous Sequential Circuits

2) Asynchronous Sequential Circuits

Asynchronous Sequential Circuits:

The Asynchronous Sequential Circuits respond to the change in the input immediately. In these
circuits, the memory element within the circuit responds to the change in the input immediately.

Synchronous Sequential Circuits:

In these circuits, the memory element within the circuit responds to change in the input only at the
discrete-time intervals. The output state of the memory element changes as per the clock signal.

The Synchronous Sequential Circuits can be further classified into two types:

1) Edge Triggered

2) Level Triggered

Level Triggered Sequential Circuits:

In these circuits, the memory element within the circuit responds to the input, when the clock level
goes high (or low). These circuits are sensitive to the clock level.

Edge Triggered Sequential Circuits:

In these circuits, the memory element within the circuit responds to the input during the clock
transition. (At the rising or the falling edge of the clock signal)

Latch and Flip-Flop

The latch and flip-flop are the basic memory element that stores 1-bit ( 0 or 1) of information.

Since the output of these memory elements has two stable states ( 0 or 1), they are also known as a
bi-stable multivibrator.

Difference between Latch and Flip-Flop:

The Latch is a level-sensitive memory element. It responds to the input level change immediately.
Sometimes it is also known as a transparent latch (because it responds to the change in input
immediately).

The transparent latch with the control input / enable input is known as the Gated Latch. This type of
latch becomes transparent when the enable input is high.

Although Latch behaves as an Asynchronous memory element, it can be used as a Synchronous

memory element by applying the periodic clock signal at the control / enable input.

In this case, still it is level sensitive. Because it responds to the change in the input when the clock
signal / enable input is high. And in this way, it is sensitive to the clock signal level.

The flip-flop is an edge-sensitive memory element. It responds to the input at the clock transitions.
If the flip-flop responds to the input at the rising edge of the clock then it is called a positive edge-
triggered flip-flop. And if the flip-flop responds at the falling edge of the clock then it is called a
negative edge-triggered flip-flop.
SR Latch

The SR latch has two inputs (SET and RESET) for setting and resetting the 1-bit of information.

And it has two complementary outputs Q and Q'.

When S is 1 and R is 0 then latch Sets the output to logic '1'.

When S is 0 and R is 1 then latch Resets the output to logic '0'.

And when both S and R inputs are 0 then latch retain the currently stored information.
In the active high SR latch, S = 1 and R = 1 input combination is forbidden.

In this lesson, the SR latch is designed using NOR gates and NAND gates. And the working of the
latch is explained for the different input combinations.

Gated SR Latch:

The normal SR latch is transparent, because it immediately responds to the change in input .

But the Gated SR latch has control / enable input. When this enable input is high, then only it
becomes transparent to the inputs. In this lesson, the design of Gated SR latch using the NOR gates
and NAND gates is explained. And its working is explained using the timing diagram.
Inputs 1 and 1 are forbidden for NOR gates.
Inputs 0 and 0 are forbidden for NAND gates.

The above latch is a transparent latch, that is, a change in input immediately affects the change in
output. However, by adding two AND gates, a normal (transparent) SR latch can be converted into
the gated SR latch.
In this condition, if the enable input is low, then both the inputs of the latch will remain zero. In that
condition, the latch will retain its present state. When the enable input is high, then will both S and R
reach to the latch; and accordingly the latch will respond to the inputs.

Do not forget that the inputs 1 and 1 are forbidden for NOR gates.
 SR Flip-Flop

Gated SR Latch with Clock

Positive Edge Triggered Flip Flop

Negative Edge Triggered Flip Flop

This explains why the combinations S=1 and R=1 is forbidden.

Initially, the output Q is equal to zero. Therefore, it will remain low until the next falling edge.
State Diagram

State diagram is a pictorial view of the FSM. In a state diagram, each state of the circuit is
represented with a circle. Transition from one state to another is represented with the arrow. The
value on top of the arrow represents the inputs which will lead to the state transition. In a given
state, for each input value, we can only have one possible transition. Each state in the state diagram
must specify what happens for each possible input combination.

Example of a Moore Machine

D Flip flop State Table

State Diagram of D Flip flop

State Table of T Flip flop

State Transition Diagram of T Flip Flop

State Table of JK Flip Flop