Digital Design

Thursday, Apr. 17
Dr. Asmaa Farouk
Assiut University
 Course Overview
• Topics will be covered in this course
– Digital Systems and Binary Numbers.
– Boolean Algebra and Logic Gates.
– Gate-Level Minimization.
– Combinational Logic.
– Synchronous Sequential Logic.
– Registers and Counters..
Lecture # 9, 10

• Reading:
Mano:
Chapter 5.
 Topics of Today
• Sequential Circuits.
• Storage Elements: Latches.
• Storage Elements: Flip-Flops.
• Analysis of Clocked Sequential Circuits.
• State Reduction and Assignment.
• Design Procedure.
 Sequential Circuits
• Digital circuits we have learned, so far, have
been combinational:
– No memory
– Outputs are entirely defined by the “current” inputs.
 Sequential Circuits
• However, many digital systems encountered
everyday life are sequential (i.e., they have
memory):
– The memory elements remember (store) past
inputs.
– Outputs of sequential circuits are not only
dependent on the current input but also on the
state of the memory elements.
 Sequential Circuits
Inputs Outputs
Combinational
Circuit

Current Next
state state

Memory
Elements

– The current state is a function of past inputs and

initial state.
 Sequential Circuits
• Two Types:
1. Synchronous:
• Signals affect the memory elements at discrete instants of
time.
• Discrete instants of time requires synchronization.
• Synchronization is usually achieved through the use of a
common clock.
• A “clock generator” is a device that generates a periodic
train of pulses.
 Sequential Circuits
• Two Types:
1. Synchronous:
• The state of the memory elements are updated with the
arrival of each pulse.
• This type of logical circuit is also known as clocked
sequential circuits.
 Sequential Circuits
• Two Types:
2. Asynchronous:
• No clock.
• Behavior of an asynchronous sequential circuits depends
upon the input signals at any instant of time and the order
in which the inputs change.
• Memory elements in asynchronous circuits are regarded
as time-delay elements.
 Sequential Circuits
• Clocked Sequential Circuits:
– Memory elements are flip-flops which are logic
devices, each of which is capable of storing one bit
of information.
 Sequential Circuits
• Clocked Sequential Circuits:
– The outputs of a clocked sequential circuit come
from the combinational circuit, from the outputs of
the flip-flops or both.
– The state of the flip-flops change only during a
clock pulse transition.
• I.e., low-to-high and high-to-low (clock edge).
• The transition from one state to the next occurs at the
clock edge.
– When the clock maintains its value, the flip-flop
output does not change.
 Topics of Today
• Sequential Circuits.
• Storage Elements: Latches.
• Storage Elements: Flip-Flops.
• Analysis of Clocked Sequential Circuits.
• State Reduction and Assignment.
• Design Procedure.
 Storage Elements: Latches
• Basic types of memory elements are not flip-
flops, but latches.
• A latch: is a memory device that maintain a
binary state indefinitely.
• Latches are, in fact, asynchronous devices and
they usually do not require a clock to operate.
– Therefore, they are not directly used in clocked
synchronous sequential circuits.
– They rather be used to construct flip-flops.
 Storage Elements: Latches
• SR Latch (Set-Reset):
– Made of cross-coupled NOR (or NAND) gates.

Previous
state

Previous
state
 Storage Elements: Latches
• SR Latch (Set-Reset):
– S = R = 1 (OR implementation) may result in an
undefined state.
• The next state is unpredictable when both S and R goes to
0 at the same time.
• It may oscillate, or the outcome state depend on which of
S and R goes to 0 first.
 Storage Elements: Latches
• SR Latch with Enable:
– Control inputs (enable) allow the changes at S and R
to change the state of the latch.
 Storage Elements: Latches
• D (data) Latch (Transparent Latch):
– SR latches are seldom used in practice because the
indeterminate state may cause instability.
– Remedy: D-latches.
– Symbol:
 Storage Elements: Latches
• D (data) Latch (Transparent Latch):
– D-latches can be used as temporary storage.
– The input of D-latch is transferred to the Q output
when En = 1.
– When En = 0 the binary information is stored.
– We call latches level-sensitive devices.
• As long as En remains at logic-1 level, any change in data
input will change the state and the output of the latch.
– Memory devices that are sensitive to the rising or
falling edge of control input is called flip-flops.
 Topics of Today
• Sequential Circuits.
• Storage Elements: Latches.
• Storage Elements: Flip-Flops.
• Analysis of Clocked Sequential Circuits.
• State Reduction and Assignment.
• Design Procedure.
 Storage Elements: Flip Flops
• How does it Work?
– The state of a latch or flip-flop is switched by a
change in the control input (enable).
– This momentary change is called a trigger, and the
transition it causes is said to trigger the flip-flop.
– The D-latch with pulses in its control input is
essentially a flip-flop that is triggered every time the
pulse goes to the logic-1.
– As long as the input pulse remains at logic-1, any
change in the input data will change the output (and
the state of the latch).
 Storage Elements: Flip Flops
• Edge-Triggered D Flip Flop:
– Constructed using two D latches.

Y=D

clk clk

Q=Y=D
D
clk’
Y

Q Negative edge-triggered D flip-flop

 Storage Elements: Flip Flops
• Edge-Triggered D Flip Flop:
– Constructed using two D latches.
Y
D D Q D Q Q
D latch D latch
(master) (slave)
clk’ C C

clk
clk

Positive edge-triggered D flip-flop

 Storage Elements: Flip Flops
• Edge-Triggered D Flip Flop:
– Symbol:
 Storage Elements: Flip Flops
• Other Flip Flops:
– JK flip-flops.
– T flip-flops
 Storage Elements: Flip Flops
• Other Flip Flops:
– JK flip-flops.
• Three operations: Set, Reset and Complement.

J K Q(t+1) next state

0 0 Q(t) no change
0 1 0 Reset
1 0 1 Set
1 1 Q’(t) Complement
Characteristic Table
 Storage Elements: Flip Flops
• Other Flip Flops:
– T flip-flops.
• Toggle or complementing flip flop.

T Q(t+1) next state

0 Q(t) no change
1 Q’(t) Complement
Characteristic Table
 Storage Elements: Flip Flops
• Characteristic Tables:
 Storage Elements: Flip Flops
• Characteristic Equations:
– D flip flop:

– JK flip flop:

– T flip flop:
 Storage Elements: Flip Flops
• Direct Inputs:
– They are used to force the flip-flop to a particular
state independent of the clock.
• “Preset” (direct set) set FF state to 1.
• “Clear” (direct reset) set FF state to 0.
– They are especially useful at startup.
• In digital circuits when the power is turned on, the state
of flip-flops are unknown.
• Direct inputs are used to bring all flip-flops to a known
“starting” state prior to clock operation.
 Storage Elements: Flip Flops
• Direct Inputs:
– They are used to force the flip-flop to a particular
state independent of the clock.
• “Preset” (direct set) set FF state to 1.
• “Clear” (direct reset) set FF state to 0.
 Topics of Today
• Sequential Circuits.
• Storage Elements: Latches.
• Storage Elements: Flip-Flops.
• Analysis of Clocked Sequential Circuits.
• State Reduction and Assignment.
• Design Procedure.
Analysis of Clocked Sequential Circuits
• Goal:
– To determine the behavior of clocked sequential
circuits.
– “Behavior” is determined from:
• Inputs.
• Outputs.
• State of the flip-flops.
– We have to obtain:
• Boolean expressions for the output and the next state.
– Output & state equations.
• State table.
• State diagram.
Analysis of Clocked Sequential Circuits
• State Equations:
– Known as “transition equations”.
– Specify the next state as a function of the present
state and inputs.
Analysis of Clocked Sequential Circuits
• State Equations:
– Example:
Analysis of Clocked Sequential Circuits
• State Tables:
– Example:
• A sequential
circuit with
m FFs and n
inputs needs
2m+n rows in
the state
table .
Analysis of Clocked Sequential Circuits
• State Diagram:
– The state table can be represented graphically in the
form of a state diagram.
– A state is represented by a circle, and the
transitions between states are indicated by directed
lines connecting the circles.
– The directed lines are labeled with two binary
numbers separated by a slash. The input value
during the present state is labeled first, and the
number after the slash gives the output during the
present state with the given input.
Analysis of Clocked Sequential Circuits
• State Diagram:
– Example:
How many states?
m FFs = 2m states.
We have 2 FFs = 4
states.
 Analysis of Clocked Sequential Circuits
• State Diagram:
– Example:
0/0

00 11

1/0

01 10
 Analysis of Clocked Sequential Circuits
• State Diagram:
– Example:
0/0

00 10

1/0 0/1

01 11

1/0
 Analysis of Clocked Sequential Circuits
• State Diagram:
– Example:
0/0 1/0

00 0/1 10

1/0 0/1

01 11

1/0
 Analysis of Clocked Sequential Circuits
• State Diagram:
– Example:
0/0 1/0

00 0/1 10

1/0 0/1 0/0 1/0

01 11

1/0
Analysis of Clocked Sequential Circuits
• Flip Flop Input Equations:
– Example:
• Same as the state equations in D flip-flops.
• Sometimes called “excitation equations”.
Analysis of Clocked Sequential Circuits
• Analysis with D Flip Flops:
– The circuit we want to analyze is described by the
input equation:

• The x and y variables are the inputs.

• No output equations are given, implies that the output
comes from the output of the flip-flop.
Analysis of Clocked Sequential Circuits
• Analysis with D Flip Flops:
– The circuit we want to analyze is described by the
input equation:

– The state equation and state diagram:

Analysis of Clocked Sequential Circuits
• Analysis with JK Flip Flops:
– Goal is to find state equations.
– Method:
1. Determine flip-flop input equations.
2. List the binary values of each input equation.
3. Use the corresponding flip-flop characteristic table to
determine the next state values in the state table.
Analysis of Clocked Sequential Circuits
• Analysis with JK Flip Flops: Example:
Analysis of Clocked Sequential Circuits
• Analysis with JK Flip Flops: Example:
Analysis of Clocked Sequential Circuits
• Analysis with JK Flip Flops: Example:
– Characteristic equations:
Analysis of Clocked Sequential Circuits
• Analysis with JK Flip Flops: Example:
– State diagram:
Analysis of Clocked Sequential Circuits
• Analysis with T Flip Flops:
– Method is
the same:
Analysis of Clocked Sequential Circuits
• Analysis with T Flip Flops:
– Method is
the same:
 Topics of Today
• Sequential Circuits.
• Storage Elements: Latches.
• Storage Elements: Flip-Flops.
• Analysis of Clocked Sequential Circuits.
• State Reduction and Assignment.
• Design Procedure.
 State Reduction and Assignment
• In the design process of sequential circuits
certain techniques are useful in reducing the
circuit complexity:
– State reduction.
– State assignment.
 State Reduction and Assignment
• State reduction:
– Fewer states  fewer number of flip-flops.
– m flip-flops  2m states.
– Example: m = 5  2m = 32.
• If we reduce the number of states to 21 do we reduce the
number of flip-flops?
• Yes, or No.
 State Reduction and Assignment
Note: we use
• State reduction: letters to designate
the states for
– Example: the time being.
1. Get the state table.
 State Reduction and Assignment
• State reduction:
– Example:
2. Inspect the state table for equivalent states.
» Equivalent states: Two states,
• That produce exactly the same output.
• Whose next states are identical.
» Do that for each input combination.
 State Reduction and Assignment
• State reduction:
– Example:
2. Inspect the state table for equivalent states.

After States “e”

removing and “g” are
“g” row, equivalent.
replace One of them
each “g” can be
with “e”. removed.
 State Reduction and Assignment
• State reduction:
– Example:
2. Inspect the state table for equivalent states.

Keep
reducing.
 State Reduction and Assignment
• State reduction:
– Example:
2. Inspect the state table for equivalent states.
 State Reduction and Assignment
• State assignment:
– We have to assign binary values to each state.
– If we have m states, then we need a code with
minimum n bits, where n = log2m.
– There are different ways of encoding.
– The circuit complexity depends on the state
encoding (assignment) scheme.
 State Reduction and Assignment
• State assignment:
– Example: five states: a, b, c, d, e (of Table 5.8).
 State Reduction and Assignment
• State assignment:
– Example: five states: a, b, c, d, e (of Table 5.8).
 Topics of Today
• Sequential Circuits.
• Storage Elements: Latches.
• Storage Elements: Flip-Flops.
• Analysis of Clocked Sequential Circuits.
• State Reduction and Assignment.
• Design Procedure.
 Design Procedure
• Combinational circuits:
– Can be designed given a truth table.
• Sequential circuits:
– We need,
• State diagram or state table.
– Two parts,
• Flip-flops: number of flip-flops is determined by the
number of states.
• Combinational part:
– Output equations.
– Flip-flop input equations.
 Design Procedure
• Procedure:
1. From the word description and specifications of
the desired operation, derive a state diagram.
2. Reduce the number of states if necessary.
3. Assign binary values to the states.
4. Obtain the binary-coded state table.
5. Choose the type of flip-flops to be used.
6. Derive the simplified flip-flop input equations and
output equations.
7. Draw the logic diagram.
 Design Procedure
• Example:
– Verbal description: “we want a (sequential) circuit
that detects three or more consecutive 1’s in a string
of bits”.
– Input: string of bits of any length.
– Output:
• “1” if the circuit detects the pattern in the string.
• “0” otherwise.
 Design Procedure
• Example:
– Step 1: Derive the state diagram.
0
1

S0 /0 S1/0

0 1
0

S3/1 S2/0
1

1
 Design Procedure
• Synthesis Using D Flip Flops:
– Number of flip-flops
• Four states, flip-flops ?
– State reduction:
• Not possible in this case.
– State assignment:
• Use binary encoding:
– S0  00
– S1  01
– S2  10
– S3  11
 Design Procedure
• Synthesis Using D Flip Flops:
– Step 4: Obtain the state table.
 Design Procedure
• Synthesis Using D Flip Flops:
– Step 5: Choose the flip-flops.
• D flip-flops.
 Design Procedure
• Synthesis Using D Flip Flops:
– Step 6: Derive the simplified flip-flop input
equations.
• Boolean expressions for DA and DB.
 Design Procedure
• Synthesis Using D Flip Flops:
– Step 6: Derive the simplified flip-flop input
equations.

Bx
A 00 01 11 10
0 0 0 1 0
1 0 1 1 0

DA = Ax + Bx
 Design Procedure
• Synthesis Using D Flip Flops:
– Step 6: Derive the simplified flip-flop input
equations.

Bx
A 00 01 11 10
0 0 1 0 0
1 0 1 1 0

DB = Ax + B’x
 Design Procedure
• Synthesis Using D Flip Flops:
– Step 6: Derive the simplified flip-flop input
equations.

Bx
A 00 01 11 10
0 0 0 0 0
1 0 0 1 1

y = AB
 Design Procedure
• Synthesis Using D Flip Flops:
– Step 8: Draw the logic diagram.
 Design Procedure
• Excitation Tables:
– Synthesis using flip flops other than D type, is more
complicated.
– We should know the “excitation tables”.

+ +
 Design Procedure
• Synthesis Using JK Flip Flops:
 Design Procedure
• Synthesis Using JK Flip Flops:
Bx Bx
A 00 01 11 10 A 00 01 11 10
0 0 0 0 1 0 X X X X
1 X X X X 1 0 0 1 0

JA = Bx’ kA = Bx
Bx Bx
A 00 01 11 10 A 00 01 11 10
0 0 1 X X 0 X X 0 1
1 0 1 X X 1 X X 1 0

JB = x kB = (A  x)’
 Design Procedure
• Synthesis Using JK Flip Flops:
 Design Procedure
• Synthesis Using T Flip Flops:
– Example: 3-bit binary counter:
• 012 ...  7  0  1  2…
• State assignments:
– S0  000
– S1  001
– S2  010
– ...
– S7  111
 Design Procedure
• Synthesis Using T Flip Flops:
– Example: 3-bit binary counter:
 Design Procedure
• Synthesis Using T Flip Flops:
– Example: 3-bit binary counter:
A1 A0 A1 A0
A2 00 01 11 10 A2 00 01 11 10
0 0 1 1 0 0 0 0 1 0
1 0 1 1 0 1 0 0 1 0
TA1 = A0 TA2 = A1A0
A1 A0
A2 00 01 11 10
0 1 1 1 1
1 1 1 1 1
TA0 = 1
 Design Procedure
• Synthesis Using T Flip Flops:
– Example: 3-bit binary counter:
Questions?