Layout and Post-Layout Simulation tutorial

1. What is a layout?
A layout is a physical representation of an IC's components and
connections. It shows how elements (transistors, resistors etc.) are
placed on the silicon chip and how they're interconnected with metal
layers.
2. Objectives for this tutorial:
● Learn how to use Virtuoso layout editor (by inverter layout)
● DRC checking
● LVS checking
● Run Post-Layout simulation
Learn how to use Virtuoso layout editor
We are going to use inverter as an example for our layout.You can create
(or use an existing) schematic view and symbol view of your inverter before
starting this part

1 Creating a layout view for the inverter design

1.1. Create the new view: By using the Library Manager, under your design library
323002myLib, create the layout view of the inv cell.
· In the File ->New-> CellView Form, select “Layout” as the tool to be used.
2 Introducing the Layer Selection Window (LSW)
Function:
The Layer Selection Window (LSW) shows you which layout layer is being
selected for drawing.

For example：
Let’s say you want to draw a poly gate, you have to highlight the “Poly (drw)” field
in the LSW, hence, what you draw then is for the poly mask.

You should refer to this table for each of the layer types, to know which layer to
use for building different elements in this platform
3 Setting up layout editing window
Some general information listed so that the setting makes senses to you
1. We are using 180nm technology, the description is ‘TSRI 0.18um 1.8V/3.3V
1P6M Virtual Mixed Mode CMOS Process’.
2. Default unit for layout drawing dimension is micro-meter, µm.
3. The design rules (design rules file at the given link on page 2) and the
lambda rule use the value of lambda l = 0.01µm for the given technology.
4. The resolution for mask making, i.e. the smallest dimension achievable, is
0.005µm.
Steps to set up the layout editor window:
1. Check the display option and see whether they are appropriate or not: Click on
Options -> Display
2. The X and Y snap spacing should not be smaller than the smallest dimension
which is 0.005 (i.e. the resolution for mask making).
4 Creating PMOS Transistor Layout
Here is a guide on how to draw the layout of a PMOS transistor step by step
below. In layout view we use polygons to represent transistors and all device
elements.The minimum allowable geometry dimensions are all listed in the Design
Rules file. The value of lambda (λ) is 0.01µm, and the smallest dimension you can
draw is 0.005µm. (Note: the following figures are not drawn to scale)

Here is how each view (layout, cross section and schematic correlate to each other):

Figure show how each of representation resemble a pmos

A overview of the composition of layers and drawing sequence:

 Steps:
1. Drawing with a specific layer: (we draw with poly and active/diff layer)
1.1. The first thing to draw is the polysilicon block; click on the ‘Poly (drw)’ box
in the LSW first.
*Hence any geometry being drawn is on the polysilicon layer then.
1.2. click on Create -> Rectangle to draw the polysilicon gate in the layout
editing window.
1.3. Now we draw the active area (the diff layer)

click on ‘diff (drw)’ in the LSW first.

1.4. Draw the blocks with the dimensions shown with the diff layer

Some tips:
● You can use the Ruler to measure the dimension;
Click on Window → Create Ruler then press F3 for options.
● To remove the Ruler by Window → Delete All Rulers
● You can also use ‘Stretch’ to help you to extend blocks in all
directions by Edit → Stretch
● You can check/change the properties (the size, place & layer) of
rectangles by Edit → Properties.
● More you can use Edit → Quick Align to align objects
● More functions you can always refer to the user guide:
Help -> Layout L user Guide->(a window pops up)->show
documentation browser -> ( find for Virtuoso Layout Suite L
user guide / Virtuoso Layout Suite XL user guide, based on
your Layout editor version )
 2. Draw the remaining structure for the PMOS with the similar way

(*note: typo in picture oxide-> diff)

5 Design Rule Check (DRC)
In order to lower the probability of fabrication defects, the mask layout must conform to
a set of design rules. You should perform DRC frequently while you are drawing the layout.
The tool called Design Rule Checker, which is built into the layout editor, is used to detect
design rule violations.
steps:
1. Use your current layout to run a DRC, Calibre ->Run nmDRC, and the
DRC form will appear. Change the settings below, then click on ’OK’ to
start the checking.

2. It may take some time to finish the checking. As it finished, windows will prompt
out automatically, then click on ‘Yes’ to see the result. If there is error, you have
to correct it at once, and then do the DRC again to verify. The DRC checker (the
Error Layer Window) will tell you what the errors are, and can help you to locate
them. Please ask TA for help if necessary.
3. If there is no error or you have fixed all the errors, you can proceed to the next
part - wiring the transistor.
5 Wiring the Transistor
You now have a PMOS transistor layout, which has passed DRC. Then we will wire
the transistor with Metal 1 and contact.

Note:
To draw the contacts and metal 1 wires as above, you have to determine their
dimension/spacing constraints by checking the design rules of contact layer and metal 1
layer yourself, then undergo DRC to check for any errors, fix them for any.
5 Creating NMOS Transistor Layout
Using the similar procedure as drawing PMOS, draw the NMOS transistor as
shown below and place it below the PMOS transistor. The gate width of PMOS
100λ NMOS should be 50λ. You also need to run DRC, and fix errors if there is
any
 5 Connecting NMOS and PMOS
You have finished the NMOS and PMOS transistors of the inv cell. Make sure
they pass the design rules check (DRC). The next step is to make the internal and
the external connection for the inv layout view

Steps:
1. As above pictures, connect the two transistors’ Poly rectangles together (i.e. their Gate terminals),
and connect the two transistors’ Metal1 rectangles together (i.e. their Drain terminals).
To do so, we can use the Edit ->Stretch to help. Refer to the above pictures for correct
connections.
2. Make connections for external circuit (for input pin A and output pin Out):
Make the interconnection as shown below, determine the dimensions by checking the
design rules of contact, via1, metal 1 and metal 2 layers yourself, then undergo DRC to
check for any errors.
3. Run DRC again and check for any error, and correct them if there are any.
6 Calculate area of layout
To find the area of the layout, select all layouts, click on Design ->Properties,
the coordinates of the boundary box of your layout will be shown.
For example, in this case, the area of the layout is x*y = z µm2. You need to read
the dimensions and calculate the area.
7 Setting layer visibility and selectivity using
LSW
You have basically finished the inv layout. However, you may want to check/look
into the transistor design layer by layer. The Layer Selection Window (LSW)
allows you to set particular layers selectable and visible.

Steps:
1. To make the layers invisible, click on the ‘Metal1 (drw)’ in the LSW. Then click
on ‘NV’ button at the top, then ‘Window’ ->‘Redraw’ in the layout editing
window to refresh the screen.
• Note that except the Metal1 layer all other layers are hidden. To
show the hidden layers, click on ‘AV’ button and click on
‘Window’ -> ‘Redraw’.
(AV: all visible; NV: Not visible)

2. To make the layer unselectable (inactive), move the cursor over the ‘Metal1
(drw)’ in the LSW then click the right mouse button. The function is very
useful if there are too many layers overlapping each other.
• The right mouse button toggles layer selectivity, try it out! If ‘Metal1
(drw)’ field’s background color becomes grey. It means that the layer
has been made unselectable (inactive) in the layout window.

If you right click on it one more time, it will become active again. These
functions can also be applied by clicking on the ‘NS’ and ‘AS’ buttons
(AS: All selectable, NS: Not selectable).
8 Creating Pins in layout view
In the previous part we’ve done the layout and drc check. Now it’s time for us to
locate the ports that have an external connection.

Pins will be defined and drawn, after which the layout design will be
complete. Pins locate where to connect from a cell/instance/block to the
‘outside world’ (external connections), and different names are given for pins of
different purposes. There are total 4 pins in our inverter, i.e. on the inv
schematic view, they are vdd!, gnd!, A and Out.
Steps:
● In LSW, select the layer ‘M1_text’ (this is a key step!). ‘M1_text’ stands for
pin text defining on Metal 1 layer.
● In the layout editing window, press ‘l’ and this form pops up,

● In the Create Label form, type in the pin’s name ‘vdd!’, then attach the
label to the layout on the specific location to mark where are the ports of
this subcircuit
● To create pin for gnd!, A, and Out in the same way.
9 Layout versus Schematic Check (LVS Check)
You are ready to carry out the Layout versus Schematic Check (LVS). It is an
important step because the layout drawing is based on its schematic, the devices’
dimensions and connection in the layout should be consistent with that in the schematic.
In order to ensure the layout design is matched with its schematic view totally, the layout
versus schematic check (LVS) must be performed.

The layout view represents the circuit topology, which consists of layers of
rectangles only! How can the system recognise devices and their connectivity in the
layout view? While LVS is running, Cadence will look for the technology file which
contains the electrical rules. These rules define structures, for example if overlapping
poly layer, Nimp layer and Oxide layer are present, that will be considered as a NMOS
transistor. Therefore, gates and electrical connections are traced out and identified from
their layout view. Only then the layout and schematic views can be compared.
Steps:
10 Standard-cells based design
We have built an inverter in our 323002myLib library.
We encourage you to try to design a buffer and a NAND2 gate( nand gate with 2
inputs)
Then, let say you have design your nand2 and buffer you should have a library of
different cells.

You can call and reuse your layout of these cells in higher level designs, for example
a 2 stage buffer consisting of 2 inverters. You can reuse the inverter layout 2 times to
reuse
All the cells’ layouts should be designed with a fixed height so that they can be
abutted side by side to form rows for sharing a common power and ground bus.
Moreover, these fixed height cells can enable automated placement and routing of cells.
11 circuit extraction from layout
Circuit extraction is performed after the layout design is completed. The
circuit extractor generates an extracted view from a layout view. What is the use of
the extracted view? The circuit extractor is able to estimate actual devices’
dimensions, interconnections and the parasitic components present between
layers from the layout view, this information is then stored in the extracted view.
Thus, the resulting circuit simulation results obtained from its extracted view are a
better estimation of the circuit’s real performance.

Steps:
1. Open the layout view of the inv cell.
2. Although you did LVS before, you have to perform LVS again everytime
before doing the extraction.
3. Export gds: File→export→stream→inv.gds
4. As LVS finished, click on Calibre à Run PEXs,
5. Change the content in Rule.rce and make sure Rule_08KA and Rule_20KA is in
the same directory as Rule.rce. Change source path, source primary, layout path,
and layout primary.
As the extraction finished, in CIW, the message shows that there is an av_extracted
view stored under your inv cell. Open this newly created view and see what it is.
12 Post-Layout Simulation of the inverter design
We use the extracted view to run the post-layout simulation. The netlist
generated from the extracted view includes the parasitic components inevitably
present between layers. Therefore, the resulting simulation results provide a
better estimation on its real performance. You did the schematic circuit
simulation on inv .In this part, you will run the post-layout simulation. You
should compare the results to those obtained from pre-layout simulation (with
netlist obtained from schematic)

Steps:
1. Use the same testbench hspice code that you have written for the
Inverter schematic design.
2. Then change the included file by
Ex:
.include "the_extracted_circuit_file.pex.spi"
This is the file with all the parasitic elements extracted from the layout
3. Check the pins order and modify the testbench: sometimes the pin
order of the subcircuit extracted is different from the pin order of the
netlist extracted from the schematic, Hence it’s crucial to check the order
of the pins
4. Now you can compare the waveform between presim and postsim and
comment on the differences observed.
Appendix I: More about LVS
If the LVS checker reports that the schematic and layout do not match each
other, you have to find, check and correct the errors.

To know what is unmatched, you have to understand the terms used in the debug
window:

Instance - The instance of devices in ‘layout’ and in ‘schematic’.

Unmatched instances - The instance of devices in ‘layout’ and in
‘schematic’ do not match with each other.
Rewired instances - LVS recognizes that a better match can be made by
switching the terminal connection of an instance from one net to another.
This is referred to as a rewired terminal. For this to occur, many of the
instances and nets in the local region must have already matched. This kind
of error occurs when two nets are cross-wired. The LVS program
interchanges the connection and continues processing.
Size errors – Size Difference in W & L values, LVS compares transistors’ W
& L values only when the instances are matched with each other in its
schematic and layout. Any unmatched instances will not be compared.

Pruned instances - You may ignore this error.

Nets – interconnection node.

Merged nets - A second class of unmatched nets is the merged nets. In
some cases, LVS recognizes that two nets need to be “shorted” together to
improve the comparison. This occurs when many of the instances attached
to the nets have already matched. When two nets need to be merged in the
extracted representation, it indicates the possibility of an open. When two
nets are merged in the schematic representation, it indicates the possibility
of a short in the layout.

Pruned nets - You may ignore this error.

Terminals – pins for input, output and power.

Unmatched terminals - Terminals (Pins) that failed to match in layout as
compared to those in schematic.