EXPERIMENT NO.

AIM: WAP To design a butter worth low pass and high pass filters for the given specification.

PROGRAM:
%butter worth low pass filter%
clc;
rp=input('Enter the pass band ripple');
rs=input('Enter the stop band ripple');
wp=input('Enter the pass band frequency');
ws=input('Enter the stop band frequency');
fs=input('Enter the sampling band frequency');

w1=2*wp/fs;
w2=2*ws/fs;
[n,wn]=buttord(w1,w2,rp,rs);
[b,a]=butter(n,wn,'low');

w=0:0.1:pi;
[h,om]=freqz(b,a,w);

m=20*log10(abs(h));
an=angle(h);

subplot(2,1,1);
plot(om/pi,m);
Ylabel('gain in db');
Xlabel('normalized frequency');
subplot(2,1,2);
plot(om/pi,an);
Xlabel('normalized angle');
Ylabel('phase in radians');

INPUT:
Enter the pass band ripple .6
Enter the stop band ripple 51
Enter the pass band frequency 1203
Enter the stop band frequency 2503
Enter the sampling band frequency 12030

OUTPUT PLOT
 EXPERIMENT NO. 6

AIM: WAP To design a butter worth band pass and band stop filter for the given specification.

PROGRAM:
%butter worth band pass filter%
clc;
rp=input('Enter the pass band ripple');
rs=input('Enter the stop band ripple');
wp=input('Enter the pass band frequency');
ws=input('Enter the stop band frequency');
fs=input('Enter the sampling band frequency');

w1=2*wp/fs;
w2=2*ws/fs;

[n]=buttord(w1,w2,rp,rs);
wn=[w1,w2];
[b,a]=butter(n,wn,'bandpass');

w=0:0.1:pi;
[h,om]=freqz(b,a,w);

m=20*log10(abs(h));
an=angle(h);

subplot(2,1,1);
plot(om/pi,m);
ylabel('gain in dB');
xlabel('normalized frequency');
subplot(2,1,2);
plot(om/pi,an);
xlabel('normalized angle');
ylabel('phase in radians');

INPUT:

Enter the pass band ripple .36

Enter the stop band ripple 36
Enter the pass band frequency 1503
Enter the stop band frequency 2030
Enter the sampling band frequency 6030

OUTPUT PLOT:
 EXPERIMENT NO. 7

AIM: Write a program to design a Chebyshev – I low pass filters to given specification.

PROGRAM:
%Chebyshev low pass filter%
clc;

rp = input('Enter the pass band ripple');

rs = input('Enter the stop band ripple');
wp = input('Enter the pass band frequency');
ws = input('Enter the stop band frequency');
fs = input('Enter the sampling band frequency');

w1=2*wp/fs;
w2=2*ws/fs;

[n,wn] = cheb1ord(w1,w2,rp,rs);
[b,a] = cheby1(n,rp,wn);

w = 0:0.1:pi;
[h,om] = freqs(b,a,w);
m = 20*log10(abs(h));
an = angle(h);

subplot(2,1,1);
plot(om/pi,m);
Ylabel('gain in db');
Xlabel('normalized frequency');
subplot(2,1,2);
plot(om/pi,an);
Xlabel('normalized frequency');
Ylabel('phase in radians');

INPUT:

Enter the pass band ripple .6

Enter the stop band ripple 45
Enter the pass band frequency 1030
Enter the stop band frequency 2503
Enter the sampling band frequency 12030

OUTPUT PLOT:
 EXPERIMENT NO. 8 (A)

AIM: Write a program to design a low pass FIR filter using Rectangular Window

PROGRAM:

% rectangular window low pass filter %

clc;
clear all;
close all;

N=input(‘Enter the value of N:’);

wc=input(‘Enter cutoff frequency:’);

h=fir1(N,wc/pi,rectwin(N+1));
freqz(h);

INPUT:

Enter the value of N:28

Enter cutoff frequency: 0.5*pi
OUTPUT PLOT:
 EXPERIMENT NO. 8 (B)

AIM: Write a program to design a low pass FIR filter using Blackmann Window

PROGRAM:

% Blackmann window low pass filter %

clc;
clear all;
close all;

N=input('Enter the value of N:');

wc=input('Enter cutoff frequency:');

h=fir1(N,wc/pi,blackman(N+1));
freqz(h);

INPUT:

Enter the value of N:28

Enter cutoff frequency: 0.5*pi

OUTPUT PLOT:
 EXPERIMENT NO. 8 (C)

AIM: Write a program to design a low pass FIR filter using Hamming Window

PROGRAM:

% Hamming window low pass filter %

clc;
clear all;
close all;

N=input('Enter the value of N:');

wc=input('Enter cutoff frequency:');

h=fir1(N,wc/pi,hamming(N+1));
freqz(h);

INPUT:

Enter the value of N:28

Enter cutoff frequency: 0.5*pi

OUTPUT PLOT:
 EXPERIMENT NO. 8 (D)

AIM: Write a program to design a low pass FIR filter using Hanning Window.

PROGRAM:

% Hanning window low pass filter %

clc;
clear all;
close all;

N=input('Enter the value of N:');

wc=input('Enter cutoff frequency:');

h=fir1(N,wc/pi,hanning(N+1));
freqz(h);

INPUT:

Enter the value of N:28

Enter cutoff frequency: 0.5*pi

OUTPUT PLOT:
 EXPERIMENT NO. 9
Aim: Introduction to DSP Processor.
A signal can be defined as a function that conveys information,
generally about the state or behavior of a physical system. There are two basic types of signals viz
Analog (continuous time signals which are defined along a continuum of times) and Digital
(discrete-time).
Remarkably, under reasonable constraints, a continuous time signal can be adequately
represented by samples, obtaining discrete time signals. Thus digital signal processing is an ideal
schoice for anyone who needs the performance advantage of digital manipulation along with today’s
analog reality.
Hence a processor which is designed to perform the special operations (digital
manipulations) on the digital signal within very less time can be called as a Digital signal processor.
The difference between a DSP processor, conventional microprocessor and a microcontroller are
listed below.
Microprocessor or General Purpose Processor such as Intel xx86 or Motorola 680xx family
Contains - only CPU
-No RAM
-No ROM
-No I/O ports
-No Timer
Microcontroller such as 8051 family
Contains - CPU
- RAM
- ROM
-I/O ports
- Timer &
- Interrupt circuitry
Some Micro Controllers also contain A/D, D/A and Flash Memory
DSP Processors such as Texas instruments and Analog Devices
Contains - CPU
- RAM
-ROM
- I/O ports
- Timer
Optimized for – fast arithmetic
- Extended precision
- Dual operand fetch
- Zero overhead loop
- Circular buffering
-

ARCHITECTURE OF 6713 DSP PROCESSOR

This chapter provides an overview of the architectural structure of the TMS320C67xx DSP, which
comprises the central processing unit (CPU), memory, and on-chip peripherals. The C67xE DSPs
use an advanced modified Harvard architecture that maximizes processing power with eight buses.
Separate program and data spaces allow simultaneous access to program instructions and data,
providing a high degree of parallelism. For example, three reads and one write can be performed in a
single cycle. Instructions with parallel store and application-specific instructions fully utilize this
architecture. In addition, data can be transferred between data and program spaces. Such
Parallelism supports a powerful set of arithmetic, logic, and bit-manipulation operations that can all
be performed in a single machine cycle. Also, the C67xx DSP includes the control mechanisms to
manage interrupts, repeated operations, and function calling.
The C67xx DSP architecture is built around eight major 16-bit buses (four program/data buses and
four address buses):
_ The program bus (PB) carries the instruction code and immediate operands from program
memory.
_ Three data buses (CB, DB, and EB) interconnect to various elements, such as the CPU, data
address generation logic, program address generation logic, on-chip peripherals, and data memory.
_ The CB and DB carry the operands that are read from data memory.
_ The EB carries the data to be written to memory.
_ Four address buses (PAB, CAB, DAB, and EAB) carry the addresses needed for instruction
execution.
The C67xx DSP can generate up to two data-memory addresses per cycle using the two auxiliary
register arithmetic units (ARAU0 and ARAU1). The PB can carry data operands stored in program
space (for instance, a coefficient table) to the multiplier and adder for multiply/accumulate
operations or to a destination in data space for data move instructions (MVPD and READA). This
capability, in conjunction with the feature of dual-operand read, supports the execution of single-
cycle, 3-operand instructions such as the FIRS instruction. The C67xx DSP also has an on-chip
bidirectional bus for accessing on-chip peripherals. This bus is connected to DB and EB through the
bus exchanger in the CPU interface. Accesses that use this bus can require two or more cycles for
reads and writes, depending on the peripheral’s structure.

Central Processing Unit (CPU)

The CPU is common to all C67xE devices. The C67x CPU contains:

_ 40-bit arithmetic logic unit (ALU)

_ Two 40-bit accumulators
_ Barrel shifter
_ 17 × 17-bit multiplier
_ 40-bit adder
_ Compare, select, and store unit (CSSU)
_ Data address generation unit
_ Program address generation unit

Arithmetic Logic Unit (ALU)

The C67x DSP performs 2s-complement arithmetic with a 40-bit arithmetic logic unit (ALU) and
two 40-bit accumulators (accumulators A and B). The ALU can also perform Boolean operations.
The ALU uses these inputs:

_ 16-bit immediate value

_ 16-bit word from data memory
_ 16-bit value in the temporary register, T
_ Two 16-bit words from data memory
_ 32-bit word from data memory
_ 40-bit word from either accumulator