8bit ALU Sourcecode
8bit ALU Sourcecode
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 09/24/2024 10:46:28 PM
// Design Name:
// Module Name: ALU
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module ALU(
input [7:0] a,b,op,
output [7:0] x,
output [3:0] flag
);
reg [7:0] temp;
always@(a or b or op)
begin
flag[3]=0;
flag[1]=0;
case(op)
3'b000:
begin
{flag[1],x} = a+b;
flag[0] = x[7];
flag[2] = (x==0)?1:0;
flag[3] = ((a(7) == b(7))&(x[7] != a[7]))?1:0;
end
3'b001:
begin
temp = ~b +1;
{flag[1],x} = a+temp;
flag[0] = x[7];
flag[2] = (x==0)?1:0;
flag[3] = ((a(7) == b(7))&(x[7] != a[7]))?1:0;
end
3'b010:
begin
x=a&b;
flag[0] = x[7];
flag[2] = (x==0)?1:0;
end
3'b011:
begin
x=a|b;
flag[0] = x[7];
flag[2] = (x==0)?1:0;
end
3'b100:
begin
x=a^b;
flag[0] = x[7];
flag[2] = (x==0)?1:0;
end
3'b101:
begin
x=a|b;
flag[0] = x[7];
flag[2] = (x==0)?1:0;
end
3'b110:
begin
x=a<<1;
flag[0] = x[7];
flag[2] = (x==0)?1:0;
end
3'b111:
begin
x=a>>1;
flag[0] = x[7];
flag[2] = (x==0)?1:0;
end
endcase
end
endmodule