DEVICE MODELING © Te ET D.C, MODELS, SMALL SIGNAL MODELS, MOS MODELS, — MOSFET MODELS IN HIGH FREQUENCY AND SIMALL — SIGNAL, SHORT CHANNEL DEVICES, SUB THRESHOLD OPERATIONS, MODELING NOISE SOURCES IN MOSFETs eT Q.t What do you mean by device modeling 2? (RGR, June 2016) Or Eyplain the chart that explains the approach to device modelling. (R.GP.V., May 2019 tins, The aimof'device modeling is to get the functional relationship between the terminal electrical variables of the device which is to be modeled. These electrical characteristics based on a parameter set containing geometric variables and variables dependent upon the device physics. Design parameters or process are all variables which appear in the equations. The design parameters controlled by the circuit designer. The characteristic of the semiconductor process are process parameters itself and are not at the control of the circuit designer once the process has been specified. At best only a good approximation to the real relationship of the electrical variables can be found, for most physical electrical ‘Accurate High and Low Frequency Model Appropriate for Computer Simulation ignal Equivalent Fig. 2.0Ans. Modeling — Models ~The D.C. model of a * the actual terminal voltages and currents at C. model of a device must be valid over a large problem under inv short note on small signal model. in purposes. For di tgnal Values. the following conve total variab aan upper case variable signal value Device Modeling 57 ygnal analysis V, is considered to be periodic with perio ined by — pent L(t =2fy ver ah signal variable isthe time varying component ofV,. Fig. mn between Vo, V, and y, :SB VIS! Desge (VikSem} Device Modeling 59 There are S10 we low frequency small signal 5 replacing point as shown in f ermined from the process, due plenty formed by parameters measured from an actual process Parameters | NMOS | PMOS. 7e7 yor O7 KP 8x 10% }25x 10% GAMMA [04 05 036 037 LAMBDA | 001 1D oe Purposes and may TOX 2 ofa circuit NSUB__}2Cevice Medeing 61 s have been don: 2 LEVELS) modeling which is needed for CMOSE " termed a the panial derivative of ly fermined from equation (i) to be Vos 7 Vos~ Yr Vpps causes the channel Pinch off For Ving > V dependent of Vg) at . Hence. this value is determin, n (i) at Vps = Veg ~ Ve to iin Fh. Discuss the model of lm frequency channel MOSEEE on i = Stes - Vr? state the governing equations. > Vo5-Vy i ne a ey 57 Vos = Na and Vos > Vr The eon of opera in 21s, = 4s termed the saturation region. Ip snot dependent of Ving, Tae portion of the curve in the third quadrant of fig. 2.5. where Ving © dashed. Equation (i) is no longer v ~08V ‘pn junction, becomes rg brased, causing considerable bulk current to flow. The MOSFET termed Sah’s mod: forsai fl based upon equation (1) and equation (iv) ‘The drain current in the saturat channel length, W is the channi Fesmscondacuunce parameter and V; is the threshold voltage. nore accurate expression for the drain current in the saturation region is . in obtained as ~ kw ; Ip = “3p Was ~ Vr)" 1+ Nps) Vs > Vos ~ Vr-Vos > Vr ‘The MOSFET model defined by equation 2.6. It should be noted that all pro quadrant 2 intersect the Vps axis at ‘The threshold voltage Vz is somewhat based on the b This dependence can be anticipated since the bulk-channel v the camers in the depletion region under the gate, which in tum affect the ‘oltage that must be applied to the gate 10 form the inversion layer. This dependence is obtained as ~ Vr = Vro+1Qo- Ves ~ where Vag is the bulk-source voltage and Vip. and @ are process parameters Vo = Threshold voltage for Vs = 0 +y = Bulk threshold parameter @ = Strong inversion surface potential You? Yosy> Ver? Vet ven or 2 MOSFET as given by equation (i) is fig. 2.5 for several values af Vgs. The portions ofee re NS TEE 2. VLSI Design (Vil-Sem.) Device Modeling 63 , i ther physi i The transconductance parameter Ki is defined in terms of other physicg | js " H 8 gradually changing function of process parameters by position avy) as shown in Bip. 27, The distance of the order of the insulator KI [Cog } thickness Cox is, mensional Poi here C,, = Capacitance density of the gate-channel capacitor, and ws} forthe semiconductor is or sons equation where Coy = C s Channel mobility. hs >> af ‘A summary of the MOSFET model for n-channel devices which is enough ox aye, @ for most D.C. hand calculations appears in table 2.2. where, Fx and Ey ae oe and ¥ components of the electric field in the Table 2.2 Low Frequency n-channel MOSFET Model Span, & is the ic permittivity of the semiconductor and Sharge density in the channel. GCA is valid under the assumption OF, Vas Vrs Vps > Ves - Ys : Kw 4A las > Vt» Vs > Vos = Vr i ap (Was = V2)" 2N09) (saturation) a z ‘Semiconductor z eal bere Vr= Waa + 15-05 — J) = i ee Ditmar 1 if (a) Dimensions and Fietd (6) Variation of Channel Potentiat ne, Gok Besa Direction in MOSFET Fig. 2.7 “The eross sectional view of an n-channel MOSFET is shown in fig. 2.8. At the surface end x = 0 and at the ddain end x =L. The potential atthe source i. the channel potential is represented by Vo(x) and Q, is the total surface charge density induced into the semiconductor considering a situation in whi device operates in the above threshold region and an inversion Fig. 2.8 Cross Sectional View of layers present, the induced surface ‘an n-channel MOSFET charge density Q, is given by Q.= —CoxlVa -268 — Ven ~ VeO)) V(x) is the channel voltage and $f, Vp Will form the components of the threshold voltage later which is constant along the entire channel re Equation (iii) can also be written as ~ Qe= ~S28[Vo -2¢F Vin ~ Ve] Gal tox Fig. 2.6 Q.7. Draw and explain the ouput characteristic curve for n-channel MOSFET. (RGRY., May 2019) Ans, Refer to the ans. of Q.6. Q.8. Explain gradual channel approximation used to calculate the + MOSFET current-voltage characteristics. fms. Gradual Channel Appr nation — Gradual channel approximation wee characteristics of MOSFET. It Shockley. GCA is based on the assumption that the ated to the vari leetric charge density rel Petpendicularto the semiconductor insulator interface. Thereforvery small as com ex OF. | go Fis dominant according «© OC* Ournest ge Vet) (source grounded) to the boundary conditions forthe channel voll Vein = 0) = Ve= 9 Vex == Vos fo the entire channe! region Vos due to the inder the by the drift 0! 2Vr Also it By The channel current Ip is ree to dra ce induced density of fee elect med by deducting the surface layer Qp from the total induced charze Qs me q 4q ‘The depletion yor charge density B= HS Qp (x= 0)= -\4QNa En OF charge of accepto and is given by. From equation (vil) We the semiconductor surface is bending between the bulk of the semi 26p * Ve as the induced n-channel. Voltage Vetx). The band as-Vo) (a) Source Side (b) Drain Side 2.9 Energy Band Diagram of MOSFET ppared to the Vaniay ‘electron charge in thiy oon n,_ at each point of the channel cay in the depletion ady seen that the total band bending 2p and else where in the channel the total band | vonductor substrate and the surface iy strate junction is reverse biased by diagram at the source side and at the drain side j assumptions leag t t f } =A Device Mode 2.9. We obsene the increase ing 65 pow in ig. 2.9. 0a opeene ie nsteas of the band bending in the show? Fgetion from the source 1 drain (26, ~ Ve(a)), Ths rool channel in depletion layer charge density and eae iru ; ” (Vit) modifies Q(x = 0) = ~V2EgaN AWC) =O_) ‘the channel potential V(x) provides an adit iqayeed rchannel substrate junction, ae “The drain current Ip is writen as Ip= aH,W.n, YE the low field clecon ob i sanere Bis the TOW ctron mobility, n, is des “rons $0 thatthe electron Velocity is proportional to the component ofthe oct field Fy in the channel parallel to the semiconductor insulator interface tor imerface sin the in increas (vi) reverse bias for the as given by Va = BaF. snstuence the electrical properties of the device at large values of dran to source bias. irain to Equation (ix) can be written as ~ = wean Ip Integrating equation (xi) in the channel region ic, from 0 (a L(adain, we getthe arcane de tee eaiatc aeee fe f° seat ae “ oc (Xi) «f® Cc . WL= Jy aha WEB Cves ~20p- Ven Veo) 22 ve AWC, Ip= eatiCon{(ves -267-Ven- “oWvp -2|(seaay 32 age 2}} ci Al cam } owen -26e7"7] (i) Equation (xii) shows the current-voltage characteristics as obtained by gradual channel approximation. Fig. 2.10 shows the current-voltage characteristics of MOSFET as obtained by gradual channel approximation (CGA).65 Cox Oxide capacitance, « potential () is aterm which accounts for the upon a forthe doping ofthe substrate, ich represents te difference between the Fermi energy level ofthe doped whit onductor and the Fermi energy level of ic semiconductor. Th semicmpotscen the valence-band edge and n-band edge of ibe dearer to the nearer tothe \e source of an Mf ely drops "since the carrier ° the gate-oxide Sapueitance, which is inversely proportional to the gate-onide thickness (.) the permittivity of silicon (1.06 » 10-1? Farads/em), The kis ine Boltzmann's constant (1.380 x 10-3 JK) and T is the temperature (°K) and q is the electronic charge (1.602 » 10-!” Coulomb). Expression KT/q equals 0.02586 volts at 300°K. Threshold voltage (Vo) is positive for n- rransistors and negative for p-transistors, Expression of the flatband voltage (Vpy) is given as ~ y,) of an MOS tra voltage ( i one smal Iso depends on the tet oe a ee imperfections in the silicon oxide interface and doping. ‘ms ~ Work function difference between the gate material and the silicon substrate (p21. ~ i) Which may be calculated for an ni gate over a p substrate, and is given by ~ The threshold voltage (V,) vey, ij 15 m3 threshold volta 4s = “(Eg /2+4)=09V(N, = 110! em) where, B,= Band gap energy of silicon, * calculated by considering the MOS capacitor structure which makes the galé T+1108 T= Temperature in Kelvin. For an n* polygate on an n-substrate - bos * -(-+)- ~02V(Nq =1x10"em™)68 VLSI Design (Vil-Sem) 114s observed from these equations that for a given gate and subst. material, the threshold voltage can be varied by changing the doping concentration of the substrate (Na). the oxide capacitance (Coy). oF state charge (Qye)- 0.10, Explain different method to control threshold voltage of MOS devieg ‘Ans, The value of threshold voltage (V,) for the p-channel standayy is common to use a power-supply voltage oy the power, polar in s. Henge, jeveloped to control V;. General smaller switching time owing «)higher packing densitic, ings reshold voltage, following three methods to the smaller voltage swing To control the magnitude of feshold MOSFET described above uses a silicon crystal he <100> direction, iti observed that a value i found with orientation. mately 2, icon doped with boron ference in contact potential reduces threshold voltage, low-threshold 2.5V, whereas the standard {approximately 4 to 6V. the thermal noise. Assume operation in the saturation region. (R.GPV, Dec. 2016) has zero mean. Itis Dovico ic and saturation regions, the nee oo J by the spectral density as given below — _ 2K rK'Ipg Cet (uy ns (i) and (ii) for saturs 8kTEm _ 2KrK'lpg 3 Col? T noise curre ion region, we pet Sm= YT vito! «w) tions (iv) and (¥), equation 3 K'Ky (vez) f ( v a Mie Iuis seen that the relative impact of the thermal noise and flicker noise are strongly dependent on the quiescent operating point and the device size 4? Draw and explain all the MOSFET models for digital applications with the help of a suitable diagram, (RGPS:, Dee. 2015, 2017) Ans, Many digital applications involve large numbers of gates and transistors which make hand analysis using the device models. This type of of necessity, not provide highly accurate results. A very simple t makes hand analysis tractable is needed for these applications F the MOSFET used for simple analysis of digital circuits are shown 21 In fig. 2.11 (a), the S, switch is open when Ves « Viy/2 and closed wher Ves > Vyl2 here Vj, is the logical high voltage in the digital logic family and where the logical low voltage is considered to be near zero, The values of and From equal L L a KW - T. R where V> = Threshold voltage of MOSs c s o ). These models are used for DD > Rp " sos o ) Fig. 2.10 0.13. Derive expressions for simple MOSFET models for digital applications. Explain derivations for the simple digital inverter. (R.GPY., Dec. 2016) source connected to. oad resistor of some short connected from drai all conditions are considered ‘or. It is also considered Rohde inverters without degrading the requirement is metie., V,,= V, = 0.5 Vpp is set for det [At this point, both the transistors are ita EN is given by cement mode (p.d. transistor), V,, = V, W, 2 luge Kea Wing Vo MZpa. = Lpa/Wpe, 2Nd Zp, ~ Lpy/Wp us then the equal (Vine VW? (Wu)? 2 = Zn: Thus, Va Zou! Zpa QJFDraw and explain small-signal MOSFET model. (RGR, Dec. 2013, June 2017) approximated as linear for small changes around a bias for understanding the behaviour of amplifiers and other analog circuits. The currents and voltages can be written as Ves = Vos + Ves Vas = Vos tas wwe commonty wrie te sexatnvitics 25 Ya EnX ye” Fae = = Mas -%) Mei ats and becante the sauration correct is ideally independent of Vigy : ati nF =6 iL) a bigeVon This Taylor series spproe gives the same results as the direct expansioe in equation (ii). __ ba real MOSFET, the output current docs increase with V,, because | ey eC neh length modulation. Ven Fig, 2.14 Bias-point and Smalt-signal BehaviowrDevies Madetng 75 =0 _ mensconductance 8 expresses the relatio {._and the input voliage V,, and is defined by aship between ourput 2 dle. Bon AyiMes = Constant ris used to measure the gain of an MOS device. In the linear region js given BY Ee Sextzears = BVes inthe saturation region by, Bates) = BV. V) Fig. 215 Small ing, princl is 3 Draw a high frequency model of MOS transi ; 5. Explain the operating principle of MOS transistor at D.C. QAT. Dra ransistor and derive the eS -maleiimial (RODS, Dec Soya | equation Jor iS transconductance Ce) and ranstion frequeny 3 ia yr aah ee = ee Draw ahigh frequency model of MOS transistor and derive the equation Q.16. Draw low frequency small-signal model of MOS transistor ang “por its transition frequency (fj). mnductance (B_)- Or Explain the high frequency MOSFET model. (RGPV., June 2015, Dec. 2015) ‘Ans, At high frequency, small signal models of the MOS transistor is generally considered inadequate. These limitations are to a large extent Snributable to the unavoidable parasitic capacitances inherent in capacitances can be divided in ; vi] i 1a, = Bg - VVan- 2 |0< Vas < Ves Vy in source conductance ce in the linear region can be rit < of -. A CHF «w ity of the dielectric material separating the p 1 to combine £/d into a single parameter C,, called the CHCA 4) thus a process parameter and A is a design parameter.Device Modeling jw be of tteknes 9 77 represents the perm of free space. nd Caso Tepresent the gate-drain and gate spectively. Their existe source overlap nce can be atribuled to Seren ied to the undes me ofthe impunis used generate te dare .. This diffusion causes a small reduce in the effective leah or Mentors. If Ly is the distance feral most diffusion undes rin path of these parasitic capacitors are nearly rectangular with enue i wh Lp, fesulting in a eapacitance of 7 Cop0= Caso=CaWLp ) Cgq:is the gate-to-channel capacitance. For the cut-off region, the channel Oe ned. $0 Cgc =O. For the ohmic region, the channel is quite uniform, mng from drain-to-source under the entire gate region. For this region, ene gate-to-hannel can be expressed as ~ ae Coc= CWE i) typically assumed that half of Cg¢ directly from gate-to-source and ihe other half from gate-to-drain to simply calculations when the device is "ing in the ohmic region. For the saturation region, the majority of the | area behaves as an ohmic extension of the source region. Typically rant depending Upon the mood for - 25 Ve S Op?2 Seurce/Body ‘Model for MOS Transistor Fig. 2.¢,, WL is modeled as a lumped element between gate and source, and the “The relation between the small signal parameter like transconductance 3 1 : ince high cut-ol frequency can be given by remaining ~Cox WL is neglected, 2 Cop is the gain-bulk capacitance. For the cut-off region, the inversion layer does not exist, so the bulk region extends to the bottom side of the gate Q.18. Derive a relation for MOSFET models in high frequency for ide layer and Cgp = CoxWL. Can becomes voltage dependent and reduces small signals. (RGR, June 2018 | ith bias when operating in cubofT with a depletion region present in the Gps fo the ens oF Q1I7. 4 channel, The existence of the inversion layer makes Cgp essentially zero for ‘ | both the saturation and ohmic regions. A small gate-bulk capacitance associated Q.19. What is the role of parasitic capacitors in MOS transistors for with gate material overlapping the bulk w jth the thick field oxide as a dielectric channel device ? Explain with suitable diagram. (R.GPV, May 201) does exist. 4s. Fig. 2.17 shows the parasitic capacitors in MOS transistors for Cpc1 Fepresents the bulk-to-channel junction capacitance. For the cute off region, the inversion layer does not exist, causing Cyc to vanish. For both the ohmic and saturation regions, a junction capacitance, from the bulk-to- -apacttor values are operating region dependent. Moreover, some ; od tt 2. is n 5 e sment modeling, the 535 and 5:0 i¢ cupatitors are actually distributed devices. channel exists. To maintain lumped element modeling, 72 3 15 the capacitance density of the gate/oxide/channel capacitor. If Eg les are used in the ohmic and saturation regions, respectively, to distribute the relative permituvity of the silicon dioxide dielectric, which is parasitic capacitance between the drain and source. Em fre ae. 2nCs78 VLSI Design (Vi-Se7) 2.17 are representeg buted capacitors Coe. an fig. 2.18 ( between the drain and source nodes, | bave been lumped and sj tors 2.18 (c) shows the s 2 the capacitive parasitic. The resistors Rp and Re have been inch ce in the drain and source regions from ns to the m I drain (D') and source of the device. These resistors become quite large for large physical drain (a) bumped Sodet Device Modeling 79 ivalent Cire Capacitance (c) Small Signal Eq Fig. 2.18 Paras 0.20. Explain the method for measurement of and RG ¢ drain current Dec. 2013)2 represents dal ne parameter 4 7 Nos - Vr and deters “Sod ips are the and V'psp- then, wena 5 Belpful Sand Vigs are fined so that Vos > Vy ay "2 relationship Vo = —IpR ww If Vps; 9nd Vso are the ty son (1) and Voi and Wo2 tespectygy e inputs, then we get Voz = Vou [Vor Vbs2 ~ Yo2 Vosi] Vpst a Fig, 2.19 Fig. 2.20 rom asurement of K'= It follows from equation (i) that K'can be calculated roma measurement of Ip for fixed values of Vos and Vg from the equation bi Device Modeling 51 — Woes Vy}(iravpg) The circuit of fig. 2.20 is again helpful for measunng K! 9.21. Explain short channel devices, ges aud limitations. K'= oN) a Aso ment is eptestion, antag GPK, 20" sas, The minimum MOSFET device lengths has eee ih 0.5 1 range oF below are projected by carly 1990s. For shorter channel jengths, the model is gradually deteriorate. Transistors with channel leneths rs iro uae rlerrd oa shor enrages the vertical and lateral dimensions is reduced with short channel devices, Geometrically. there is the change in the channel region from thin right rectangular region to irregular structure. Short channel transistors give some te icc ane transistors but have some limitations Improvements in speed and reduced area needs which are attainable with circuit employing short channel transistors are the important advantages. In the output impedance characteristics, deterioration js the major drawback. Better matching of short channel transistor characteristics is more complex to achieve. The comparison of the output characteristics area oe eueeasl oad ant channel is shown in fig. 2.21 A simple model of the MOSFET which is necessarily an extension of the tong channel mode! in given by the following equations — Fig. 2.21 Ig=0 ti) 0, Vgs < Vr(cut-off) K'Wer(y _y- Vos gp. { Ex Slee ii {ves ve “BS Nog] 1 +4{ Sr Vo, p= Vos > Vr.0< Vps < Vos - Vr i) Wry | {ota} 2M Vos VP] 1+ vos area [ OLer «itty Vos > Vr-Vps > Vos ~ Vr (saturation)az vit Design (VSM) Effective = Effective chat ne} width. vives are used easily obtainable f high ovtpul impedance and gis Bog coef the improvernent frequency respon ng characteristics 2 c s find some uses in spit Bea kxplain in bri subthreshold with the Or shold operations with the help of sui (GRY, June 2044 ¢ MOSFET, the drain current f0F posit onzero for Vy. > Vy In yi anticipated and does not take plage drain current is much smaller for Vix 3V 1» the term ¢~ Yds! Yr in equation (ii), and we find the equivalent of strong inversion saturation region of operation. Often Vp, = 0. Under the assumption that V,, = Oand V4, > 3V;. equation (ii) becomes as ~ 1,=0 1 =X of¥e Volta) need ‘of Vg. Parameter I is However, it is often the case that power supply restrictions operation of subthreshold devices with smaller values related to the transconductance parameter and ts approximately given ss ~4 VLSI Design (Vil-Sem) _ k2nVp)? e There are many practic: imitations of devices operating in weak inversion. First, the frequency response of dev operating far into weak inversion is poor. This can be qt seen by observing that the F device capacitance © jg, 2.23 Typical ly-Vax Chardcterisic, ly determined ae Jor MOSFET Operating in Subthreshoyy sed in aximum current avi char, a i roading 10 a significant deterioration gy "and source substrate Currents ASSociateg te junction are not essentially negligip rd, the linearity is Very poor fo lenging. Fourth, deterioration oy easing drain current, eee lable to charge and di strong inversion mod these capacitors is sii frequency response. Second, ¢ reine revere biased moat-subst jd drain currents. T xr designs more chi ‘es of MOS transistors with deer <3, makin ing, chara further complicates linear design. ns, it is often desirable to operate near the Nveen strong, inversion and weak inversion, where some + associated with weak inversion can be ions are not too problem: transition region > of the advantages of reduced powe! obtained but where these other limita diffusion current dominates weak trong inversion operation, both mechanisms interact in the tran region icate the modeling problem. 9.23. Derive a relation for the subthreshold operations, How we can "implement this operation on short channel devices ? (R.GRY, Dec. 2015, June 2017, Dec. 2017) Ans, Refer to the ans. of Q.22 and Q.21. 0.24. Explain the subthreshold operation when MOSFET operating in weak inversion. (R.GR¥., May 2019) Ans. Refer to the ans. of Q.22. Q.25. What do you mean by modeling noise sources for MOSFET ? (R.GP, June 2019, Or Explain in detail modeling noise sources in MOSFET. (GP. June 2017) In MOSFETS, flicker noise and thermay S. In either the smal ‘ontribute to the total de inal or large the source 8 current, as ise model can be modeled as deviet quse these noise Sources c fg. 2-24 (a). | Device Modoing a5 Drain) j | i Sate) Source (S) (b) Fig. 2.24 -the thermal noise current is white noise, which has ze spy eharactrized by its spectral density as given below — come ae are G vi Siw= | Rrer eam) 8kT Em FI (Saturation segion) where, Rye ~ Equivalent FET resistance T = Temperature in °K. K = Boltzmann’s constant Sm ~ Small signal transconductance, In the ohmic region and saturation region, flicker noise current sacterized by the spectral density — 2K sK'Ipg Colt Ipg = Quiescent current Ky = Flicker noise coefficient f = Frequency Coy, L_ = MOSFET model parameters, ‘The spectral current density of noise current source Iy can be determined by adding Sipand Spy as given below ~ Sy = Siw + Sir cha Sie where86. VLSI Design (Vil-Sem.) ¢ frequency band [1 & .d from the spectral density and mh noise current source eg, cen by ~ In deter Inne { J, fe RMS Hicker noise and wl Aiof the spectral densities ~ syot Itis noted that, if' we defi by the square root of the lw. Ivo = yliva + fF 26, How noise sources are modeled? Iustrate with an exampie m (BGP, Dec. 2014, June 2,5 | 25 and sol. of Prob.1. Hence, “Ans. Refer to the ans. of Q. Nyssa cele simple transconductance amplifier. Determing the output noise eurrent spectral density, the Voainh npur-referred voltage spectral density and the RMS ouput thermal noise current, the RUS output flicker noise current, the output RMS noise current, and the input-referred RMS noise voltage in the flat frequency band from 100 Hz 10 1 MHz if the small signal input v, is zero, Suppose W=5 1s L= 5 Hh Veg = 2¥, Kyp= 3x 107107F Sot Observe that the MOSFET is operating in the saturation region since ps = Vp > Vos ~ Vr. Then we get kw 5 Jno = Sp (ose ~ Vr)” = 18.75 na pein, J2K'W. See Jipg =30.0nA/V Siw = 33 « 107 A2 see Device Modeur 154% 19719 ing 87 Syp= IO” 2 T see 154 x 19719 A see Iwn= ff e we Lie sivarscas ss lp = [pe or Alizsear= sy nA(RMS) Tenia Vm gh =43 HV (RMS) ©" pIODE MODELS, BIPOLAR MODELS, passive COMPONENTS MODELS | YE Sy = 33x 10-25 and 0.27. ‘Ans. Diode is the most basic of semiconductor devices, When two diffusions of opposite polarity form a junction, a janction diode made or a Schottky diode is generated. Only ohmic contacts are formed in Tost CMOS processes, where metal contacts diffusions. In an nMOS (or pMOS) transistor, the source and drain terminals form np (or pn) j Giodes to the substrate (or well). Fig. 2.26 shows the schematic symbol for a junction diode. The two terminals are designated the anode and cathode = 5 Fig. 226 0.28. Explain the D.C, model for diode. (RGR, Dec. 2013) Ans, Fig, 2.27 shows the V/I characteristics of a diode. In a diode, the current is expressed as ~ av. 1= Agl, |e - | w What do you mean by diode models ? Camode a Anode ppwned os veneer Sede feed High Frequency Diode Made! — pos & Ss po fancies tece eepacmance mace by te becomes Seen nhs Epes noeies Dy 2 Sapacaor cummed berween te seme of we hake of { Cyr ji ve ee c= *3 Joac_ | 20¥ P Corl oa ve $e 0.30. How the circuits and signals get affected by changing the circuit low frequency t0 high frequency ? Explain. (RGPV., Dec. 2015) Ans. Refer to the ens. of Q29. 9.31. What is meant by bipolar model ? ‘Ans. Fig. 2.28 shows the apa acd pop bipolar transistors and the convention for the electrical variables. The following model development is The arem aipidly . pesircied to the npa transistor. The pap development will be identical with the 3 Cnception of siga changes in some of the equations. & © c ¥ =A ey vec fie vic fie + _ + ag sea a ne oy =~ ve the ve the LED. Explain the following ~ 7 - Small rignsl tiode model B E (ii) High frequency diode model (a) npn () pop Am. iy Small Signal Diode Model ~ In low frequency small 2.28 Convention for Electrical Variables of BIT Trans spicata diode is rarely used aad like a small signal model requirement me90 VLSI Design (Vil-Sem) 3 so svt stie= (RGR. Dec. x, C. model for BIT. 0.32. Explain the D. seminal variables in Ebers ang 4} ynship among the term Ma j 2 Device Moaeling 91 of fig. 2.29 serves as an equivalent ci reads sat y the standard diode eg ee it where the currents model is given by the fo ns. BIT is operated in forward in forward active mn. When Vine ~ 0-5 Vand Vic “0.3 V then the emninal variables singly signal reverse current gain of common base “ Fewrig rand current gain of common Base Configuaya p= Large signal fo Ig =IgelYor'™s Here, T= Absolute temperature k= Boltzmann’s constant 4 = Charge of electro : : two equations along with KCL and KVL applied tothe transis, s convenient 10 use Ie and ly rather than Ic and Iy as the dependent if modeling the BIT. Br is given by F oe sariables i =aore Be I-ap efit) Ic and Ip can be written as = Ige(oe/M0 Tp) Vee = Var ~ Vac ‘The BIT is characterized by these four equations. From equations (j) and Wy) aS (bev) Br the device moda | calculates the ap and ag parameters, and as such | hase to the collector with the gain rela are process parameters. The transport saturation Io =Brlp avi) current can be determined as — Is =JgA, Here, A= Area of the emitter Js = Transport saturation current density. Js parameter can be expressed as, Js=qD,n7/Q5 Similarly, if By is described as then, Where, D,, = Average effective electron diffusion constant Qu = Number of doping atoms in the base per unit area 1, = Instrinsie carrier concentration in silicon Aix) Base-to-emitter current gain in the reverse active region is given as lollows ~ Pele Fishes ote7 7 92. VLSI Design (Vil-Sem } the high frequency diode model which explain the bipoy, miidel circuits for D.C. BJT model. (RGR June 2044, Ans. High Frequency Diode Model ~ At high frequencies, the paras. jjunetion capacitance of the diode playsa important role in the diode performang. and also effects the transient response. The small sign can be expressed as follows — BuOE Wp ‘The characterization of a junction capacitance under forward bias different from the characterization under reverse bias, Under reverse bias (fy, Vp < FC.$p), Cp is given by Coe A, = Normalized cross-sectional area of the function Gp = Zero-bias junction capacitance I, = Saturation current ince barrier potential where, FC = Coefficient for forward/reverse bias transition m = Coefficient of grading ‘Therefore. term of the equation (i) is essentially functionally equivalent to that used in the junction capacitance model for the MOSFET. The I" term of the equation (i) increases from the charge stored in the junction because of minority carrier injection. Under forward bias (for Vp > Fc. bn): Cp is given by the equation from on Ve Tem 4" Term C= The 1 term of the equation (ii) indicates a continuous and differentiable linear entension of the P term of equation (i) across the boundary Vp = FC. The I™ term of the equations (i) and (ii) are indentical, D.C. BJT Model ~ Refer to the ans. of Q.32. ; De in the high frequency dod, MCE Modlin le modet wij 0 93 pla 3 Expl : He Suitable exampy, eter HE ANS: FO.29 and Q.34, GRY, stay 2019) Ai rte SHOT! note 0M Smal Signal modes, 36g small signal model can be obiained dirty Bur, s. TM signal applications, the BIT is biaseg Tom the DC. mod ,j small signal model will be restricted 1g ee in th folector current Ie and base current jy eae e ISA Wor/vy Br tne BIT is modeled as a three terminal deve, al «iy et Bees oe BIT. The base and collector © 10 obtain the small viel for BIT. F nodes of the Bi go met emitter node by B. The parameter yy «BIT ate denoted by and ip te model. This is given by y the dominant pee verte ae a OVpe |Yae=Vorg Veo=Veug a i a IgA e¥ae9!¥0) fins (2 } a IAL I, Neco v Var then Fig. 2.30 shows the small signal model equivalent circuit and the small signal model parameters for BJT is given i (a) ¥-parameter Modelwr 94 vis! Desiga (Vii-Sem) bie rer Model (a parame! Cre | Parameters for BJT sail Signal Model Fig, 2.30 Sm Table 23 ¥- parameters ramneter a en =e by =BF Yeb = Sm vi Be. | =p.-8m Beve yee =82 » = Yee Be smsponent models. (R.GPN, May 2019, Nov. 2o1y ements are very simple to model. Ideal capaciten, rs respectively. Temperate he major disadvantages, both applications via judiciog i resistors and capacitors are temperature and imits the practical range of values. Lang | practical. Figures of merit, which are used components are given below — = Write short note on passive CO} 5 @)_ Capacitance or resistance density (@) Voltage coefficients of capacitance or resistance (i) Texoperature coefficients of capacitance or resistance IW) Relative accuracy of capacitance. (si) Absolute accuracy of capacitance. 34 Explain im brief the following — @ Manolakic capacitors (@ Monolithic resistors. (RGR, June 2015 Tear | p-base Diffusion apitasiat Tars are used for resistors in bing, | Iy base diffusion is used "| 96 VLSI Design (Vil-Sem.) pitaxial strips linear. Mo _ A contact is red _juncti and voltage. Diffusion strips oF <1 zs devices are quite esistane ‘¢ collector ed to the epitaxial in. A base diffused regi processes. The: its reasonably high sheet r to stop forward biasing of the shown in fig. 2.31. is